ASoC: sdm660_cdc: Update volatile register set for cache bypass

Update the volatile register set for cache bypassing. Set
only required registers as volatile and others as
non volatile in order to enable register read from
cache.

CRs-Fixed: 2031818
Change-Id: Ib53798a3f81fc133f6f3902f7bac750cca1cabc6
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>

diff --git a/sound/soc/codecs/sdm660_cdc/sdm660-regmap.c b/sound/soc/codecs/sdm660_cdc/sdm660-regmap.c
index fff1fdc..c9babac 100644 (file)
--- a/sound/soc/codecs/sdm660_cdc/sdm660-regmap.c
+++ b/sound/soc/codecs/sdm660_cdc/sdm660-regmap.c
@@ -452,8 +452,23 @@ bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg)
 bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg)
 {
        switch (reg) {
-       /* cache bypass for initial version */
-       default:
+       case MSM89XX_CDC_CORE_RX1_B1_CTL:
+       case MSM89XX_CDC_CORE_RX2_B1_CTL:
+       case MSM89XX_CDC_CORE_RX3_B1_CTL:
+       case MSM89XX_CDC_CORE_RX1_B6_CTL:
+       case MSM89XX_CDC_CORE_RX2_B6_CTL:
+       case MSM89XX_CDC_CORE_RX3_B6_CTL:
+       case MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG:
+       case MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG:
+       case MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG:
+       case MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG:
+       case MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG:
+       case MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL:
+       case MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL:
+       case MSM89XX_CDC_CORE_CLK_MCLK_CTL:
+       case MSM89XX_CDC_CORE_CLK_PDM_CTL:
                return true;
+       default:
+               return false;
        }
 }