[AMDGPU][MC][DOC] Updated AMD GPU assembler description

Stage 2: added detailed description of operands

See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349368 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/docs/AMDGPU/AMDGPUAsmGFX7.rst b/docs/AMDGPU/AMDGPUAsmGFX7.rst
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+++ b/docs/AMDGPU/AMDGPUAsmGFX7.rst
@@ -0,0 +1,1411 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+============================
+Syntax of GFX7 Instructions
+============================
+
+.. contents::
+  :local:
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Introduction
+============
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+DS
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**         **SRC0**      **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    ds_add_rtn_u32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_u64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_u32                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_u64                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_u32                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_u64                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_b32                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_b64                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_rtn_b32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_rtn_b64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_src2_b32                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_src2_b64                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_append                      :ref:`vdst<amdgpu_synid7_vdst32_0>`                                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_b32                               :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata32_0>`,   :ref:`vdata1<amdgpu_synid7_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_b64                               :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata64_0>`,   :ref:`vdata1<amdgpu_synid7_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_f32                               :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata32_0>`,   :ref:`vdata1<amdgpu_synid7_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_f64                               :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata64_0>`,   :ref:`vdata1<amdgpu_synid7_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_b32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata32_0>`,   :ref:`vdata1<amdgpu_synid7_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_b64               :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata64_0>`,   :ref:`vdata1<amdgpu_synid7_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata32_0>`,   :ref:`vdata1<amdgpu_synid7_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_f64               :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata64_0>`,   :ref:`vdata1<amdgpu_synid7_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_condxchg32_rtn_b64          :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_consume                     :ref:`vdst<amdgpu_synid7_vdst32_0>`                                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_rtn_u32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_rtn_u64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_src2_u32                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_src2_u64                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_u32                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_u64                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_barrier                             :ref:`vdata<amdgpu_synid7_vdata32_0>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_init                                :ref:`vdata<amdgpu_synid7_vdata32_0>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_br                             :ref:`vdata<amdgpu_synid7_vdata32_0>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_p                                                                 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_release_all                                                       :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_v                                                                 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_rtn_u32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_rtn_u64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_src2_u32                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_src2_u64                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_u32                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_u64                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_f32                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_f64                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_i32                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_i64                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_f32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_f64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_i32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_i64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_u32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_u64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_f32                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_f64                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_i32                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_i64                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_u32                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_u64                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_u32                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_u64                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_f32                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_f64                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_i32                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_i64                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_f32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_f64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_i32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_i64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_u32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_u64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_f32                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_f64                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_i32                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_i64                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_u32                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_u64                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_u32                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_u64                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_b32                               :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata32_0>`,   :ref:`vdata1<amdgpu_synid7_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_b64                               :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata64_0>`,   :ref:`vdata1<amdgpu_synid7_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_rtn_b32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata32_0>`,   :ref:`vdata1<amdgpu_synid7_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_rtn_b64               :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata64_0>`,   :ref:`vdata1<amdgpu_synid7_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_nop
+    ds_or_b32                                  :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_b64                                  :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_rtn_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_rtn_b64                  :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_src2_b32                             :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_src2_b64                             :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_ordered_count               :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2_b32                   :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b32x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2_b64                   :ref:`vdst<amdgpu_synid7_vdst128_0>`::ref:`b64x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2st64_b32               :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b32x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2st64_b64               :ref:`vdst<amdgpu_synid7_vdst128_0>`::ref:`b64x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b128                   :ref:`vdst<amdgpu_synid7_vdst128_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b32                    :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b64                    :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b96                    :ref:`vdst<amdgpu_synid7_vdst96_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i16                    :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i8                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u16                    :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u8                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_rtn_u32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_rtn_u64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_src2_u32                           :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_src2_u64                           :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_u32                                :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_u64                                :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_rtn_u32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_rtn_u64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_src2_u32                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_src2_u64                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_u32                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_u64                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_swizzle_b32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`sw_offset16<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrap_rtn_b32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata32_0>`,   :ref:`vdata1<amdgpu_synid7_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2_b32                              :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata32_0>`,   :ref:`vdata1<amdgpu_synid7_vdata32_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2_b64                              :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata64_0>`,   :ref:`vdata1<amdgpu_synid7_vdata64_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2st64_b32                          :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata32_0>`,   :ref:`vdata1<amdgpu_synid7_vdata32_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2st64_b64                          :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata64_0>`,   :ref:`vdata1<amdgpu_synid7_vdata64_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b128                              :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata128_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b16                               :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b32                               :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b64                               :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b8                                :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b96                               :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata96_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_src2_b32                          :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_src2_b64                          :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2_rtn_b32             :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b32x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata32_0>`,   :ref:`vdata1<amdgpu_synid7_vdata32_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2_rtn_b64             :ref:`vdst<amdgpu_synid7_vdst128_0>`::ref:`b64x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata64_0>`,   :ref:`vdata1<amdgpu_synid7_vdata64_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2st64_rtn_b32         :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b32x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata32_0>`,   :ref:`vdata1<amdgpu_synid7_vdata32_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2st64_rtn_b64         :ref:`vdst<amdgpu_synid7_vdst128_0>`::ref:`b64x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata0<amdgpu_synid7_vdata64_0>`,   :ref:`vdata1<amdgpu_synid7_vdata64_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg_rtn_b32              :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg_rtn_b64              :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_b32                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_b64                                 :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_rtn_b32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_rtn_b64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,       :ref:`vaddr<amdgpu_synid7_addr_ds>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_src2_b32                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_src2_b64                            :ref:`vaddr<amdgpu_synid7_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+
+EXP
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**      **SRC2**      **SRC3**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    exp                            :ref:`tgt<amdgpu_synid7_tgt>`,      :ref:`vsrc0<amdgpu_synid7_src_exp>`,    :ref:`vsrc1<amdgpu_synid7_src_exp>`,    :ref:`vsrc2<amdgpu_synid7_src_exp>`,    :ref:`vsrc3<amdgpu_synid7_src_exp>`          :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+
+FLAT
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**           **SRC0**      **SRC1**             **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    flat_atomic_add                :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_add_x2             :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_and                :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_and_x2             :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_cmpswap            :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`b32x2<amdgpu_synid7_type_dev>`      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_cmpswap_x2         :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata128_0>`::ref:`b64x2<amdgpu_synid7_type_dev>`      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_dec                :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`u32<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_dec_x2             :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`u64<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fcmpswap           :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`f32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`f32x2<amdgpu_synid7_type_dev>`      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fcmpswap_x2        :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`f64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata128_0>`::ref:`f64x2<amdgpu_synid7_type_dev>`      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fmax               :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`f32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`f32<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fmax_x2            :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`f64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`f64<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fmin               :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`f32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`f32<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fmin_x2            :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`f64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`f64<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_inc                :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`u32<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_inc_x2             :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`u64<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_or                 :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_or_x2              :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smax               :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`s32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`s32<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smax_x2            :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`s64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`s64<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smin               :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`s32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`s32<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smin_x2            :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`s64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`s64<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_sub                :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_sub_x2             :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_swap               :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_swap_x2            :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umax               :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`u32<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umax_x2            :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`u64<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umin               :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`u32<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umin_x2            :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`u64<amdgpu_synid7_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_xor                :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_xor_x2             :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dword                :ref:`vdst<amdgpu_synid7_vdst32_0>`,         :ref:`vaddr<amdgpu_synid7_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx2              :ref:`vdst<amdgpu_synid7_vdst64_0>`,         :ref:`vaddr<amdgpu_synid7_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx3              :ref:`vdst<amdgpu_synid7_vdst96_0>`,         :ref:`vaddr<amdgpu_synid7_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx4              :ref:`vdst<amdgpu_synid7_vdst128_0>`,         :ref:`vaddr<amdgpu_synid7_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sbyte                :ref:`vdst<amdgpu_synid7_vdst32_0>`,         :ref:`vaddr<amdgpu_synid7_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sshort               :ref:`vdst<amdgpu_synid7_vdst32_0>`,         :ref:`vaddr<amdgpu_synid7_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ubyte                :ref:`vdst<amdgpu_synid7_vdst32_0>`,         :ref:`vaddr<amdgpu_synid7_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ushort               :ref:`vdst<amdgpu_synid7_vdst32_0>`,         :ref:`vaddr<amdgpu_synid7_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_byte                              :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dword                             :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx2                           :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx3                           :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata96_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx4                           :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata128_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_short                             :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
+MIMG
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**       **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    image_atomic_add                         :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_and                         :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_cmpswap                     :ref:`vdata<amdgpu_synid7_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_dec                         :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_inc                         :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_or                          :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_smax                        :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_smin                        :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_sub                         :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_swap                        :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_umax                        :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_umin                        :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_xor                         :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4                  :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_b                :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_b_cl             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_b_cl_o           :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_b_o              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c                :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_b              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_b_cl           :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_b_cl_o         :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_b_o            :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_cl             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_cl_o           :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_l              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_l_o            :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_lz             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_lz_o           :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_o              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_cl               :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_cl_o             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_l                :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_l_o              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_lz               :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_lz_o             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_o                :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_get_lod                  :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_get_resinfo              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load                     :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_mip                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_mip_pck             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_mip_pck_sgn         :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_pck                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_pck_sgn             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample                   :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_b                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_b_cl              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_b_cl_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_b_o               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_b               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_b_cl            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_b_cl_o          :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_b_o             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_cd              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_cd_cl           :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_cd_cl_o         :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_cd_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_cl              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_cl_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_d               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_d_cl            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_d_cl_o          :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_d_o             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_l               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_l_o             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_lz              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_lz_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_o               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_cd                :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_cd_cl             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_cd_cl_o           :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_cd_o              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_cl                :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_cl_o              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_d                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_d_cl              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_d_cl_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_d_o               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_l                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_l_o               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_lz                :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_lz_o              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_o                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_store                              :ref:`vdata<amdgpu_synid7_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_store_mip                          :ref:`vdata<amdgpu_synid7_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_store_mip_pck                      :ref:`vdata<amdgpu_synid7_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_store_pck                          :ref:`vdata<amdgpu_synid7_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+
+MUBUF
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**             **SRC1**      **SRC2**      **SRC3**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    buffer_atomic_add                        :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_add_x2                     :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and                        :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and_x2                     :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap                    :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`b32x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap_x2                 :ref:`vdata<amdgpu_synid7_data_buf_atomic128>`::ref:`dst<amdgpu_synid7_ret>`::ref:`b64x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec                        :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec_x2                     :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc                        :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc_x2                     :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or                         :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or_x2                      :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax                       :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax_x2                    :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin                       :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin_x2                    :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub                        :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub_x2                     :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap                       :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap_x2                    :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax                       :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax_x2                    :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin                       :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin_x2                    :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor                        :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor_x2                     :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dword              :ref:`vdst<amdgpu_synid7_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_dwordx2            :ref:`vdst<amdgpu_synid7_dst_buf_64>`,     :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dwordx3            :ref:`vdst<amdgpu_synid7_dst_buf_96>`,     :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dwordx4            :ref:`vdst<amdgpu_synid7_dst_buf_128>`,     :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_x           :ref:`vdst<amdgpu_synid7_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_format_xy          :ref:`vdst<amdgpu_synid7_dst_buf_64>`,     :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_xyz         :ref:`vdst<amdgpu_synid7_dst_buf_96>`,     :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_xyzw        :ref:`vdst<amdgpu_synid7_dst_buf_128>`,     :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_sbyte              :ref:`vdst<amdgpu_synid7_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_sshort             :ref:`vdst<amdgpu_synid7_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_ubyte              :ref:`vdst<amdgpu_synid7_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_ushort             :ref:`vdst<amdgpu_synid7_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_store_byte                        :ref:`vdata<amdgpu_synid7_vdata32_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dword                       :ref:`vdata<amdgpu_synid7_vdata32_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx2                     :ref:`vdata<amdgpu_synid7_vdata64_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx3                     :ref:`vdata<amdgpu_synid7_vdata96_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx4                     :ref:`vdata<amdgpu_synid7_vdata128_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_x                    :ref:`vdata<amdgpu_synid7_vdata32_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xy                   :ref:`vdata<amdgpu_synid7_vdata64_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyz                  :ref:`vdata<amdgpu_synid7_vdata96_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyzw                 :ref:`vdata<amdgpu_synid7_vdata128_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_short                       :ref:`vdata<amdgpu_synid7_vdata32_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`,    :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,    :ref:`soffset<amdgpu_synid7_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_wbinvl1
+    buffer_wbinvl1_vol
+
+SMRD
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_buffer_load_dword            :ref:`sdst<amdgpu_synid7_sdst32_0>`,     :ref:`sbase<amdgpu_synid7_base_smem_buf>`,    :ref:`soffset<amdgpu_synid7_offset_smem>`
+    s_buffer_load_dwordx16         :ref:`sdst<amdgpu_synid7_sdst512_0>`,     :ref:`sbase<amdgpu_synid7_base_smem_buf>`,    :ref:`soffset<amdgpu_synid7_offset_smem>`
+    s_buffer_load_dwordx2          :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`sbase<amdgpu_synid7_base_smem_buf>`,    :ref:`soffset<amdgpu_synid7_offset_smem>`
+    s_buffer_load_dwordx4          :ref:`sdst<amdgpu_synid7_sdst128_0>`,     :ref:`sbase<amdgpu_synid7_base_smem_buf>`,    :ref:`soffset<amdgpu_synid7_offset_smem>`
+    s_buffer_load_dwordx8          :ref:`sdst<amdgpu_synid7_sdst256_0>`,     :ref:`sbase<amdgpu_synid7_base_smem_buf>`,    :ref:`soffset<amdgpu_synid7_offset_smem>`
+    s_dcache_inv
+    s_dcache_inv_vol
+    s_load_dword                   :ref:`sdst<amdgpu_synid7_sdst32_0>`,     :ref:`sbase<amdgpu_synid7_base_smem_addr>`,    :ref:`soffset<amdgpu_synid7_offset_smem>`
+    s_load_dwordx16                :ref:`sdst<amdgpu_synid7_sdst512_0>`,     :ref:`sbase<amdgpu_synid7_base_smem_addr>`,    :ref:`soffset<amdgpu_synid7_offset_smem>`
+    s_load_dwordx2                 :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`sbase<amdgpu_synid7_base_smem_addr>`,    :ref:`soffset<amdgpu_synid7_offset_smem>`
+    s_load_dwordx4                 :ref:`sdst<amdgpu_synid7_sdst128_0>`,     :ref:`sbase<amdgpu_synid7_base_smem_addr>`,    :ref:`soffset<amdgpu_synid7_offset_smem>`
+    s_load_dwordx8                 :ref:`sdst<amdgpu_synid7_sdst256_0>`,     :ref:`sbase<amdgpu_synid7_base_smem_addr>`,    :ref:`soffset<amdgpu_synid7_offset_smem>`
+    s_memtime                      :ref:`sdst<amdgpu_synid7_sdst64_0>`
+
+SOP1
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_abs_i32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_and_saveexec_b64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_andn2_saveexec_b64           :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_bcnt0_i32_b32                :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_bcnt0_i32_b64                :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_bcnt1_i32_b32                :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_bcnt1_i32_b64                :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_bitset0_b32                  :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_bitset0_b64                  :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`
+    s_bitset1_b32                  :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_bitset1_b64                  :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`
+    s_brev_b32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_brev_b64                     :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_cbranch_join                           :ref:`ssrc<amdgpu_synid7_ssrc32_1>`
+    s_cmov_b32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_cmov_b64                     :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_ff0_i32_b32                  :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_ff0_i32_b64                  :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_ff1_i32_b32                  :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_ff1_i32_b64                  :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_flbit_i32                    :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_flbit_i32_b32                :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_flbit_i32_b64                :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_flbit_i32_i64                :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_getpc_b64                    :ref:`sdst<amdgpu_synid7_sdst64_1>`
+    s_mov_b32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_mov_b64                      :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_mov_fed_b32                  :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_movreld_b32                  :ref:`sdst<amdgpu_synid7_sdst32_0>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_movreld_b64                  :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_movrels_b32                  :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_2>`
+    s_movrels_b64                  :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_1>`
+    s_nand_saveexec_b64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_nor_saveexec_b64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_not_b32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_not_b64                      :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_or_saveexec_b64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_orn2_saveexec_b64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_quadmask_b32                 :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_quadmask_b64                 :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_rfe_b64                                :ref:`ssrc<amdgpu_synid7_ssrc64_1>`
+    s_setpc_b64                              :ref:`ssrc<amdgpu_synid7_ssrc64_1>`
+    s_sext_i32_i16                 :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_3>`
+    s_sext_i32_i8                  :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_3>`
+    s_swappc_b64                   :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_1>`
+    s_wqm_b32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+    s_wqm_b64                      :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_xnor_saveexec_b64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+    s_xor_saveexec_b64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+
+SOP2
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**       **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_absdiff_i32                  :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_add_i32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_add_u32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_addc_u32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_and_b32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_and_b64                      :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+    s_andn2_b32                    :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_andn2_b64                    :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+    s_ashr_i32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    s_ashr_i64                     :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    s_bfe_i32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    s_bfe_i64                      :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    s_bfe_u32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_bfe_u64                      :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    s_bfm_b32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_bfm_b64                      :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`
+    s_cbranch_g_fork                         :ref:`ssrc0<amdgpu_synid7_ssrc64_2>`,     :ref:`ssrc1<amdgpu_synid7_ssrc64_2>`
+    s_cselect_b32                  :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_cselect_b64                  :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+    s_lshl_b32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    s_lshl_b64                     :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    s_lshr_b32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    s_lshr_b64                     :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    s_max_i32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_max_u32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_min_i32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_min_u32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_mul_i32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_nand_b32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_nand_b64                     :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+    s_nor_b32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_nor_b64                      :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+    s_or_b32                       :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_or_b64                       :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+    s_orn2_b32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_orn2_b64                     :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+    s_sub_i32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_sub_u32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_subb_u32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_xnor_b32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_xnor_b64                     :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+    s_xor_b32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_xor_b64                      :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+
+SOPC
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **SRC0**      **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_bitcmp0_b32                  :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_bitcmp0_b64                  :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    s_bitcmp1_b32                  :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_bitcmp1_b64                  :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    s_cmp_eq_i32                   :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_cmp_eq_u32                   :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_cmp_ge_i32                   :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_cmp_ge_u32                   :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_cmp_gt_i32                   :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_cmp_gt_u32                   :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_cmp_le_i32                   :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_cmp_le_u32                   :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_cmp_lg_i32                   :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_cmp_lg_u32                   :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_cmp_lt_i32                   :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_cmp_lt_u32                   :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+    s_setvskip                     :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+
+SOPK
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_addk_i32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_cbranch_i_fork                         :ref:`ssrc<amdgpu_synid7_ssrc64_3>`,     :ref:`label<amdgpu_synid7_label>`
+    s_cmovk_i32                    :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_cmpk_eq_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_cmpk_eq_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
+    s_cmpk_ge_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_cmpk_ge_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
+    s_cmpk_gt_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_cmpk_gt_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
+    s_cmpk_le_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_cmpk_le_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
+    s_cmpk_lg_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_cmpk_lg_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
+    s_cmpk_lt_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_cmpk_lt_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
+    s_getreg_b32                   :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`hwreg<amdgpu_synid7_hwreg>`
+    s_movk_i32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_mulk_i32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_setreg_b32                   :ref:`hwreg<amdgpu_synid7_hwreg>`,    :ref:`ssrc<amdgpu_synid7_ssrc32_1>`
+    s_setreg_imm32_b32             :ref:`hwreg<amdgpu_synid7_hwreg>`,    :ref:`imm32<amdgpu_synid7_bimm32>`
+
+SOPP
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **SRC**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_barrier
+    s_branch                       :ref:`label<amdgpu_synid7_label>`
+    s_cbranch_cdbgsys              :ref:`label<amdgpu_synid7_label>`
+    s_cbranch_cdbgsys_and_user     :ref:`label<amdgpu_synid7_label>`
+    s_cbranch_cdbgsys_or_user      :ref:`label<amdgpu_synid7_label>`
+    s_cbranch_cdbguser             :ref:`label<amdgpu_synid7_label>`
+    s_cbranch_execnz               :ref:`label<amdgpu_synid7_label>`
+    s_cbranch_execz                :ref:`label<amdgpu_synid7_label>`
+    s_cbranch_scc0                 :ref:`label<amdgpu_synid7_label>`
+    s_cbranch_scc1                 :ref:`label<amdgpu_synid7_label>`
+    s_cbranch_vccnz                :ref:`label<amdgpu_synid7_label>`
+    s_cbranch_vccz                 :ref:`label<amdgpu_synid7_label>`
+    s_decperflevel                 :ref:`imm16<amdgpu_synid7_bimm16>`
+    s_endpgm
+    s_icache_inv
+    s_incperflevel                 :ref:`imm16<amdgpu_synid7_bimm16>`
+    s_nop                          :ref:`imm16<amdgpu_synid7_bimm16>`
+    s_sendmsg                      :ref:`msg<amdgpu_synid7_msg>`
+    s_sendmsghalt                  :ref:`msg<amdgpu_synid7_msg>`
+    s_sethalt                      :ref:`imm16<amdgpu_synid7_bimm16>`
+    s_setkill                      :ref:`imm16<amdgpu_synid7_bimm16>`
+    s_setprio                      :ref:`imm16<amdgpu_synid7_bimm16>`
+    s_sleep                        :ref:`imm16<amdgpu_synid7_bimm16>`
+    s_trap                         :ref:`imm16<amdgpu_synid7_bimm16>`
+    s_ttracedata
+    s_waitcnt                      :ref:`waitcnt<amdgpu_synid7_waitcnt>`
+
+VINTRP
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**       **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_interp_mov_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`param<amdgpu_synid7_param>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`attr<amdgpu_synid7_attr>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_interp_p1_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vsrc<amdgpu_synid7_vsrc32_0>`,      :ref:`attr<amdgpu_synid7_attr>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_interp_p2_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vsrc<amdgpu_synid7_vsrc32_0>`,      :ref:`attr<amdgpu_synid7_attr>`::ref:`b32<amdgpu_synid7_type_dev>`
+
+VOP1
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_bfrev_b32                    :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_ceil_f32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_ceil_f64                     :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+    v_clrexcp
+    v_cos_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_f16_f32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_f32_f16                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_1>`
+    v_cvt_f32_f64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+    v_cvt_f32_i32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_f32_u32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_f32_ubyte0               :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_f32_ubyte1               :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_f32_ubyte2               :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_f32_ubyte3               :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_f64_f32                  :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_f64_i32                  :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_f64_u32                  :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_flr_i32_f32              :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_i32_f32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_i32_f64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+    v_cvt_off_f32_i4               :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_rpi_i32_f32              :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_u32_f32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_cvt_u32_f64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+    v_exp_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_exp_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_ffbh_i32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_ffbh_u32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_ffbl_b32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_floor_f32                    :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_floor_f64                    :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+    v_fract_f32                    :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_fract_f64                    :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+    v_frexp_exp_i32_f32            :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_frexp_exp_i32_f64            :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+    v_frexp_mant_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_frexp_mant_f64               :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+    v_log_clamp_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_log_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_log_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_mov_b32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_mov_fed_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_movreld_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_movrels_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
+    v_movrelsd_b32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
+    v_nop
+    v_not_b32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_rcp_clamp_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_rcp_clamp_f64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+    v_rcp_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_rcp_f64                      :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+    v_rcp_iflag_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_rcp_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_readfirstlane_b32            :ref:`sdst<amdgpu_synid7_sdst32_2>`,     :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
+    v_rndne_f32                    :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_rndne_f64                    :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+    v_rsq_clamp_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_rsq_clamp_f64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+    v_rsq_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_rsq_f64                      :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+    v_rsq_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_sin_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_sqrt_f32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_sqrt_f64                     :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+    v_trunc_f32                    :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
+    v_trunc_f64                    :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
+
+VOP2
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST0**      **DST1**      **SRC0**      **SRC1**      **SRC2**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_add_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_add_i32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_addc_u32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`,    :ref:`vcc<amdgpu_synid7_vcc_64>`
+    v_and_b32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_ashr_i32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_ashrrev_i32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_bcnt_u32_b32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_bfm_b32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cndmask_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`,    :ref:`vcc<amdgpu_synid7_vcc_64>`
+    v_cvt_pk_i16_i32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cvt_pk_u16_u32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cvt_pkaccum_u8_f32           :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_cvt_pknorm_i16_f32           :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cvt_pknorm_u16_f32           :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cvt_pkrtz_f16_f32            :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_ldexp_f32                    :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`i32<amdgpu_synid7_type_dev>`
+    v_lshl_b32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_lshlrev_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_lshr_b32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_lshrrev_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_mac_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_mac_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_madak_f32                    :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`,    :ref:`imm32<amdgpu_synid7_fimm32>`
+    v_madmk_f32                    :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`imm32<amdgpu_synid7_fimm32>`,    :ref:`vsrc2<amdgpu_synid7_vsrc32_0>`
+    v_max_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_max_i32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_max_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_max_u32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_mbcnt_hi_u32_b32             :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_mbcnt_lo_u32_b32             :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_min_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_min_i32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_min_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_min_u32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_mul_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_mul_hi_i32_i24               :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_mul_hi_u32_u24               :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_mul_i32_i24                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_mul_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_mul_u32_u24                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_or_b32                       :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_readlane_b32                 :ref:`sdst<amdgpu_synid7_sdst32_2>`,               :ref:`vsrc0<amdgpu_synid7_vsrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_4>`
+    v_sub_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_sub_i32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_subb_u32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`,    :ref:`vcc<amdgpu_synid7_vcc_64>`
+    v_subbrev_u32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`,    :ref:`vcc<amdgpu_synid7_vcc_64>`
+    v_subrev_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_subrev_i32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_writelane_b32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_4>`
+    v_xor_b32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+
+VOP3
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST0**       **DST1**      **SRC0**        **SRC1**        **SRC2**            **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_add_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_f64                      :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_i32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_addc_u32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+    v_alignbit_b32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
+    v_alignbyte_b32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
+    v_and_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_ashr_i32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_ashr_i64                     :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_ashrrev_i32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_2>`
+    v_bcnt_u32_b32_e64             :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_bfe_i32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_bfe_u32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
+    v_bfi_b32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
+    v_bfm_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_bfrev_b32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_ceil_f32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ceil_f64_e64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_clrexcp_e64
+    v_cmp_class_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_cmp_class_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_cmp_eq_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_eq_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_eq_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_eq_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_eq_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_eq_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_f_f32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_f_f64_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_f_i32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_f_i64_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_f_u32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_f_u64_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_ge_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_ge_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_ge_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_ge_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_ge_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_ge_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_gt_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_gt_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_gt_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_gt_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_gt_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_gt_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_le_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_le_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_le_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_le_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_le_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_le_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_lg_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_lg_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_lt_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_lt_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_lt_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_lt_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_lt_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_lt_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_ne_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_ne_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_ne_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_ne_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_neq_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_neq_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_nge_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_nge_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_ngt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_ngt_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_nle_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_nle_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_nlg_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_nlg_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_nlt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_nlt_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_o_f32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_o_f64_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_t_i32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_t_i64_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_t_u32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_t_u64_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmp_tru_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_tru_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_u_f32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_u_f64_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_eq_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_eq_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_f_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_f_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_ge_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_ge_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_gt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_gt_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_le_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_le_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_lg_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_lg_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_lt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_lt_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_neq_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_neq_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_nge_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_nge_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_ngt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_ngt_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_nle_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_nle_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_nlg_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_nlg_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_nlt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_nlt_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_o_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_o_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_tru_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_tru_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_u_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_u_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_eq_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_eq_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_f_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_f_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_ge_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_ge_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_gt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_gt_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_le_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_le_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_lg_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_lg_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_lt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_lt_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_neq_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_neq_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_nge_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_nge_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_ngt_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_ngt_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_nle_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_nle_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_nlg_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_nlg_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_nlt_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_nlt_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_o_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_o_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_tru_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_tru_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_u_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_u_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_class_f32_e64           :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_cmpx_class_f64_e64           :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_cmpx_eq_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_eq_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_eq_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_eq_i64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_eq_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_eq_u64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_f_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_f_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_f_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_f_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_f_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_f_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_ge_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_ge_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_ge_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_ge_i64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_ge_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_ge_u64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_gt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_gt_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_gt_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_gt_i64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_gt_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_gt_u64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_le_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_le_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_le_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_le_i64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_le_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_le_u64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_lg_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_lg_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_lt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_lt_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_lt_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_lt_i64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_lt_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_lt_u64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_ne_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_ne_i64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_ne_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_ne_u64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_neq_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_neq_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_nge_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_nge_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_ngt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_ngt_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_nle_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_nle_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_nlg_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_nlg_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_nlt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_nlt_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_o_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_o_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_t_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_t_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_t_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_t_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
+    v_cmpx_tru_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_tru_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_u_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_u_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cndmask_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+    v_cos_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubeid_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubema_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubesc_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubetc_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_f32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_f32_f16_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_f64_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_i32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_u32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte0_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_cvt_f32_ubyte1_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_cvt_f32_ubyte2_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_cvt_f32_ubyte3_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_cvt_f64_f32_e64              :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_i32_e64              :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src32_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_u32_e64              :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src32_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_flr_i32_f32_e64          :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_i32_f32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_i32_f64_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_off_f32_i4_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_i16_i32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cvt_pk_u16_u32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cvt_pk_u8_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_cvt_pkaccum_u8_f32_e64       :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_cvt_pknorm_i16_f32_e64       :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_pknorm_u16_f32_e64       :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_pkrtz_f16_f32_e64        :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_rpi_i32_f32_e64          :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_u32_f32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_u32_f64_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_div_fixup_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_scale_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
+    v_div_scale_f64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,      :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`,       :ref:`src2<amdgpu_synid7_src64_1>`
+    v_exp_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_i32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_ffbh_u32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_ffbl_b32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_floor_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_floor_f64_e64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f64                      :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f64_e64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_exp_i32_f32_e64        :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_frexp_exp_i32_f64_e64        :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+    v_frexp_mant_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_frexp_mant_f64_e64           :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`i32<amdgpu_synid7_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f64                    :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`i32<amdgpu_synid7_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lerp_u8                      :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_log_clamp_f32_e64            :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_log_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_log_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lshl_b32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_lshl_b64                     :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_lshlrev_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_2>`
+    v_lshr_b32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_lshr_b64                     :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_lshrrev_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_2>`
+    v_mac_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mac_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i32_i24                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`::ref:`i32<amdgpu_synid7_type_dev>`
+    v_mad_i64_i32                  :ref:`vdst<amdgpu_synid7_vdst64_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src64_1>`::ref:`i64<amdgpu_synid7_type_dev>`
+    v_mad_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u32_u24                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_mad_u64_u32                  :ref:`vdst<amdgpu_synid7_vdst64_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src64_1>`::ref:`u64<amdgpu_synid7_type_dev>`
+    v_max3_f32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_i32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
+    v_max3_u32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
+    v_max_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_f64                      :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_i32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_max_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_u32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_mbcnt_hi_u32_b32_e64         :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_mbcnt_lo_u32_b32_e64         :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_med3_f32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_i32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
+    v_med3_u32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
+    v_min3_f32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_i32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
+    v_min3_u32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
+    v_min_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_f64                      :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_i32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_min_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_u32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_mov_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_mov_fed_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_movreld_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_movrels_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
+    v_movrelsd_b32_e64             :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
+    v_mqsad_pk_u16_u8              :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b64<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`
+    v_mqsad_u32_u8                 :ref:`vdst<amdgpu_synid7_vdst128_0>`::ref:`b128<amdgpu_synid7_type_dev>`,           :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`vsrc2<amdgpu_synid7_vsrc128_0>`::ref:`b128<amdgpu_synid7_type_dev>`
+    v_msad_u8                      :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_mul_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_f64                      :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_i32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_mul_hi_i32_i24_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_mul_hi_u32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_mul_hi_u32_u24_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_mul_i32_i24_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_mul_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_i32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_mul_lo_u32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_mul_u32_u24_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_mullit_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_nop_e64
+    v_not_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_or_b32_e64                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_qsad_pk_u16_u8               :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b64<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`
+    v_rcp_clamp_f32_e64            :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_clamp_f64_e64            :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_f64_e64                  :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_iflag_f32_e64            :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f64_e64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_clamp_f32_e64            :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_clamp_f64_e64            :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f64_e64                  :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_hi_u8                    :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`,  :ref:`src1<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`,  :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_sad_u16                      :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u16x2<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_1>`::ref:`u16x2<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_sad_u32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
+    v_sad_u8                       :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`,  :ref:`src1<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`,  :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_sin_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f64_e64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_i32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_subb_u32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+    v_subbrev_u32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+    v_subrev_f32_e64               :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_i32_e64               :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_trig_preop_f64               :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f64_e64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_xor_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+
+VOPC
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_cmp_class_f32                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_cmp_class_f64                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_cmp_eq_f32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_eq_f64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_eq_i32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_eq_i64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_eq_u32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_eq_u64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_f_f32                    :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_f_f64                    :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_f_i32                    :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_f_i64                    :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_f_u32                    :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_f_u64                    :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_ge_f32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_ge_f64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_ge_i32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_ge_i64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_ge_u32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_ge_u64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_gt_f32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_gt_f64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_gt_i32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_gt_i64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_gt_u32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_gt_u64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_le_f32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_le_f64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_le_i32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_le_i64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_le_u32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_le_u64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_lg_f32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_lg_f64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_lt_f32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_lt_f64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_lt_i32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_lt_i64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_lt_u32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_lt_u64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_ne_i32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_ne_i64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_ne_u32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_ne_u64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_neq_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_neq_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_nge_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_nge_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_ngt_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_ngt_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_nle_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_nle_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_nlg_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_nlg_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_nlt_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_nlt_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_o_f32                    :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_o_f64                    :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_t_i32                    :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_t_i64                    :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_t_u32                    :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_t_u64                    :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_tru_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_tru_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmp_u_f32                    :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmp_u_f64                    :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_eq_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_eq_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_f_f32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_f_f64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_ge_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_ge_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_gt_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_gt_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_le_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_le_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_lg_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_lg_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_lt_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_lt_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_neq_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_neq_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_nge_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_nge_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_ngt_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_ngt_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_nle_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_nle_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_nlg_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_nlg_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_nlt_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_nlt_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_o_f32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_o_f64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_tru_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_tru_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmps_u_f32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmps_u_f64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_eq_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_eq_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_f_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_f_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_ge_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_ge_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_gt_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_gt_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_le_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_le_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_lg_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_lg_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_lt_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_lt_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_neq_f32                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_neq_f64                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_nge_f32                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_nge_f64                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_ngt_f32                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_ngt_f64                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_nle_f32                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_nle_f64                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_nlg_f32                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_nlg_f64                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_nlt_f32                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_nlt_f64                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_o_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_o_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_tru_f32                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_tru_f64                :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpsx_u_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpsx_u_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_class_f32               :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_cmpx_class_f64               :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_cmpx_eq_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_eq_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_eq_i32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_eq_i64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_eq_u32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_eq_u64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_f_f32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_f_f64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_f_i32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_f_i64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_f_u32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_f_u64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_ge_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_ge_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_ge_i32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_ge_i64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_ge_u32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_ge_u64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_gt_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_gt_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_gt_i32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_gt_i64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_gt_u32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_gt_u64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_le_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_le_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_le_i32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_le_i64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_le_u32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_le_u64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_lg_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_lg_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_lt_f32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_lt_f64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_lt_i32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_lt_i64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_lt_u32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_lt_u64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_ne_i32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_ne_i64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_ne_u32                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_ne_u64                  :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_neq_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_neq_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_nge_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_nge_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_ngt_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_ngt_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_nle_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_nle_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_nlg_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_nlg_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_nlt_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_nlt_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_o_f32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_o_f64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_t_i32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_t_i64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_t_u32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_t_u64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_tru_f32                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_tru_f64                 :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+    v_cmpx_u_f32                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_cmpx_u_f64                   :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+
+.. |---| unicode:: U+02014 .. em dash
+
+
+.. toctree::
+    :hidden:
+
+    gfx7_attr
+    gfx7_bimm16
+    gfx7_bimm32
+    gfx7_fimm32
+    gfx7_hwreg
+    gfx7_label
+    gfx7_msg
+    gfx7_param
+    gfx7_simm16
+    gfx7_tgt
+    gfx7_uimm16
+    gfx7_waitcnt
+    gfx7_addr_buf
+    gfx7_addr_ds
+    gfx7_addr_flat
+    gfx7_addr_mimg
+    gfx7_base_smem_addr
+    gfx7_base_smem_buf
+    gfx7_data_buf_atomic128
+    gfx7_data_buf_atomic32
+    gfx7_data_buf_atomic64
+    gfx7_data_mimg_atomic_cmp
+    gfx7_data_mimg_atomic_reg
+    gfx7_data_mimg_store
+    gfx7_dst_buf_128
+    gfx7_dst_buf_64
+    gfx7_dst_buf_96
+    gfx7_dst_buf_lds
+    gfx7_dst_flat_atomic32
+    gfx7_dst_flat_atomic64
+    gfx7_dst_mimg_gather4
+    gfx7_dst_mimg_regular
+    gfx7_offset_buf
+    gfx7_offset_smem
+    gfx7_rsrc_buf
+    gfx7_rsrc_mimg
+    gfx7_samp_mimg
+    gfx7_sdst128_0
+    gfx7_sdst256_0
+    gfx7_sdst32_0
+    gfx7_sdst32_1
+    gfx7_sdst32_2
+    gfx7_sdst512_0
+    gfx7_sdst64_0
+    gfx7_sdst64_1
+    gfx7_src32_0
+    gfx7_src32_1
+    gfx7_src32_2
+    gfx7_src32_3
+    gfx7_src64_0
+    gfx7_src64_1
+    gfx7_src64_2
+    gfx7_src_exp
+    gfx7_ssrc32_0
+    gfx7_ssrc32_1
+    gfx7_ssrc32_2
+    gfx7_ssrc32_3
+    gfx7_ssrc32_4
+    gfx7_ssrc64_0
+    gfx7_ssrc64_1
+    gfx7_ssrc64_2
+    gfx7_ssrc64_3
+    gfx7_vcc_64
+    gfx7_vdata128_0
+    gfx7_vdata32_0
+    gfx7_vdata64_0
+    gfx7_vdata96_0
+    gfx7_vdst128_0
+    gfx7_vdst32_0
+    gfx7_vdst64_0
+    gfx7_vdst96_0
+    gfx7_vsrc128_0
+    gfx7_vsrc32_0
+    gfx7_vsrc64_0
+    gfx7_mod
+    gfx7_opt
+    gfx7_ret
+    gfx7_type_dev

diff --git a/docs/AMDGPU/AMDGPUAsmGFX8.rst b/docs/AMDGPU/AMDGPUAsmGFX8.rst
new file mode 100644 (file)
index 0000000..9dc78e1
--- /dev/null
+++ b/docs/AMDGPU/AMDGPUAsmGFX8.rst
@@ -0,0 +1,1846 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+============================
+Syntax of GFX8 Instructions
+============================
+
+.. contents::
+  :local:
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Introduction
+============
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+DS
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**         **SRC0**      **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    ds_add_f32                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_f32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_u32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_u64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_f32                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_u32                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_u64                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_u32                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_u64                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_b32                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_b64                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_rtn_b32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_rtn_b64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_src2_b32                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_src2_b64                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_append                      :ref:`vdst<amdgpu_synid8_vdst32_0>`                                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_bpermute_b32                :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
+    ds_cmpst_b32                               :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata32_0>`,   :ref:`vdata1<amdgpu_synid8_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_b64                               :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata64_0>`,   :ref:`vdata1<amdgpu_synid8_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_f32                               :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata32_0>`,   :ref:`vdata1<amdgpu_synid8_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_f64                               :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata64_0>`,   :ref:`vdata1<amdgpu_synid8_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_b32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata32_0>`,   :ref:`vdata1<amdgpu_synid8_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_b64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata64_0>`,   :ref:`vdata1<amdgpu_synid8_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata32_0>`,   :ref:`vdata1<amdgpu_synid8_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_f64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata64_0>`,   :ref:`vdata1<amdgpu_synid8_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_condxchg32_rtn_b64          :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_consume                     :ref:`vdst<amdgpu_synid8_vdst32_0>`                                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_rtn_u32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_rtn_u64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_src2_u32                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_src2_u64                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_u32                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_u64                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_barrier                             :ref:`vdata<amdgpu_synid8_vdata32_0>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_init                                :ref:`vdata<amdgpu_synid8_vdata32_0>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_br                             :ref:`vdata<amdgpu_synid8_vdata32_0>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_p                                                                 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_release_all                                                       :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_v                                                                 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_rtn_u32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_rtn_u64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_src2_u32                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_src2_u64                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_u32                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_u64                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_f32                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_f64                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_i32                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_i64                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_f32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_f64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_i32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_i64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_u32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_u64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_f32                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_f64                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_i32                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_i64                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_u32                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_u64                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_u32                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_u64                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_f32                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_f64                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_i32                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_i64                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_f32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_f64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_i32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_i64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_u32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_u64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_f32                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_f64                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_i32                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_i64                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_u32                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_u64                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_u32                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_u64                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_b32                               :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata32_0>`,   :ref:`vdata1<amdgpu_synid8_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_b64                               :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata64_0>`,   :ref:`vdata1<amdgpu_synid8_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_rtn_b32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata32_0>`,   :ref:`vdata1<amdgpu_synid8_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_rtn_b64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata64_0>`,   :ref:`vdata1<amdgpu_synid8_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_nop
+    ds_or_b32                                  :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_b64                                  :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_rtn_b32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_rtn_b64                  :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_src2_b32                             :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_src2_b64                             :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_ordered_count               :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_permute_b32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
+    ds_read2_b32                   :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b32x2<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2_b64                   :ref:`vdst<amdgpu_synid8_vdst128_0>`::ref:`b64x2<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2st64_b32               :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b32x2<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2st64_b64               :ref:`vdst<amdgpu_synid8_vdst128_0>`::ref:`b64x2<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b128                   :ref:`vdst<amdgpu_synid8_vdst128_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b32                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b64                    :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b96                    :ref:`vdst<amdgpu_synid8_vdst96_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i16                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i8                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u16                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u8                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_rtn_u32                :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_rtn_u64                :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_src2_u32                           :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_src2_u64                           :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_u32                                :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_u64                                :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_rtn_u32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_rtn_u64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_src2_u32                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_src2_u64                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_u32                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_u64                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_swizzle_b32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`sw_offset16<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrap_rtn_b32                :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata32_0>`,   :ref:`vdata1<amdgpu_synid8_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2_b32                              :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata32_0>`,   :ref:`vdata1<amdgpu_synid8_vdata32_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2_b64                              :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata64_0>`,   :ref:`vdata1<amdgpu_synid8_vdata64_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2st64_b32                          :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata32_0>`,   :ref:`vdata1<amdgpu_synid8_vdata32_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2st64_b64                          :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata64_0>`,   :ref:`vdata1<amdgpu_synid8_vdata64_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b128                              :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata128_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b16                               :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b32                               :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b64                               :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b8                                :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b96                               :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata96_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_src2_b32                          :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_src2_b64                          :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2_rtn_b32             :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b32x2<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata32_0>`,   :ref:`vdata1<amdgpu_synid8_vdata32_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2_rtn_b64             :ref:`vdst<amdgpu_synid8_vdst128_0>`::ref:`b64x2<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata64_0>`,   :ref:`vdata1<amdgpu_synid8_vdata64_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2st64_rtn_b32         :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b32x2<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata32_0>`,   :ref:`vdata1<amdgpu_synid8_vdata32_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2st64_rtn_b64         :ref:`vdst<amdgpu_synid8_vdst128_0>`::ref:`b64x2<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata0<amdgpu_synid8_vdata64_0>`,   :ref:`vdata1<amdgpu_synid8_vdata64_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg_rtn_b32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg_rtn_b64              :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_b32                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_b64                                 :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_rtn_b32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_rtn_b64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,       :ref:`vaddr<amdgpu_synid8_addr_ds>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_src2_b32                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_src2_b64                            :ref:`vaddr<amdgpu_synid8_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+
+EXP
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**      **SRC2**      **SRC3**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    exp                            :ref:`tgt<amdgpu_synid8_tgt>`,      :ref:`vsrc0<amdgpu_synid8_src_exp>`,    :ref:`vsrc1<amdgpu_synid8_src_exp>`,    :ref:`vsrc2<amdgpu_synid8_src_exp>`,    :ref:`vsrc3<amdgpu_synid8_src_exp>`          :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+
+FLAT
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**           **SRC0**      **SRC1**             **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    flat_atomic_add                :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_add_x2             :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_and                :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_and_x2             :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_cmpswap            :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`::ref:`b32x2<amdgpu_synid8_type_dev>`      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_cmpswap_x2         :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata128_0>`::ref:`b64x2<amdgpu_synid8_type_dev>`      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_dec                :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_dec_x2             :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`::ref:`u64<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`::ref:`u64<amdgpu_synid8_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_inc                :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_inc_x2             :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`::ref:`u64<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`::ref:`u64<amdgpu_synid8_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_or                 :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_or_x2              :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smax               :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`::ref:`s32<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`::ref:`s32<amdgpu_synid8_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smax_x2            :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`::ref:`s64<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`::ref:`s64<amdgpu_synid8_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smin               :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`::ref:`s32<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`::ref:`s32<amdgpu_synid8_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smin_x2            :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`::ref:`s64<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`::ref:`s64<amdgpu_synid8_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_sub                :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_sub_x2             :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_swap               :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_swap_x2            :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umax               :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umax_x2            :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`::ref:`u64<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`::ref:`u64<amdgpu_synid8_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umin               :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umin_x2            :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`::ref:`u64<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`::ref:`u64<amdgpu_synid8_type_dev>`        :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_xor                :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_xor_x2             :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dword                :ref:`vdst<amdgpu_synid8_vdst32_0>`,         :ref:`vaddr<amdgpu_synid8_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx2              :ref:`vdst<amdgpu_synid8_vdst64_0>`,         :ref:`vaddr<amdgpu_synid8_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx3              :ref:`vdst<amdgpu_synid8_vdst96_0>`,         :ref:`vaddr<amdgpu_synid8_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx4              :ref:`vdst<amdgpu_synid8_vdst128_0>`,         :ref:`vaddr<amdgpu_synid8_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sbyte                :ref:`vdst<amdgpu_synid8_vdst32_0>`,         :ref:`vaddr<amdgpu_synid8_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sshort               :ref:`vdst<amdgpu_synid8_vdst32_0>`,         :ref:`vaddr<amdgpu_synid8_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ubyte                :ref:`vdst<amdgpu_synid8_vdst32_0>`,         :ref:`vaddr<amdgpu_synid8_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ushort               :ref:`vdst<amdgpu_synid8_vdst32_0>`,         :ref:`vaddr<amdgpu_synid8_addr_flat>`                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_byte                              :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dword                             :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx2                           :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx3                           :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata96_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx4                           :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata128_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_short                             :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
+MIMG
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**       **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    image_atomic_add                         :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_and                         :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_cmpswap                     :ref:`vdata<amdgpu_synid8_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_dec                         :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_inc                         :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_or                          :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_smax                        :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_smin                        :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_sub                         :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_swap                        :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_umax                        :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_umin                        :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_xor                         :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4                  :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b                :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_cl             :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_cl_o           :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_o              :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c                :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b              :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_cl           :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_cl_o         :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_o            :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_cl             :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_cl_o           :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_l              :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_l_o            :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_lz             :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_lz_o           :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_o              :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_cl               :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_cl_o             :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_l                :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_l_o              :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_lz               :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_lz_o             :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_o                :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_get_lod                  :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_get_resinfo              :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load                     :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_load_mip                 :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_load_mip_pck             :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_mip_pck_sgn         :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_pck                 :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_pck_sgn             :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample                   :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b                 :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_cl              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_cl_o            :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_o               :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c                 :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b               :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_cl            :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_cl_o          :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_o             :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_cl           :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_cl_o         :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_o            :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cl              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cl_o            :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d               :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_cl            :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_cl_o          :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_o             :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_l               :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_l_o             :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_lz              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_lz_o            :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_o               :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd                :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_cl             :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_cl_o           :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_o              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cl                :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cl_o              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d                 :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_cl              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_cl_o            :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_o               :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_l                 :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_l_o               :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_lz                :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_lz_o              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_o                 :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_store                              :ref:`vdata<amdgpu_synid8_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_store_mip                          :ref:`vdata<amdgpu_synid8_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_store_mip_pck                      :ref:`vdata<amdgpu_synid8_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_store_pck                          :ref:`vdata<amdgpu_synid8_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+
+MUBUF
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**             **SRC1**      **SRC2**      **SRC3**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    buffer_atomic_add                        :ref:`vdata<amdgpu_synid8_data_buf_atomic32>`::ref:`dst<amdgpu_synid8_ret>`,       :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_add_x2                     :ref:`vdata<amdgpu_synid8_data_buf_atomic64>`::ref:`dst<amdgpu_synid8_ret>`,       :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and                        :ref:`vdata<amdgpu_synid8_data_buf_atomic32>`::ref:`dst<amdgpu_synid8_ret>`,       :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and_x2                     :ref:`vdata<amdgpu_synid8_data_buf_atomic64>`::ref:`dst<amdgpu_synid8_ret>`,       :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap                    :ref:`vdata<amdgpu_synid8_data_buf_atomic64>`::ref:`dst<amdgpu_synid8_ret>`::ref:`b32x2<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap_x2                 :ref:`vdata<amdgpu_synid8_data_buf_atomic128>`::ref:`dst<amdgpu_synid8_ret>`::ref:`b64x2<amdgpu_synid8_type_dev>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec                        :ref:`vdata<amdgpu_synid8_data_buf_atomic32>`::ref:`dst<amdgpu_synid8_ret>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec_x2                     :ref:`vdata<amdgpu_synid8_data_buf_atomic64>`::ref:`dst<amdgpu_synid8_ret>`::ref:`u64<amdgpu_synid8_type_dev>`,   :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc                        :ref:`vdata<amdgpu_synid8_data_buf_atomic32>`::ref:`dst<amdgpu_synid8_ret>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc_x2                     :ref:`vdata<amdgpu_synid8_data_buf_atomic64>`::ref:`dst<amdgpu_synid8_ret>`::ref:`u64<amdgpu_synid8_type_dev>`,   :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or                         :ref:`vdata<amdgpu_synid8_data_buf_atomic32>`::ref:`dst<amdgpu_synid8_ret>`,       :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or_x2                      :ref:`vdata<amdgpu_synid8_data_buf_atomic64>`::ref:`dst<amdgpu_synid8_ret>`,       :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax                       :ref:`vdata<amdgpu_synid8_data_buf_atomic32>`::ref:`dst<amdgpu_synid8_ret>`::ref:`s32<amdgpu_synid8_type_dev>`,   :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax_x2                    :ref:`vdata<amdgpu_synid8_data_buf_atomic64>`::ref:`dst<amdgpu_synid8_ret>`::ref:`s64<amdgpu_synid8_type_dev>`,   :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin                       :ref:`vdata<amdgpu_synid8_data_buf_atomic32>`::ref:`dst<amdgpu_synid8_ret>`::ref:`s32<amdgpu_synid8_type_dev>`,   :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin_x2                    :ref:`vdata<amdgpu_synid8_data_buf_atomic64>`::ref:`dst<amdgpu_synid8_ret>`::ref:`s64<amdgpu_synid8_type_dev>`,   :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub                        :ref:`vdata<amdgpu_synid8_data_buf_atomic32>`::ref:`dst<amdgpu_synid8_ret>`,       :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub_x2                     :ref:`vdata<amdgpu_synid8_data_buf_atomic64>`::ref:`dst<amdgpu_synid8_ret>`,       :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap                       :ref:`vdata<amdgpu_synid8_data_buf_atomic32>`::ref:`dst<amdgpu_synid8_ret>`,       :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap_x2                    :ref:`vdata<amdgpu_synid8_data_buf_atomic64>`::ref:`dst<amdgpu_synid8_ret>`,       :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax                       :ref:`vdata<amdgpu_synid8_data_buf_atomic32>`::ref:`dst<amdgpu_synid8_ret>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax_x2                    :ref:`vdata<amdgpu_synid8_data_buf_atomic64>`::ref:`dst<amdgpu_synid8_ret>`::ref:`u64<amdgpu_synid8_type_dev>`,   :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin                       :ref:`vdata<amdgpu_synid8_data_buf_atomic32>`::ref:`dst<amdgpu_synid8_ret>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin_x2                    :ref:`vdata<amdgpu_synid8_data_buf_atomic64>`::ref:`dst<amdgpu_synid8_ret>`::ref:`u64<amdgpu_synid8_type_dev>`,   :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor                        :ref:`vdata<amdgpu_synid8_data_buf_atomic32>`::ref:`dst<amdgpu_synid8_ret>`,       :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor_x2                     :ref:`vdata<amdgpu_synid8_data_buf_atomic64>`::ref:`dst<amdgpu_synid8_ret>`,       :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dword              :ref:`vdst<amdgpu_synid8_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_dwordx2            :ref:`vdst<amdgpu_synid8_dst_buf_64>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dwordx3            :ref:`vdst<amdgpu_synid8_dst_buf_96>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dwordx4            :ref:`vdst<amdgpu_synid8_dst_buf_128>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_x       :ref:`vdst<amdgpu_synid8_dst_buf_d16_32>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_xy      :ref:`vdst<amdgpu_synid8_dst_buf_d16_64>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_xyz     :ref:`vdst<amdgpu_synid8_dst_buf_d16_96>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_xyzw    :ref:`vdst<amdgpu_synid8_dst_buf_d16_128>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_x           :ref:`vdst<amdgpu_synid8_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_format_xy          :ref:`vdst<amdgpu_synid8_dst_buf_64>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_xyz         :ref:`vdst<amdgpu_synid8_dst_buf_96>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_xyzw        :ref:`vdst<amdgpu_synid8_dst_buf_128>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_sbyte              :ref:`vdst<amdgpu_synid8_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_sshort             :ref:`vdst<amdgpu_synid8_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_ubyte              :ref:`vdst<amdgpu_synid8_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_ushort             :ref:`vdst<amdgpu_synid8_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid8_addr_buf>`,           :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_store_byte                        :ref:`vdata<amdgpu_synid8_vdata32_0>`,           :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dword                       :ref:`vdata<amdgpu_synid8_vdata32_0>`,           :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx2                     :ref:`vdata<amdgpu_synid8_vdata64_0>`,           :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx3                     :ref:`vdata<amdgpu_synid8_vdata96_0>`,           :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx4                     :ref:`vdata<amdgpu_synid8_vdata128_0>`,           :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_x                :ref:`vdata<amdgpu_synid8_data_buf_d16_32>`,           :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xy               :ref:`vdata<amdgpu_synid8_data_buf_d16_64>`,           :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xyz              :ref:`vdata<amdgpu_synid8_data_buf_d16_96>`,           :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xyzw             :ref:`vdata<amdgpu_synid8_data_buf_d16_128>`,           :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_x                    :ref:`vdata<amdgpu_synid8_vdata32_0>`,           :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xy                   :ref:`vdata<amdgpu_synid8_vdata64_0>`,           :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyz                  :ref:`vdata<amdgpu_synid8_vdata96_0>`,           :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyzw                 :ref:`vdata<amdgpu_synid8_vdata128_0>`,           :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_lds_dword                   :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,           :ref:`soffset<amdgpu_synid8_offset_buf>`                            :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`lds<amdgpu_synid_lds>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_short                       :ref:`vdata<amdgpu_synid8_vdata32_0>`,           :ref:`vaddr<amdgpu_synid8_addr_buf>`,    :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,    :ref:`soffset<amdgpu_synid8_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_wbinvl1
+    buffer_wbinvl1_vol
+
+SMEM
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_atc_probe                              :ref:`imm3<amdgpu_synid8_perm_smem>`,     :ref:`sbase<amdgpu_synid8_base_smem_addr>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`
+    s_atc_probe_buffer                       :ref:`imm3<amdgpu_synid8_perm_smem>`,     :ref:`sbase<amdgpu_synid8_base_smem_buf>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`
+    s_buffer_load_dword            :ref:`sdst<amdgpu_synid8_sdst32_0>`,     :ref:`sbase<amdgpu_synid8_base_smem_buf>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx16         :ref:`sdst<amdgpu_synid8_sdst512_0>`,     :ref:`sbase<amdgpu_synid8_base_smem_buf>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx2          :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`sbase<amdgpu_synid8_base_smem_buf>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx4          :ref:`sdst<amdgpu_synid8_sdst128_0>`,     :ref:`sbase<amdgpu_synid8_base_smem_buf>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx8          :ref:`sdst<amdgpu_synid8_sdst256_0>`,     :ref:`sbase<amdgpu_synid8_base_smem_buf>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_store_dword                     :ref:`sdata<amdgpu_synid8_sdata32_0>`,    :ref:`sbase<amdgpu_synid8_base_smem_buf>`,    :ref:`soffset<amdgpu_synid8_offset_smem_store>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_store_dwordx2                   :ref:`sdata<amdgpu_synid8_sdata64_0>`,    :ref:`sbase<amdgpu_synid8_base_smem_buf>`,    :ref:`soffset<amdgpu_synid8_offset_smem_store>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_store_dwordx4                   :ref:`sdata<amdgpu_synid8_sdata128_0>`,    :ref:`sbase<amdgpu_synid8_base_smem_buf>`,    :ref:`soffset<amdgpu_synid8_offset_smem_store>`        :ref:`glc<amdgpu_synid_glc>`
+    s_dcache_inv
+    s_dcache_inv_vol
+    s_dcache_wb
+    s_dcache_wb_vol
+    s_load_dword                   :ref:`sdst<amdgpu_synid8_sdst32_0>`,     :ref:`sbase<amdgpu_synid8_base_smem_addr>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx16                :ref:`sdst<amdgpu_synid8_sdst512_0>`,     :ref:`sbase<amdgpu_synid8_base_smem_addr>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx2                 :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`sbase<amdgpu_synid8_base_smem_addr>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx4                 :ref:`sdst<amdgpu_synid8_sdst128_0>`,     :ref:`sbase<amdgpu_synid8_base_smem_addr>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx8                 :ref:`sdst<amdgpu_synid8_sdst256_0>`,     :ref:`sbase<amdgpu_synid8_base_smem_addr>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_memrealtime                  :ref:`sdst<amdgpu_synid8_sdst64_0>`
+    s_memtime                      :ref:`sdst<amdgpu_synid8_sdst64_0>`
+    s_store_dword                            :ref:`sdata<amdgpu_synid8_sdata32_0>`,    :ref:`sbase<amdgpu_synid8_base_smem_addr>`,    :ref:`soffset<amdgpu_synid8_offset_smem_store>`        :ref:`glc<amdgpu_synid_glc>`
+    s_store_dwordx2                          :ref:`sdata<amdgpu_synid8_sdata64_0>`,    :ref:`sbase<amdgpu_synid8_base_smem_addr>`,    :ref:`soffset<amdgpu_synid8_offset_smem_store>`        :ref:`glc<amdgpu_synid_glc>`
+    s_store_dwordx4                          :ref:`sdata<amdgpu_synid8_sdata128_0>`,    :ref:`sbase<amdgpu_synid8_base_smem_addr>`,    :ref:`soffset<amdgpu_synid8_offset_smem_store>`        :ref:`glc<amdgpu_synid_glc>`
+
+SOP1
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_abs_i32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_and_saveexec_b64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_andn2_saveexec_b64           :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_bcnt0_i32_b32                :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_bcnt0_i32_b64                :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_bcnt1_i32_b32                :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_bcnt1_i32_b64                :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_bitset0_b32                  :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_bitset0_b64                  :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`::ref:`b32<amdgpu_synid8_type_dev>`
+    s_bitset1_b32                  :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_bitset1_b64                  :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`::ref:`b32<amdgpu_synid8_type_dev>`
+    s_brev_b32                     :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_brev_b64                     :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_cbranch_join                           :ref:`ssrc<amdgpu_synid8_ssrc32_1>`
+    s_cmov_b32                     :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_cmov_b64                     :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_ff0_i32_b32                  :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_ff0_i32_b64                  :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_ff1_i32_b32                  :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_ff1_i32_b64                  :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_flbit_i32                    :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_flbit_i32_b32                :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_flbit_i32_b64                :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_flbit_i32_i64                :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_getpc_b64                    :ref:`sdst<amdgpu_synid8_sdst64_1>`
+    s_mov_b32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_mov_b64                      :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_mov_fed_b32                  :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_movreld_b32                  :ref:`sdst<amdgpu_synid8_sdst32_0>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_movreld_b64                  :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_movrels_b32                  :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_1>`
+    s_movrels_b64                  :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_1>`
+    s_nand_saveexec_b64            :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_nor_saveexec_b64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_not_b32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_not_b64                      :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_or_saveexec_b64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_orn2_saveexec_b64            :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_quadmask_b32                 :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_quadmask_b64                 :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_rfe_b64                                :ref:`ssrc<amdgpu_synid8_ssrc64_1>`
+    s_set_gpr_idx_idx                        :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_setpc_b64                              :ref:`ssrc<amdgpu_synid8_ssrc64_1>`
+    s_sext_i32_i16                 :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_sext_i32_i8                  :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_swappc_b64                   :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_1>`
+    s_wqm_b32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
+    s_wqm_b64                      :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_xnor_saveexec_b64            :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+    s_xor_saveexec_b64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
+
+SOP2
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**       **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_absdiff_i32                  :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_add_i32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_add_u32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_addc_u32                     :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_and_b32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_and_b64                      :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc64_0>`
+    s_andn2_b32                    :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_andn2_b64                    :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc64_0>`
+    s_ashr_i32                     :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`
+    s_ashr_i64                     :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`
+    s_bfe_i32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`
+    s_bfe_i64                      :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`
+    s_bfe_u32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_bfe_u64                      :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`
+    s_bfm_b32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_bfm_b64                      :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`::ref:`b32<amdgpu_synid8_type_dev>`
+    s_cbranch_g_fork                         :ref:`ssrc0<amdgpu_synid8_ssrc64_2>`,     :ref:`ssrc1<amdgpu_synid8_ssrc64_2>`
+    s_cselect_b32                  :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_cselect_b64                  :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc64_0>`
+    s_lshl_b32                     :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`
+    s_lshl_b64                     :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`
+    s_lshr_b32                     :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`
+    s_lshr_b64                     :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`
+    s_max_i32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_max_u32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_min_i32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_min_u32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_mul_i32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_nand_b32                     :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_nand_b64                     :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc64_0>`
+    s_nor_b32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_nor_b64                      :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc64_0>`
+    s_or_b32                       :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_or_b64                       :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc64_0>`
+    s_orn2_b32                     :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_orn2_b64                     :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc64_0>`
+    s_rfe_restore_b64                        :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`::ref:`b32<amdgpu_synid8_type_dev>`
+    s_sub_i32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_sub_u32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_subb_u32                     :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_xnor_b32                     :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_xnor_b64                     :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc64_0>`
+    s_xor_b32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_xor_b64                      :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,     :ref:`ssrc1<amdgpu_synid8_ssrc64_0>`
+
+SOPC
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **SRC0**      **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_bitcmp0_b32                  :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_bitcmp0_b64                  :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`
+    s_bitcmp1_b32                  :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_bitcmp1_b64                  :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`
+    s_cmp_eq_i32                   :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_cmp_eq_u32                   :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_cmp_eq_u64                   :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc64_0>`
+    s_cmp_ge_i32                   :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_cmp_ge_u32                   :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_cmp_gt_i32                   :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_cmp_gt_u32                   :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_cmp_le_i32                   :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_cmp_le_u32                   :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_cmp_lg_i32                   :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_cmp_lg_u32                   :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_cmp_lg_u64                   :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc64_0>`
+    s_cmp_lt_i32                   :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_cmp_lt_u32                   :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+    s_set_gpr_idx_on               :ref:`ssrc<amdgpu_synid8_ssrc32_0>`,     :ref:`imm4<amdgpu_synid8_imm4>`
+    s_setvskip                     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
+
+SOPK
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_addk_i32                     :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`imm16<amdgpu_synid8_simm16>`
+    s_cbranch_i_fork                         :ref:`ssrc<amdgpu_synid8_ssrc64_3>`,     :ref:`label<amdgpu_synid8_label>`
+    s_cmovk_i32                    :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`imm16<amdgpu_synid8_simm16>`
+    s_cmpk_eq_i32                            :ref:`ssrc<amdgpu_synid8_ssrc32_2>`,     :ref:`imm16<amdgpu_synid8_simm16>`
+    s_cmpk_eq_u32                            :ref:`ssrc<amdgpu_synid8_ssrc32_2>`,     :ref:`imm16<amdgpu_synid8_uimm16>`
+    s_cmpk_ge_i32                            :ref:`ssrc<amdgpu_synid8_ssrc32_2>`,     :ref:`imm16<amdgpu_synid8_simm16>`
+    s_cmpk_ge_u32                            :ref:`ssrc<amdgpu_synid8_ssrc32_2>`,     :ref:`imm16<amdgpu_synid8_uimm16>`
+    s_cmpk_gt_i32                            :ref:`ssrc<amdgpu_synid8_ssrc32_2>`,     :ref:`imm16<amdgpu_synid8_simm16>`
+    s_cmpk_gt_u32                            :ref:`ssrc<amdgpu_synid8_ssrc32_2>`,     :ref:`imm16<amdgpu_synid8_uimm16>`
+    s_cmpk_le_i32                            :ref:`ssrc<amdgpu_synid8_ssrc32_2>`,     :ref:`imm16<amdgpu_synid8_simm16>`
+    s_cmpk_le_u32                            :ref:`ssrc<amdgpu_synid8_ssrc32_2>`,     :ref:`imm16<amdgpu_synid8_uimm16>`
+    s_cmpk_lg_i32                            :ref:`ssrc<amdgpu_synid8_ssrc32_2>`,     :ref:`imm16<amdgpu_synid8_simm16>`
+    s_cmpk_lg_u32                            :ref:`ssrc<amdgpu_synid8_ssrc32_2>`,     :ref:`imm16<amdgpu_synid8_uimm16>`
+    s_cmpk_lt_i32                            :ref:`ssrc<amdgpu_synid8_ssrc32_2>`,     :ref:`imm16<amdgpu_synid8_simm16>`
+    s_cmpk_lt_u32                            :ref:`ssrc<amdgpu_synid8_ssrc32_2>`,     :ref:`imm16<amdgpu_synid8_uimm16>`
+    s_getreg_b32                   :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`hwreg<amdgpu_synid8_hwreg>`
+    s_movk_i32                     :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`imm16<amdgpu_synid8_simm16>`
+    s_mulk_i32                     :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`imm16<amdgpu_synid8_simm16>`
+    s_setreg_b32                   :ref:`hwreg<amdgpu_synid8_hwreg>`,    :ref:`ssrc<amdgpu_synid8_ssrc32_2>`
+    s_setreg_imm32_b32             :ref:`hwreg<amdgpu_synid8_hwreg>`,    :ref:`imm32<amdgpu_synid8_bimm32>`
+
+SOPP
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **SRC**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_barrier
+    s_branch                       :ref:`label<amdgpu_synid8_label>`
+    s_cbranch_cdbgsys              :ref:`label<amdgpu_synid8_label>`
+    s_cbranch_cdbgsys_and_user     :ref:`label<amdgpu_synid8_label>`
+    s_cbranch_cdbgsys_or_user      :ref:`label<amdgpu_synid8_label>`
+    s_cbranch_cdbguser             :ref:`label<amdgpu_synid8_label>`
+    s_cbranch_execnz               :ref:`label<amdgpu_synid8_label>`
+    s_cbranch_execz                :ref:`label<amdgpu_synid8_label>`
+    s_cbranch_scc0                 :ref:`label<amdgpu_synid8_label>`
+    s_cbranch_scc1                 :ref:`label<amdgpu_synid8_label>`
+    s_cbranch_vccnz                :ref:`label<amdgpu_synid8_label>`
+    s_cbranch_vccz                 :ref:`label<amdgpu_synid8_label>`
+    s_decperflevel                 :ref:`imm16<amdgpu_synid8_bimm16>`
+    s_endpgm
+    s_endpgm_saved
+    s_icache_inv
+    s_incperflevel                 :ref:`imm16<amdgpu_synid8_bimm16>`
+    s_nop                          :ref:`imm16<amdgpu_synid8_bimm16>`
+    s_sendmsg                      :ref:`msg<amdgpu_synid8_msg>`
+    s_sendmsghalt                  :ref:`msg<amdgpu_synid8_msg>`
+    s_set_gpr_idx_mode             :ref:`imm4<amdgpu_synid8_imm4>`
+    s_set_gpr_idx_off
+    s_sethalt                      :ref:`imm16<amdgpu_synid8_bimm16>`
+    s_setkill                      :ref:`imm16<amdgpu_synid8_bimm16>`
+    s_setprio                      :ref:`imm16<amdgpu_synid8_bimm16>`
+    s_sleep                        :ref:`imm16<amdgpu_synid8_bimm16>`
+    s_trap                         :ref:`imm16<amdgpu_synid8_bimm16>`
+    s_ttracedata
+    s_waitcnt                      :ref:`waitcnt<amdgpu_synid8_waitcnt>`
+    s_wakeup
+
+VINTRP
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**       **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_interp_mov_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`param<amdgpu_synid8_param>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_interp_p1_f32                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`,      :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_interp_p2_f32                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`,      :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`
+
+VOP1
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC**            **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_bfrev_b32                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_bfrev_b32_dpp                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_bfrev_b32_sdwa               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ceil_f16                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_ceil_f16_dpp                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ceil_f16_sdwa                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ceil_f32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_ceil_f32_dpp                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ceil_f32_sdwa                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ceil_f64                     :ref:`vdst<amdgpu_synid8_vdst64_0>`,     :ref:`src<amdgpu_synid8_src64_0>`
+    v_clrexcp
+    v_cos_f16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cos_f16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cos_f16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cos_f32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cos_f32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cos_f32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_f32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_f16_f32_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f16_f32_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_i16                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_f16_i16_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f16_i16_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_u16                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_f16_u16_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f16_u16_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_f16                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_f32_f16_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_f16_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_f64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src64_0>`
+    v_cvt_f32_i32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_f32_i32_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_i32_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_u32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_f32_u32_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_u32_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte0               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_f32_ubyte0_dpp           :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte0_sdwa          :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte1               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_f32_ubyte1_dpp           :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte1_sdwa          :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte2               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_f32_ubyte2_dpp           :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte2_sdwa          :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte3               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_f32_ubyte3_dpp           :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte3_sdwa          :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f64_f32                  :ref:`vdst<amdgpu_synid8_vdst64_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_f64_i32                  :ref:`vdst<amdgpu_synid8_vdst64_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_f64_u32                  :ref:`vdst<amdgpu_synid8_vdst64_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_flr_i32_f32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_flr_i32_f32_dpp          :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_flr_i32_f32_sdwa         :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_i16_f16                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_i16_f16_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_i16_f16_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_i32_f32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_i32_f32_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_i32_f32_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_i32_f64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src64_0>`
+    v_cvt_off_f32_i4               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_off_f32_i4_dpp           :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_off_f32_i4_sdwa          :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_rpi_i32_f32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_rpi_i32_f32_dpp          :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_rpi_i32_f32_sdwa         :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_u16_f16                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_u16_f16_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_u16_f16_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_u32_f32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_u32_f32_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_u32_f32_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_u32_f64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src64_0>`
+    v_exp_f16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_exp_f16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_exp_f16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_exp_f32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_exp_f32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_exp_f32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_exp_legacy_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_exp_legacy_f32_dpp           :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_exp_legacy_f32_sdwa          :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbh_i32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_ffbh_i32_dpp                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ffbh_i32_sdwa                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbh_u32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_ffbh_u32_dpp                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ffbh_u32_sdwa                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbl_b32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_ffbl_b32_dpp                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ffbl_b32_sdwa                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_floor_f16                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_floor_f16_dpp                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_floor_f16_sdwa               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_floor_f32                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_floor_f32_dpp                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_floor_f32_sdwa               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_floor_f64                    :ref:`vdst<amdgpu_synid8_vdst64_0>`,     :ref:`src<amdgpu_synid8_src64_0>`
+    v_fract_f16                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_fract_f16_dpp                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_fract_f16_sdwa               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_fract_f32                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_fract_f32_dpp                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_fract_f32_sdwa               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_fract_f64                    :ref:`vdst<amdgpu_synid8_vdst64_0>`,     :ref:`src<amdgpu_synid8_src64_0>`
+    v_frexp_exp_i16_f16            :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_frexp_exp_i16_f16_dpp        :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_exp_i16_f16_sdwa       :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_exp_i32_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_frexp_exp_i32_f32_dpp        :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_exp_i32_f32_sdwa       :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_exp_i32_f64            :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src64_0>`
+    v_frexp_mant_f16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_frexp_mant_f16_dpp           :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_mant_f16_sdwa          :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_mant_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_frexp_mant_f32_dpp           :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_mant_f32_sdwa          :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_mant_f64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,     :ref:`src<amdgpu_synid8_src64_0>`
+    v_log_f16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_log_f16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_log_f16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_log_f32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_log_f32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_log_f32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_log_legacy_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_log_legacy_f32_dpp           :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_log_legacy_f32_sdwa          :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_mov_b32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_mov_b32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mov_b32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_mov_fed_b32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_mov_fed_b32_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mov_fed_b32_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_movreld_b32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_movrels_b32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
+    v_movrelsd_b32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
+    v_nop
+    v_not_b32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_not_b32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_not_b32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rcp_f16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_rcp_f16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rcp_f16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rcp_f32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_rcp_f32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rcp_f32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rcp_f64                      :ref:`vdst<amdgpu_synid8_vdst64_0>`,     :ref:`src<amdgpu_synid8_src64_0>`
+    v_rcp_iflag_f32                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_rcp_iflag_f32_dpp            :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rcp_iflag_f32_sdwa           :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_readfirstlane_b32            :ref:`sdst<amdgpu_synid8_sdst32_2>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
+    v_rndne_f16                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_rndne_f16_dpp                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rndne_f16_sdwa               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rndne_f32                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_rndne_f32_dpp                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rndne_f32_sdwa               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rndne_f64                    :ref:`vdst<amdgpu_synid8_vdst64_0>`,     :ref:`src<amdgpu_synid8_src64_0>`
+    v_rsq_f16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_rsq_f16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rsq_f16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rsq_f32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_rsq_f32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rsq_f32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rsq_f64                      :ref:`vdst<amdgpu_synid8_vdst64_0>`,     :ref:`src<amdgpu_synid8_src64_0>`
+    v_sin_f16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_sin_f16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sin_f16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sin_f32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_sin_f32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sin_f32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sqrt_f16                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_sqrt_f16_dpp                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sqrt_f16_sdwa                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sqrt_f32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_sqrt_f32_dpp                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sqrt_f32_sdwa                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sqrt_f64                     :ref:`vdst<amdgpu_synid8_vdst64_0>`,     :ref:`src<amdgpu_synid8_src64_0>`
+    v_trunc_f16                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_trunc_f16_dpp                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_trunc_f16_sdwa               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_trunc_f32                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_trunc_f32_dpp                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_trunc_f32_sdwa               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_trunc_f64                    :ref:`vdst<amdgpu_synid8_vdst64_0>`,     :ref:`src<amdgpu_synid8_src64_0>`
+
+VOP2
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST0**      **DST1**      **SRC0**         **SRC1**        **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_add_f16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_add_f16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_f16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_f32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_add_f32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_f32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_u16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_add_u16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_u16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_u32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_add_u32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_u32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_addc_u32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`
+    v_addc_u32_dpp                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`            :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_addc_u32_sdwa                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid8_vcc_64>`            :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_and_b32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_and_b32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_and_b32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ashrrev_i16                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_ashrrev_i16_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ashrrev_i16_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ashrrev_i32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_ashrrev_i32_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ashrrev_i32_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cndmask_b32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`
+    v_cndmask_b32_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`            :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cndmask_b32_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid8_vcc_64>`            :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ldexp_f16                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`i16<amdgpu_synid8_type_dev>`
+    v_ldexp_f16_dpp                :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`i16<amdgpu_synid8_type_dev>`                  :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ldexp_f16_sdwa               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`i16<amdgpu_synid8_type_dev>`                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshlrev_b16                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_lshlrev_b16_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshlrev_b16_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshlrev_b32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_lshlrev_b32_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshlrev_b32_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b16                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_lshrrev_b16_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshrrev_b16_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_lshrrev_b32_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshrrev_b32_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mac_f16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_mac_f16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mac_f16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mac_f32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_mac_f32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mac_f32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_madak_f16                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`imm32<amdgpu_synid8_fimm16>`
+    v_madak_f32                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`imm32<amdgpu_synid8_fimm32>`
+    v_madmk_f16                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`imm32<amdgpu_synid8_fimm16>`,      :ref:`vsrc2<amdgpu_synid8_vsrc32_0>`
+    v_madmk_f32                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`imm32<amdgpu_synid8_fimm32>`,      :ref:`vsrc2<amdgpu_synid8_vsrc32_0>`
+    v_max_f16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_max_f16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_f16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_f32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_max_f32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_f32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_i16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_max_i16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_i16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_i32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_max_i32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_i32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_u16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_max_u16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_u16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_u32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_max_u32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_u32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_f16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_min_f16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_f16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_f32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_min_f32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_f32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_i16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_min_i16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_i16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_i32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_min_i32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_i32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_u16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_min_u16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_u16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_u32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_min_u32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_u32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_f16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_mul_f16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_f16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_f32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_mul_f32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_f32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_hi_i32_i24               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_mul_hi_i32_i24_dpp           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_hi_i32_i24_sdwa          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_hi_u32_u24               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_mul_hi_u32_u24_dpp           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_hi_u32_u24_sdwa          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_i32_i24                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_mul_i32_i24_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_i32_i24_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_legacy_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_mul_legacy_f32_dpp           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_legacy_f32_sdwa          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_lo_u16                   :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_mul_lo_u16_dpp               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_lo_u16_sdwa              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_u32_u24                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_mul_u32_u24_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_u32_u24_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_or_b32                       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_or_b32_dpp                   :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_or_b32_sdwa                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_f16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_sub_f16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_f16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_f32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_sub_f32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_f32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_u16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_sub_u16_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_u16_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_u32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_sub_u32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_u32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subb_u32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`
+    v_subb_u32_dpp                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`            :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subb_u32_sdwa                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid8_vcc_64>`            :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subbrev_u32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`
+    v_subbrev_u32_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`            :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subbrev_u32_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid8_vcc_64>`            :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_f16                   :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_subrev_f16_dpp               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_f16_sdwa              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_f32                   :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_subrev_f32_dpp               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_f32_sdwa              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_u16                   :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_subrev_u16_dpp               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_u16_sdwa              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_u32                   :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_subrev_u32_dpp               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_u32_sdwa              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_xor_b32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_xor_b32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_xor_b32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+
+VOP3
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST0**       **DST1**      **SRC0**         **SRC1**        **SRC2**               **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_add_f16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_f64                      :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_u16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_add_u32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_addc_u32_e64                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
+    v_alignbit_b32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
+    v_alignbyte_b32                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
+    v_and_b32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_ashrrev_i16_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`
+    v_ashrrev_i32_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`
+    v_ashrrev_i64                  :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
+    v_bcnt_u32_b32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_bfe_i32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`
+    v_bfe_u32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
+    v_bfi_b32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
+    v_bfm_b32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_bfrev_b32_e64                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`
+    v_ceil_f16_e64                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_ceil_f32_e64                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ceil_f64_e64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_clrexcp_e64
+    v_cmp_class_f16_e64            :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmp_class_f32_e64            :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmp_class_f64_e64            :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmp_eq_f16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_f32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_f64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_i16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_eq_i32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_eq_i64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_eq_u16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_eq_u32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_eq_u64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_f_f16_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f32_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f64_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_i16_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_f_i32_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_f_i64_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_f_u16_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_f_u32_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_f_u64_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_ge_f16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_i16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_ge_i32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_ge_i64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_ge_u16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_ge_u32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_ge_u64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_gt_f16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_i16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_gt_i32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_gt_i64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_gt_u16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_gt_u32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_gt_u64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_le_f16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_i16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_le_i32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_le_i64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_le_u16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_le_u32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_le_u64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_lg_f16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_i16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_lt_i32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_lt_i64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_lt_u16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_lt_u32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_lt_u64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_ne_i16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_ne_i32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_ne_i64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_ne_u16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_ne_u32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_ne_u64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_neq_f16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f16_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f32_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f64_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_t_i16_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_t_i32_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_t_i64_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_t_u16_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_t_u32_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_t_u64_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmp_tru_f16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f16_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f32_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f64_e64                :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_class_f16_e64           :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmpx_class_f32_e64           :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmpx_class_f64_e64           :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmpx_eq_f16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_f32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_f64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_i16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_eq_i32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_eq_i64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_eq_u16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_eq_u32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_eq_u64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_f_f16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_i16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_f_i32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_f_i64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_f_u16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_f_u32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_f_u64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_ge_f16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_i16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_ge_i32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_ge_i64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_ge_u16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_ge_u32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_ge_u64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_gt_f16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_i16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_gt_i32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_gt_i64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_gt_u16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_gt_u32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_gt_u64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_le_f16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_i16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_le_i32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_le_i64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_le_u16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_le_u32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_le_u64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_lg_f16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_i16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_lt_i32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_lt_i64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_lt_u16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_lt_u32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_lt_u64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_ne_i16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_ne_i32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_ne_i64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_ne_u16_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_ne_u32_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_ne_u64_e64              :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_neq_f16_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f32_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f64_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f16_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f32_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f64_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f16_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f32_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f64_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f16_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f32_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f64_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f16_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f32_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f64_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f16_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f32_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f64_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_t_i16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_t_i32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_t_i64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_t_u16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_t_u32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_t_u64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
+    v_cmpx_tru_f16_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f32_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f64_e64             :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f16_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f32_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f64_e64               :ref:`sdst<amdgpu_synid8_sdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cndmask_b32_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
+    v_cos_f16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_cos_f32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubeid_f32                   :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubema_f32                   :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubesc_f32                   :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubetc_f32                   :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_f32_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_i16_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f16_u16_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_f16_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_f64_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_i32_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_u32_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte0_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte1_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte2_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte3_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_f32_e64              :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_i32_e64              :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src<amdgpu_synid8_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_u32_e64              :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src<amdgpu_synid8_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_flr_i32_f32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_i16_f16_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_i32_f32_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_i32_f64_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_off_f32_i4_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_i16_i32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cvt_pk_u16_u32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cvt_pk_u8_f32                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`
+    v_cvt_pkaccum_u8_f32           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`
+    v_cvt_pknorm_i16_f32           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_pknorm_u16_f32           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_pkrtz_f16_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_rpi_i32_f32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_u16_f16_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_u32_f32_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_u32_f64_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_div_fixup_f16                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fixup_f32                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f64                :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_scale_f32                :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
+    v_div_scale_f64                :ref:`vdst<amdgpu_synid8_vdst64_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`,       :ref:`src2<amdgpu_synid8_src64_1>`
+    v_exp_f16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_exp_f32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_legacy_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_i32_e64                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`
+    v_ffbh_u32_e64                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`
+    v_ffbl_b32_e64                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`
+    v_floor_f16_e64                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_floor_f32_e64                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_floor_f64_e64                :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_f32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f64                      :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f16_e64                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_fract_f32_e64                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f64_e64                :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_exp_i16_f16_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_frexp_exp_i32_f32_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_frexp_exp_i32_f64_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_frexp_mant_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_frexp_mant_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f64_e64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_mov_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`param<amdgpu_synid8_param>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1_f32_e64            :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1ll_f16              :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`f32<amdgpu_synid8_type_dev>`,            :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid8_type_dev>`,  :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`                       :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1lv_f16              :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`f32<amdgpu_synid8_type_dev>`,            :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid8_type_dev>`, :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`vsrc2<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f16x2<amdgpu_synid8_type_dev>`      :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p2_f16                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid8_type_dev>`, :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`vsrc2<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid8_type_dev>`        :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_interp_p2_f32_e64            :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f16_e64                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`i16<amdgpu_synid8_type_dev>`                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_ldexp_f32                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`i32<amdgpu_synid8_type_dev>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f64                    :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`i32<amdgpu_synid8_type_dev>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lerp_u8                      :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,            :ref:`src0<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_log_f16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_log_f32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_log_legacy_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lshlrev_b16_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`
+    v_lshlrev_b32_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`
+    v_lshlrev_b64                  :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
+    v_lshrrev_b16_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`
+    v_lshrrev_b32_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`
+    v_lshrrev_b64                  :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
+    v_mac_f16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_mac_f32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_f32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`               :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i24                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`::ref:`i32<amdgpu_synid8_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i64_i32                  :ref:`vdst<amdgpu_synid8_vdst64_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src64_1>`::ref:`i64<amdgpu_synid8_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_legacy_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`               :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u24                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u64_u32                  :ref:`vdst<amdgpu_synid8_vdst64_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src64_1>`::ref:`u64<amdgpu_synid8_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_f32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_i32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
+    v_max3_u32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
+    v_max_f16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_f32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_f64                      :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_i16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_max_i32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_max_u16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_max_u32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_mbcnt_hi_u32_b32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_mbcnt_lo_u32_b32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_med3_f32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_i32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
+    v_med3_u32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
+    v_min3_f32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_i32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
+    v_min3_u32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
+    v_min_f16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_f32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_f64                      :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_i16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_min_i32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_min_u16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_min_u32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_mov_b32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`
+    v_mov_fed_b32_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`
+    v_movreld_b32_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`
+    v_movrels_b32_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
+    v_movrelsd_b32_e64             :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
+    v_mqsad_pk_u16_u8              :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b64<amdgpu_synid8_type_dev>`,            :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_mqsad_u32_u8                 :ref:`vdst<amdgpu_synid8_vdst128_0>`::ref:`b128<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`vsrc2<amdgpu_synid8_vsrc128_0>`::ref:`b128<amdgpu_synid8_type_dev>`         :ref:`clamp<amdgpu_synid_clamp>`
+    v_msad_u8                      :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,            :ref:`src0<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_f64                      :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_i32                   :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_mul_hi_i32_i24_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_mul_hi_u32                   :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_mul_hi_u32_u24_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_mul_i32_i24_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_mul_legacy_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_u16_e64               :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_mul_lo_u32                   :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_mul_u32_u24_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_nop_e64
+    v_not_b32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`
+    v_or_b32_e64                   :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_perm_b32                     :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
+    v_qsad_pk_u16_u8               :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b64<amdgpu_synid8_type_dev>`,            :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_f64_e64                  :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_iflag_f32_e64            :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_readlane_b32                 :ref:`sdst<amdgpu_synid8_sdst32_2>`,                :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`ssrc1<amdgpu_synid8_ssrc32_3>`
+    v_rndne_f16_e64                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_rndne_f32_e64                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f64_e64                :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_rsq_f32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f64_e64                  :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_hi_u8                    :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,            :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u8x4<amdgpu_synid8_type_dev>`,   :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u8x4<amdgpu_synid8_type_dev>`,  :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u16                      :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,            :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16x2<amdgpu_synid8_type_dev>`,  :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u16x2<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`               :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u8                       :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,            :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u8x4<amdgpu_synid8_type_dev>`,   :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u8x4<amdgpu_synid8_type_dev>`,  :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_sin_f16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_sin_f32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f16_e64                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_sqrt_f32_e64                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f64_e64                 :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_f16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_f32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_u16_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_sub_u32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_subb_u32_e64                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
+    v_subbrev_u32_e64              :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
+    v_subrev_f16_e64               :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f32_e64               :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_u16_e64               :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_subrev_u32_e64               :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_trig_preop_f64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f16_e64                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_trunc_f32_e64                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f64_e64                :ref:`vdst<amdgpu_synid8_vdst64_0>`,                :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_writelane_b32                :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`ssrc0<amdgpu_synid8_ssrc32_4>`,       :ref:`ssrc1<amdgpu_synid8_ssrc32_3>`
+    v_xor_b32_e64                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,                :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+
+VOPC
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**             **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_cmp_class_f16                :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmp_class_f16_sdwa           :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`b32<amdgpu_synid8_type_dev>`      :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_class_f32                :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmp_class_f32_sdwa           :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`b32<amdgpu_synid8_type_dev>`      :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_class_f64                :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmp_eq_f16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_eq_f16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_eq_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_eq_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_eq_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_eq_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_eq_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_eq_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_eq_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_u64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_f_f16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_f_f16_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_f32                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_f_f32_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_f64                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_f_i16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_f_i16_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_i32                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_f_i32_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_i64                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_f_u16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_f_u16_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_u32                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_f_u32_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_u64                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_ge_f16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ge_f16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ge_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_ge_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ge_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ge_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_ge_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ge_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ge_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_u64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_gt_f16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_gt_f16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_gt_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_gt_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_gt_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_gt_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_gt_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_gt_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_gt_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_u64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_le_f16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_le_f16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_le_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_le_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_le_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_le_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_le_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_le_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_le_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_u64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_lg_f16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_lg_f16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lg_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_lg_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lg_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_lt_f16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_lt_f16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_lt_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_lt_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_lt_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_lt_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_lt_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_lt_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_lt_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_u64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_ne_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ne_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ne_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_ne_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ne_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ne_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_u64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_neq_f16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_neq_f16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_neq_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_neq_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_neq_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_nge_f16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_nge_f16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nge_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_nge_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nge_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_ngt_f16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ngt_f16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ngt_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ngt_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ngt_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_nle_f16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_nle_f16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nle_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_nle_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nle_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_nlg_f16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_nlg_f16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlg_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_nlg_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlg_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_nlt_f16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_nlt_f16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlt_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_nlt_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlt_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_o_f16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_o_f16_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_o_f32                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_o_f32_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_o_f64                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_t_i16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_t_i16_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_i32                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_t_i32_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_i64                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_t_u16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_t_u16_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_u32                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_t_u32_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_u64                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_tru_f16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_tru_f16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_tru_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_tru_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_tru_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmp_u_f16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_u_f16_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_u_f32                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_u_f32_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_u_f64                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_class_f16               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmpx_class_f16_sdwa          :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`b32<amdgpu_synid8_type_dev>`      :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_class_f32               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmpx_class_f32_sdwa          :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`b32<amdgpu_synid8_type_dev>`      :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_class_f64               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmpx_eq_f16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_eq_f16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_eq_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_eq_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_eq_i16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_i32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_eq_i32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_i64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_eq_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_eq_u16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_u32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_eq_u32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_u64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_f_f16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_f_f16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_f_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_f_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_f_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_f_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_f_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_f_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_f_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_u64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_ge_f16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ge_f16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ge_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_ge_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ge_i16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_i32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ge_i32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_i64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_ge_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ge_u16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_u32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ge_u32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_u64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_gt_f16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_gt_f16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_gt_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_gt_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_gt_i16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_i32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_gt_i32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_i64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_gt_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_gt_u16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_u32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_gt_u32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_u64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_le_f16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_le_f16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_le_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_le_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_le_i16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_i32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_le_i32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_i64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_le_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_le_u16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_u32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_le_u32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_u64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_lg_f16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_lg_f16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lg_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_lg_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lg_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_lt_f16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_lt_f16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_lt_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_lt_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_lt_i16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_i32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_lt_i32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_i64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_lt_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_lt_u16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_u32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_lt_u32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_u64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_ne_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ne_i16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_i32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ne_i32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_i64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_ne_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ne_u16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_u32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ne_u32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_u64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_neq_f16                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_neq_f16_sdwa            :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_neq_f32                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_neq_f32_sdwa            :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_neq_f64                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_nge_f16                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_nge_f16_sdwa            :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nge_f32                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_nge_f32_sdwa            :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nge_f64                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_ngt_f16                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ngt_f16_sdwa            :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ngt_f32                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ngt_f32_sdwa            :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ngt_f64                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_nle_f16                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_nle_f16_sdwa            :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nle_f32                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_nle_f32_sdwa            :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nle_f64                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_nlg_f16                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_nlg_f16_sdwa            :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlg_f32                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_nlg_f32_sdwa            :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlg_f64                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_nlt_f16                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_nlt_f16_sdwa            :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlt_f32                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_nlt_f32_sdwa            :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlt_f64                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_o_f16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_o_f16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_o_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_o_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_o_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_t_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_t_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_t_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_t_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_t_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_t_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_u64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_tru_f16                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_tru_f16_sdwa            :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_tru_f32                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_tru_f32_sdwa            :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_tru_f64                 :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+    v_cmpx_u_f16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_u_f16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_u_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_u_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_u_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
+
+.. |---| unicode:: U+02014 .. em dash
+
+
+.. toctree::
+    :hidden:
+
+    gfx8_attr
+    gfx8_bimm16
+    gfx8_bimm32
+    gfx8_fimm16
+    gfx8_fimm32
+    gfx8_hwreg
+    gfx8_imm4
+    gfx8_label
+    gfx8_msg
+    gfx8_param
+    gfx8_perm_smem
+    gfx8_simm16
+    gfx8_tgt
+    gfx8_uimm16
+    gfx8_waitcnt
+    gfx8_addr_buf
+    gfx8_addr_ds
+    gfx8_addr_flat
+    gfx8_addr_mimg
+    gfx8_base_smem_addr
+    gfx8_base_smem_buf
+    gfx8_data_buf_atomic128
+    gfx8_data_buf_atomic32
+    gfx8_data_buf_atomic64
+    gfx8_data_buf_d16_128
+    gfx8_data_buf_d16_32
+    gfx8_data_buf_d16_64
+    gfx8_data_buf_d16_96
+    gfx8_data_mimg_atomic_cmp
+    gfx8_data_mimg_atomic_reg
+    gfx8_data_mimg_store
+    gfx8_data_mimg_store_d16
+    gfx8_dst_buf_128
+    gfx8_dst_buf_64
+    gfx8_dst_buf_96
+    gfx8_dst_buf_d16_128
+    gfx8_dst_buf_d16_32
+    gfx8_dst_buf_d16_64
+    gfx8_dst_buf_d16_96
+    gfx8_dst_buf_lds
+    gfx8_dst_flat_atomic32
+    gfx8_dst_flat_atomic64
+    gfx8_dst_mimg_gather4
+    gfx8_dst_mimg_regular
+    gfx8_dst_mimg_regular_d16
+    gfx8_offset_buf
+    gfx8_offset_smem_load
+    gfx8_offset_smem_store
+    gfx8_rsrc_buf
+    gfx8_rsrc_mimg
+    gfx8_samp_mimg
+    gfx8_sdata128_0
+    gfx8_sdata32_0
+    gfx8_sdata64_0
+    gfx8_sdst128_0
+    gfx8_sdst256_0
+    gfx8_sdst32_0
+    gfx8_sdst32_1
+    gfx8_sdst32_2
+    gfx8_sdst512_0
+    gfx8_sdst64_0
+    gfx8_sdst64_1
+    gfx8_src32_0
+    gfx8_src32_1
+    gfx8_src64_0
+    gfx8_src64_1
+    gfx8_src_exp
+    gfx8_ssrc32_0
+    gfx8_ssrc32_1
+    gfx8_ssrc32_2
+    gfx8_ssrc32_3
+    gfx8_ssrc32_4
+    gfx8_ssrc64_0
+    gfx8_ssrc64_1
+    gfx8_ssrc64_2
+    gfx8_ssrc64_3
+    gfx8_vcc_64
+    gfx8_vdata128_0
+    gfx8_vdata32_0
+    gfx8_vdata64_0
+    gfx8_vdata96_0
+    gfx8_vdst128_0
+    gfx8_vdst32_0
+    gfx8_vdst64_0
+    gfx8_vdst96_0
+    gfx8_vsrc128_0
+    gfx8_vsrc32_0
+    gfx8_vsrc64_0
+    gfx8_mod_dpp_sdwa_abs_neg
+    gfx8_mod_sdwa_sext
+    gfx8_mod_vop3_abs_neg
+    gfx8_opt
+    gfx8_ret
+    gfx8_type_dev

diff --git a/docs/AMDGPU/AMDGPUAsmGFX9.rst b/docs/AMDGPU/AMDGPUAsmGFX9.rst
new file mode 100644 (file)
index 0000000..71052d0
--- /dev/null
+++ b/docs/AMDGPU/AMDGPUAsmGFX9.rst
@@ -0,0 +1,2102 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+============================
+Syntax of GFX9 Instructions
+============================
+
+.. contents::
+  :local:
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Introduction
+============
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+DS
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**         **SRC0**      **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    ds_add_f32                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_f32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_u64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_f32                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_u32                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_u64                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_u32                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_u64                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_b32                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_b64                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_rtn_b32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_rtn_b64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_src2_b32                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_src2_b64                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_append                      :ref:`vdst<amdgpu_synid9_vdst32_0>`                                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_bpermute_b32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
+    ds_cmpst_b32                               :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata32_0>`,   :ref:`vdata1<amdgpu_synid9_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_b64                               :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata64_0>`,   :ref:`vdata1<amdgpu_synid9_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_f32                               :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata32_0>`,   :ref:`vdata1<amdgpu_synid9_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_f64                               :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata64_0>`,   :ref:`vdata1<amdgpu_synid9_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_b32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata32_0>`,   :ref:`vdata1<amdgpu_synid9_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_b64               :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata64_0>`,   :ref:`vdata1<amdgpu_synid9_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_f32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata32_0>`,   :ref:`vdata1<amdgpu_synid9_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_f64               :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata64_0>`,   :ref:`vdata1<amdgpu_synid9_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_condxchg32_rtn_b64          :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_consume                     :ref:`vdst<amdgpu_synid9_vdst32_0>`                                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_rtn_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_rtn_u64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_src2_u32                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_src2_u64                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_u32                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_u64                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_barrier                             :ref:`vdata<amdgpu_synid9_vdata32_0>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_init                                :ref:`vdata<amdgpu_synid9_vdata32_0>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_br                             :ref:`vdata<amdgpu_synid9_vdata32_0>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_p                                                                 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_release_all                                                       :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_v                                                                 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_rtn_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_rtn_u64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_src2_u32                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_src2_u64                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_u32                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_u64                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_f32                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_f64                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_i32                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_i64                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_f32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_f64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_i32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_i64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_u64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_f32                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_f64                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_i32                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_i64                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_u32                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_u64                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_u32                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_u64                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_f32                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_f64                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_i32                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_i64                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_f32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_f64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_i32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_i64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_u64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_f32                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_f64                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_i32                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_i64                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_u32                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_u64                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_u32                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_u64                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_b32                               :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata32_0>`,   :ref:`vdata1<amdgpu_synid9_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_b64                               :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata64_0>`,   :ref:`vdata1<amdgpu_synid9_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_rtn_b32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata32_0>`,   :ref:`vdata1<amdgpu_synid9_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_rtn_b64               :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata64_0>`,   :ref:`vdata1<amdgpu_synid9_vdata64_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_nop
+    ds_or_b32                                  :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_b64                                  :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_rtn_b32                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_rtn_b64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_src2_b32                             :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_src2_b64                             :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_ordered_count               :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_permute_b32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
+    ds_read2_b32                   :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2_b64                   :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2st64_b32               :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2st64_b64               :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b128                   :ref:`vdst<amdgpu_synid9_vdst128_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b32                    :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b64                    :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b96                    :ref:`vdst<amdgpu_synid9_vdst96_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i16                    :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i8                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i8_d16                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i8_d16_hi              :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u16                    :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u16_d16                :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u16_d16_hi             :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u8                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u8_d16                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u8_d16_hi              :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_rtn_u32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_rtn_u64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_src2_u32                           :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_src2_u64                           :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_u32                                :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_u64                                :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_rtn_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_rtn_u64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_src2_u32                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_src2_u64                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_u32                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_u64                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_swizzle_b32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`sw_offset16<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrap_rtn_b32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata32_0>`,   :ref:`vdata1<amdgpu_synid9_vdata32_0>`         :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2_b32                              :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata32_0>`,   :ref:`vdata1<amdgpu_synid9_vdata32_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2_b64                              :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata64_0>`,   :ref:`vdata1<amdgpu_synid9_vdata64_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2st64_b32                          :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata32_0>`,   :ref:`vdata1<amdgpu_synid9_vdata32_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2st64_b64                          :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata64_0>`,   :ref:`vdata1<amdgpu_synid9_vdata64_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b128                              :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata128_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b16                               :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b16_d16_hi                        :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b32                               :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b64                               :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b8                                :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b8_d16_hi                         :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b96                               :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata96_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_src2_b32                          :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_src2_b64                          :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2_rtn_b32             :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata32_0>`,   :ref:`vdata1<amdgpu_synid9_vdata32_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2_rtn_b64             :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata64_0>`,   :ref:`vdata1<amdgpu_synid9_vdata64_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2st64_rtn_b32         :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata32_0>`,   :ref:`vdata1<amdgpu_synid9_vdata32_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2st64_rtn_b64         :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata64_0>`,   :ref:`vdata1<amdgpu_synid9_vdata64_0>`         :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg_rtn_b32              :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg_rtn_b64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_b32                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_b64                                 :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_rtn_b32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_rtn_b64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                    :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_src2_b32                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_src2_b64                            :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+
+EXP
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**      **SRC2**      **SRC3**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    exp                            :ref:`tgt<amdgpu_synid9_tgt>`,      :ref:`vsrc0<amdgpu_synid9_src_exp>`,    :ref:`vsrc1<amdgpu_synid9_src_exp>`,    :ref:`vsrc2<amdgpu_synid9_src_exp>`,    :ref:`vsrc3<amdgpu_synid9_src_exp>`          :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+
+FLAT
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**           **SRC0**      **SRC1**         **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    flat_atomic_add                :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_add_x2             :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_and                :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_and_x2             :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_cmpswap            :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_cmpswap_x2         :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_dec                :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`                   :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_dec_x2             :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`                   :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_inc                :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`                   :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_inc_x2             :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`                   :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_or                 :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_or_x2              :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smax               :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`s32<amdgpu_synid9_type_dev>`                   :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smax_x2            :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`s64<amdgpu_synid9_type_dev>`                   :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smin               :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`s32<amdgpu_synid9_type_dev>`                   :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smin_x2            :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`s64<amdgpu_synid9_type_dev>`                   :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_sub                :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_sub_x2             :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_swap               :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_swap_x2            :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umax               :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`                   :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umax_x2            :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`                   :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umin               :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`                   :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umin_x2            :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`                   :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_xor                :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_xor_x2             :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dword                :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_addr_flat>`                                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx2              :ref:`vdst<amdgpu_synid9_vdst64_0>`,         :ref:`vaddr<amdgpu_synid9_addr_flat>`                                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx3              :ref:`vdst<amdgpu_synid9_vdst96_0>`,         :ref:`vaddr<amdgpu_synid9_addr_flat>`                                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx4              :ref:`vdst<amdgpu_synid9_vdst128_0>`,         :ref:`vaddr<amdgpu_synid9_addr_flat>`                                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sbyte                :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_addr_flat>`                                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sbyte_d16            :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_addr_flat>`                                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sbyte_d16_hi         :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_addr_flat>`                                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_short_d16            :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_addr_flat>`                                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_short_d16_hi         :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_addr_flat>`                                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sshort               :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_addr_flat>`                                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ubyte                :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_addr_flat>`                                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ubyte_d16            :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_addr_flat>`                                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ubyte_d16_hi         :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_addr_flat>`                                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ushort               :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_addr_flat>`                                 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_byte                              :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_byte_d16_hi                       :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dword                             :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx2                           :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx3                           :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata96_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx4                           :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata128_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_short                             :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_short_d16_hi                      :ref:`vaddr<amdgpu_synid9_addr_flat>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                       :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_add              :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_add_x2           :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_and              :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_and_x2           :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_cmpswap          :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_cmpswap_x2       :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_dec              :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_dec_x2           :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_inc              :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_inc_x2           :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_or               :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_or_x2            :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_smax             :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`s32<amdgpu_synid9_type_dev>`,   :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_smax_x2          :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`s64<amdgpu_synid9_type_dev>`,   :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_smin             :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`s32<amdgpu_synid9_type_dev>`,   :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_smin_x2          :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`s64<amdgpu_synid9_type_dev>`,   :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_sub              :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_sub_x2           :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_swap             :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_swap_x2          :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_umax             :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_umax_x2          :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_umin             :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_umin_x2          :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_xor              :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_xor_x2           :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`,     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_dword              :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_global>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_dwordx2            :ref:`vdst<amdgpu_synid9_vdst64_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_global>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_dwordx3            :ref:`vdst<amdgpu_synid9_vdst96_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_global>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_dwordx4            :ref:`vdst<amdgpu_synid9_vdst128_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_global>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_sbyte              :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_global>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_sbyte_d16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_global>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_sbyte_d16_hi       :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_global>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_short_d16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_global>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_short_d16_hi       :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_global>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_sshort             :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_global>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_ubyte              :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_global>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_ubyte_d16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_global>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_ubyte_d16_hi       :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_global>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_ushort             :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_global>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_store_byte                            :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_store_byte_d16_hi                     :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_store_dword                           :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_store_dwordx2                         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_store_dwordx3                         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata96_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_store_dwordx4                         :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata128_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_store_short                           :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_store_short_d16_hi                    :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_global>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_dword             :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_dwordx2           :ref:`vdst<amdgpu_synid9_vdst64_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_dwordx3           :ref:`vdst<amdgpu_synid9_vdst96_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_dwordx4           :ref:`vdst<amdgpu_synid9_vdst128_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_sbyte             :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_sbyte_d16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_sbyte_d16_hi      :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_short_d16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_short_d16_hi      :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_sshort            :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_ubyte             :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_ubyte_d16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_ubyte_d16_hi      :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_ushort            :ref:`vdst<amdgpu_synid9_vdst32_0>`,         :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`                       :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_byte                           :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_byte_d16_hi                    :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_dword                          :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_dwordx2                        :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid9_vdata64_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_dwordx3                        :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid9_vdata96_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_dwordx4                        :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid9_vdata128_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_short                          :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_short_d16_hi                   :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`,       :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>`          :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
+MIMG
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**       **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    image_atomic_add                         :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_and                         :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_cmpswap                     :ref:`vdata<amdgpu_synid9_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_dec                         :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_inc                         :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_or                          :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_smax                        :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_smin                        :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_sub                         :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_swap                        :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_umax                        :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_umin                        :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_xor                         :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4                  :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b                :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_cl             :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_cl_o           :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_o              :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c                :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b              :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_cl           :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_cl_o         :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_o            :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_cl             :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_cl_o           :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_l              :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_l_o            :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_lz             :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_lz_o           :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_o              :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_cl               :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_cl_o             :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_l                :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_l_o              :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_lz               :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_lz_o             :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_o                :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_get_lod                  :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_get_resinfo              :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load                     :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_load_mip                 :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_load_mip_pck             :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_mip_pck_sgn         :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_pck                 :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_pck_sgn             :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample                   :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b                 :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_cl              :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_cl_o            :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_o               :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c                 :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b               :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_cl            :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_cl_o          :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_o             :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd              :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_cl           :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_cl_o         :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_o            :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cl              :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cl_o            :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d               :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_cl            :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_cl_o          :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_o             :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_l               :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_l_o             :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_lz              :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_lz_o            :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_o               :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd                :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_cl             :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_cl_o           :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_o              :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cl                :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cl_o              :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d                 :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_cl              :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_cl_o            :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_o               :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_l                 :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_l_o               :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_lz                :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_lz_o              :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_o                 :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid9_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_store                              :ref:`vdata<amdgpu_synid9_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_store_mip                          :ref:`vdata<amdgpu_synid9_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_store_mip_pck                      :ref:`vdata<amdgpu_synid9_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_store_pck                          :ref:`vdata<amdgpu_synid9_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,    :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+
+MUBUF
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**             **SRC1**      **SRC2**      **SRC3**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    buffer_atomic_add                        :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_add_x2                     :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and                        :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and_x2                     :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap                    :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap_x2                 :ref:`vdata<amdgpu_synid9_data_buf_atomic128>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec                        :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec_x2                     :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc                        :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc_x2                     :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or                         :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or_x2                      :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax                       :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`,   :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax_x2                    :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`,   :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin                       :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`,   :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin_x2                    :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`,   :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub                        :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub_x2                     :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap                       :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap_x2                    :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax                       :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax_x2                    :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin                       :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin_x2                    :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor                        :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor_x2                     :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dword              :ref:`vdst<amdgpu_synid9_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_dwordx2            :ref:`vdst<amdgpu_synid9_dst_buf_64>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dwordx3            :ref:`vdst<amdgpu_synid9_dst_buf_96>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dwordx4            :ref:`vdst<amdgpu_synid9_dst_buf_128>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_hi_x    :ref:`vdst<amdgpu_synid9_dst_buf_32>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_x       :ref:`vdst<amdgpu_synid9_dst_buf_32>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_xy      :ref:`vdst<amdgpu_synid9_dst_buf_32>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_xyz     :ref:`vdst<amdgpu_synid9_dst_buf_64>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_xyzw    :ref:`vdst<amdgpu_synid9_dst_buf_64>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_x           :ref:`vdst<amdgpu_synid9_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_format_xy          :ref:`vdst<amdgpu_synid9_dst_buf_64>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_xyz         :ref:`vdst<amdgpu_synid9_dst_buf_96>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_xyzw        :ref:`vdst<amdgpu_synid9_dst_buf_128>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_sbyte              :ref:`vdst<amdgpu_synid9_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_sbyte_d16          :ref:`vdst<amdgpu_synid9_dst_buf_32>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_sbyte_d16_hi       :ref:`vdst<amdgpu_synid9_dst_buf_32>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_short_d16          :ref:`vdst<amdgpu_synid9_dst_buf_32>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_short_d16_hi       :ref:`vdst<amdgpu_synid9_dst_buf_32>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_sshort             :ref:`vdst<amdgpu_synid9_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_ubyte              :ref:`vdst<amdgpu_synid9_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_ubyte_d16          :ref:`vdst<amdgpu_synid9_dst_buf_32>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_ubyte_d16_hi       :ref:`vdst<amdgpu_synid9_dst_buf_32>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_ushort             :ref:`vdst<amdgpu_synid9_dst_buf_lds>`,     :ref:`vaddr<amdgpu_synid9_addr_buf>`,           :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`                  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_store_byte                        :ref:`vdata<amdgpu_synid9_vdata32_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_byte_d16_hi                 :ref:`vdata<amdgpu_synid9_vdata32_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dword                       :ref:`vdata<amdgpu_synid9_vdata32_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx2                     :ref:`vdata<amdgpu_synid9_vdata64_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx3                     :ref:`vdata<amdgpu_synid9_vdata96_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx4                     :ref:`vdata<amdgpu_synid9_vdata128_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_hi_x             :ref:`vdata<amdgpu_synid9_vdata32_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_x                :ref:`vdata<amdgpu_synid9_vdata32_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xy               :ref:`vdata<amdgpu_synid9_vdata32_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xyz              :ref:`vdata<amdgpu_synid9_vdata64_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xyzw             :ref:`vdata<amdgpu_synid9_vdata64_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_x                    :ref:`vdata<amdgpu_synid9_vdata32_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xy                   :ref:`vdata<amdgpu_synid9_vdata64_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyz                  :ref:`vdata<amdgpu_synid9_vdata96_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyzw                 :ref:`vdata<amdgpu_synid9_vdata128_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_lds_dword                   :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,           :ref:`soffset<amdgpu_synid9_offset_buf>`                            :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_store_short                       :ref:`vdata<amdgpu_synid9_vdata32_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_short_d16_hi                :ref:`vdata<amdgpu_synid9_vdata32_0>`,           :ref:`vaddr<amdgpu_synid9_addr_buf>`,    :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,    :ref:`soffset<amdgpu_synid9_offset_buf>`        :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_wbinvl1
+    buffer_wbinvl1_vol
+
+SMEM
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**             **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_atc_probe                              :ref:`imm3<amdgpu_synid9_perm_smem>`,            :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`
+    s_atc_probe_buffer                       :ref:`imm3<amdgpu_synid9_perm_smem>`,            :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`
+    s_atomic_add                             :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_add_x2                          :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_and                             :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_and_x2                          :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_cmpswap                         :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_cmpswap_x2                      :ref:`sdata<amdgpu_synid9_data_smem_atomic128>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_dec                             :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_dec_x2                          :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_inc                             :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_inc_x2                          :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_or                              :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_or_x2                           :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_smax                            :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_smax_x2                         :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_smin                            :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_smin_x2                         :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_sub                             :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_sub_x2                          :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_swap                            :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_swap_x2                         :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_umax                            :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_umax_x2                         :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_umin                            :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_umin_x2                         :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_xor                             :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_xor_x2                          :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_add                      :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_add_x2                   :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_and                      :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_and_x2                   :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_cmpswap                  :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_cmpswap_x2               :ref:`sdata<amdgpu_synid9_data_smem_atomic128>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_dec                      :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_dec_x2                   :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_inc                      :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_inc_x2                   :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_or                       :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_or_x2                    :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_smax                     :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_smax_x2                  :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_smin                     :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_smin_x2                  :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_sub                      :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_sub_x2                   :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_swap                     :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_swap_x2                  :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_umax                     :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_umax_x2                  :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_umin                     :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_umin_x2                  :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`,   :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_xor                      :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_xor_x2                   :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dword            :ref:`sdst<amdgpu_synid9_sdst32_0>`,     :ref:`sbase<amdgpu_synid9_base_smem_buf>`,           :ref:`soffset<amdgpu_synid9_offset_smem_buf>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx16         :ref:`sdst<amdgpu_synid9_sdst512_0>`,     :ref:`sbase<amdgpu_synid9_base_smem_buf>`,           :ref:`soffset<amdgpu_synid9_offset_smem_buf>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx2          :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`sbase<amdgpu_synid9_base_smem_buf>`,           :ref:`soffset<amdgpu_synid9_offset_smem_buf>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx4          :ref:`sdst<amdgpu_synid9_sdst128_0>`,     :ref:`sbase<amdgpu_synid9_base_smem_buf>`,           :ref:`soffset<amdgpu_synid9_offset_smem_buf>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx8          :ref:`sdst<amdgpu_synid9_sdst256_0>`,     :ref:`sbase<amdgpu_synid9_base_smem_buf>`,           :ref:`soffset<amdgpu_synid9_offset_smem_buf>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_store_dword                     :ref:`sdata<amdgpu_synid9_sdata32_0>`,           :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_store_dwordx2                   :ref:`sdata<amdgpu_synid9_sdata64_0>`,           :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_store_dwordx4                   :ref:`sdata<amdgpu_synid9_sdata128_0>`,           :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_dcache_discard                         :ref:`sbase<amdgpu_synid9_base_smem_addr>`,           :ref:`soffset<amdgpu_synid9_offset_smem_plain>`
+    s_dcache_discard_x2                      :ref:`sbase<amdgpu_synid9_base_smem_addr>`,           :ref:`soffset<amdgpu_synid9_offset_smem_plain>`
+    s_dcache_inv
+    s_dcache_inv_vol
+    s_dcache_wb
+    s_dcache_wb_vol
+    s_load_dword                   :ref:`sdst<amdgpu_synid9_sdst32_0>`,     :ref:`sbase<amdgpu_synid9_base_smem_addr>`,           :ref:`soffset<amdgpu_synid9_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx16                :ref:`sdst<amdgpu_synid9_sdst512_0>`,     :ref:`sbase<amdgpu_synid9_base_smem_addr>`,           :ref:`soffset<amdgpu_synid9_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx2                 :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`sbase<amdgpu_synid9_base_smem_addr>`,           :ref:`soffset<amdgpu_synid9_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx4                 :ref:`sdst<amdgpu_synid9_sdst128_0>`,     :ref:`sbase<amdgpu_synid9_base_smem_addr>`,           :ref:`soffset<amdgpu_synid9_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx8                 :ref:`sdst<amdgpu_synid9_sdst256_0>`,     :ref:`sbase<amdgpu_synid9_base_smem_addr>`,           :ref:`soffset<amdgpu_synid9_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_memrealtime                  :ref:`sdst<amdgpu_synid9_sdst64_0>`
+    s_memtime                      :ref:`sdst<amdgpu_synid9_sdst64_0>`
+    s_scratch_load_dword           :ref:`sdst<amdgpu_synid9_sdst32_0>`,     :ref:`sbase<amdgpu_synid9_base_smem_scratch>`,           :ref:`soffset<amdgpu_synid9_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_scratch_load_dwordx2         :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`sbase<amdgpu_synid9_base_smem_scratch>`,           :ref:`soffset<amdgpu_synid9_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_scratch_load_dwordx4         :ref:`sdst<amdgpu_synid9_sdst128_0>`,     :ref:`sbase<amdgpu_synid9_base_smem_scratch>`,           :ref:`soffset<amdgpu_synid9_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>`
+    s_scratch_store_dword                    :ref:`sdata<amdgpu_synid9_sdata32_0>`,           :ref:`sbase<amdgpu_synid9_base_smem_scratch>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_scratch_store_dwordx2                  :ref:`sdata<amdgpu_synid9_sdata64_0>`,           :ref:`sbase<amdgpu_synid9_base_smem_scratch>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_scratch_store_dwordx4                  :ref:`sdata<amdgpu_synid9_sdata128_0>`,           :ref:`sbase<amdgpu_synid9_base_smem_scratch>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_store_dword                            :ref:`sdata<amdgpu_synid9_sdata32_0>`,           :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_store_dwordx2                          :ref:`sdata<amdgpu_synid9_sdata64_0>`,           :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_store_dwordx4                          :ref:`sdata<amdgpu_synid9_sdata128_0>`,           :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+
+SOP1
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_abs_i32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_and_saveexec_b64             :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_andn1_saveexec_b64           :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_andn1_wrexec_b64             :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_andn2_saveexec_b64           :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_andn2_wrexec_b64             :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_bcnt0_i32_b32                :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_bcnt0_i32_b64                :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_bcnt1_i32_b32                :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_bcnt1_i32_b64                :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_bitreplicate_b64_b32         :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_bitset0_b32                  :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_bitset0_b64                  :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
+    s_bitset1_b32                  :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_bitset1_b64                  :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
+    s_brev_b32                     :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_brev_b64                     :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_cbranch_join                           :ref:`ssrc<amdgpu_synid9_ssrc32_1>`
+    s_cmov_b32                     :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_cmov_b64                     :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_ff0_i32_b32                  :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_ff0_i32_b64                  :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_ff1_i32_b32                  :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_ff1_i32_b64                  :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_flbit_i32                    :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_flbit_i32_b32                :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_flbit_i32_b64                :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_flbit_i32_i64                :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_getpc_b64                    :ref:`sdst<amdgpu_synid9_sdst64_1>`
+    s_mov_b32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_mov_b64                      :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_mov_fed_b32                  :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_movreld_b32                  :ref:`sdst<amdgpu_synid9_sdst32_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_movreld_b64                  :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_movrels_b32                  :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_1>`
+    s_movrels_b64                  :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_1>`
+    s_nand_saveexec_b64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_nor_saveexec_b64             :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_not_b32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_not_b64                      :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_or_saveexec_b64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_orn1_saveexec_b64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_orn2_saveexec_b64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_quadmask_b32                 :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_quadmask_b64                 :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_rfe_b64                                :ref:`ssrc<amdgpu_synid9_ssrc64_1>`
+    s_set_gpr_idx_idx                        :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_setpc_b64                              :ref:`ssrc<amdgpu_synid9_ssrc64_1>`
+    s_sext_i32_i16                 :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_sext_i32_i8                  :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_swappc_b64                   :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_1>`
+    s_wqm_b32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
+    s_wqm_b64                      :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_xnor_saveexec_b64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+    s_xor_saveexec_b64             :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+
+SOP2
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**         **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_absdiff_i32                  :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_add_i32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_add_u32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_addc_u32                     :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_and_b32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_and_b64                      :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
+    s_andn2_b32                    :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_andn2_b64                    :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
+    s_ashr_i32                     :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
+    s_ashr_i64                     :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
+    s_bfe_i32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
+    s_bfe_i64                      :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
+    s_bfe_u32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_bfe_u64                      :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
+    s_bfm_b32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_bfm_b64                      :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
+    s_cbranch_g_fork                         :ref:`ssrc0<amdgpu_synid9_ssrc64_2>`,       :ref:`ssrc1<amdgpu_synid9_ssrc64_2>`
+    s_cselect_b32                  :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_cselect_b64                  :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
+    s_lshl1_add_u32                :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_lshl2_add_u32                :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_lshl3_add_u32                :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_lshl4_add_u32                :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_lshl_b32                     :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
+    s_lshl_b64                     :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
+    s_lshr_b32                     :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
+    s_lshr_b64                     :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
+    s_max_i32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_max_u32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_min_i32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_min_u32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_mul_hi_i32                   :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_mul_hi_u32                   :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_mul_i32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_nand_b32                     :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_nand_b64                     :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
+    s_nor_b32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_nor_b64                      :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
+    s_or_b32                       :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_or_b64                       :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
+    s_orn2_b32                     :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_orn2_b64                     :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
+    s_pack_hh_b32_b16              :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`::ref:`b16x2<amdgpu_synid9_type_dev>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`b16x2<amdgpu_synid9_type_dev>`
+    s_pack_lh_b32_b16              :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`b16x2<amdgpu_synid9_type_dev>`
+    s_pack_ll_b32_b16              :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_rfe_restore_b64                        :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
+    s_sub_i32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_sub_u32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_subb_u32                     :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_xnor_b32                     :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_xnor_b64                     :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
+    s_xor_b32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_xor_b64                      :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
+
+SOPC
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **SRC0**      **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_bitcmp0_b32                  :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_bitcmp0_b64                  :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
+    s_bitcmp1_b32                  :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_bitcmp1_b64                  :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
+    s_cmp_eq_i32                   :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_cmp_eq_u32                   :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_cmp_eq_u64                   :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
+    s_cmp_ge_i32                   :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_cmp_ge_u32                   :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_cmp_gt_i32                   :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_cmp_gt_u32                   :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_cmp_le_i32                   :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_cmp_le_u32                   :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_cmp_lg_i32                   :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_cmp_lg_u32                   :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_cmp_lg_u64                   :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
+    s_cmp_lt_i32                   :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_cmp_lt_u32                   :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+    s_set_gpr_idx_on               :ref:`ssrc<amdgpu_synid9_ssrc32_0>`,     :ref:`imm4<amdgpu_synid9_imm4>`
+    s_setvskip                     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+
+SOPK
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_addk_i32                     :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`imm16<amdgpu_synid9_simm16>`
+    s_call_b64                     :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`label<amdgpu_synid9_label>`
+    s_cbranch_i_fork                         :ref:`ssrc<amdgpu_synid9_ssrc64_3>`,     :ref:`label<amdgpu_synid9_label>`
+    s_cmovk_i32                    :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`imm16<amdgpu_synid9_simm16>`
+    s_cmpk_eq_i32                            :ref:`ssrc<amdgpu_synid9_ssrc32_2>`,     :ref:`imm16<amdgpu_synid9_simm16>`
+    s_cmpk_eq_u32                            :ref:`ssrc<amdgpu_synid9_ssrc32_2>`,     :ref:`imm16<amdgpu_synid9_uimm16>`
+    s_cmpk_ge_i32                            :ref:`ssrc<amdgpu_synid9_ssrc32_2>`,     :ref:`imm16<amdgpu_synid9_simm16>`
+    s_cmpk_ge_u32                            :ref:`ssrc<amdgpu_synid9_ssrc32_2>`,     :ref:`imm16<amdgpu_synid9_uimm16>`
+    s_cmpk_gt_i32                            :ref:`ssrc<amdgpu_synid9_ssrc32_2>`,     :ref:`imm16<amdgpu_synid9_simm16>`
+    s_cmpk_gt_u32                            :ref:`ssrc<amdgpu_synid9_ssrc32_2>`,     :ref:`imm16<amdgpu_synid9_uimm16>`
+    s_cmpk_le_i32                            :ref:`ssrc<amdgpu_synid9_ssrc32_2>`,     :ref:`imm16<amdgpu_synid9_simm16>`
+    s_cmpk_le_u32                            :ref:`ssrc<amdgpu_synid9_ssrc32_2>`,     :ref:`imm16<amdgpu_synid9_uimm16>`
+    s_cmpk_lg_i32                            :ref:`ssrc<amdgpu_synid9_ssrc32_2>`,     :ref:`imm16<amdgpu_synid9_simm16>`
+    s_cmpk_lg_u32                            :ref:`ssrc<amdgpu_synid9_ssrc32_2>`,     :ref:`imm16<amdgpu_synid9_uimm16>`
+    s_cmpk_lt_i32                            :ref:`ssrc<amdgpu_synid9_ssrc32_2>`,     :ref:`imm16<amdgpu_synid9_simm16>`
+    s_cmpk_lt_u32                            :ref:`ssrc<amdgpu_synid9_ssrc32_2>`,     :ref:`imm16<amdgpu_synid9_uimm16>`
+    s_getreg_b32                   :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`hwreg<amdgpu_synid9_hwreg>`
+    s_movk_i32                     :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`imm16<amdgpu_synid9_simm16>`
+    s_mulk_i32                     :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`imm16<amdgpu_synid9_simm16>`
+    s_setreg_b32                   :ref:`hwreg<amdgpu_synid9_hwreg>`,    :ref:`ssrc<amdgpu_synid9_ssrc32_2>`
+    s_setreg_imm32_b32             :ref:`hwreg<amdgpu_synid9_hwreg>`,    :ref:`imm32<amdgpu_synid9_bimm32>`
+
+SOPP
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **SRC**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_barrier
+    s_branch                       :ref:`label<amdgpu_synid9_label>`
+    s_cbranch_cdbgsys              :ref:`label<amdgpu_synid9_label>`
+    s_cbranch_cdbgsys_and_user     :ref:`label<amdgpu_synid9_label>`
+    s_cbranch_cdbgsys_or_user      :ref:`label<amdgpu_synid9_label>`
+    s_cbranch_cdbguser             :ref:`label<amdgpu_synid9_label>`
+    s_cbranch_execnz               :ref:`label<amdgpu_synid9_label>`
+    s_cbranch_execz                :ref:`label<amdgpu_synid9_label>`
+    s_cbranch_scc0                 :ref:`label<amdgpu_synid9_label>`
+    s_cbranch_scc1                 :ref:`label<amdgpu_synid9_label>`
+    s_cbranch_vccnz                :ref:`label<amdgpu_synid9_label>`
+    s_cbranch_vccz                 :ref:`label<amdgpu_synid9_label>`
+    s_decperflevel                 :ref:`imm16<amdgpu_synid9_bimm16>`
+    s_endpgm
+    s_endpgm_ordered_ps_done
+    s_endpgm_saved
+    s_icache_inv
+    s_incperflevel                 :ref:`imm16<amdgpu_synid9_bimm16>`
+    s_nop                          :ref:`imm16<amdgpu_synid9_bimm16>`
+    s_sendmsg                      :ref:`msg<amdgpu_synid9_msg>`
+    s_sendmsghalt                  :ref:`msg<amdgpu_synid9_msg>`
+    s_set_gpr_idx_mode             :ref:`imm4<amdgpu_synid9_imm4>`
+    s_set_gpr_idx_off
+    s_sethalt                      :ref:`imm16<amdgpu_synid9_bimm16>`
+    s_setkill                      :ref:`imm16<amdgpu_synid9_bimm16>`
+    s_setprio                      :ref:`imm16<amdgpu_synid9_bimm16>`
+    s_sleep                        :ref:`imm16<amdgpu_synid9_bimm16>`
+    s_trap                         :ref:`imm16<amdgpu_synid9_bimm16>`
+    s_ttracedata
+    s_waitcnt                      :ref:`waitcnt<amdgpu_synid9_waitcnt>`
+    s_wakeup
+
+VINTRP
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**       **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_interp_mov_f32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`param<amdgpu_synid9_param>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_interp_p1_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`,      :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_interp_p2_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`,      :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`
+
+VOP1
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                     **DST**       **SRC**            **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_bfrev_b32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_bfrev_b32_dpp                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_bfrev_b32_sdwa                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ceil_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_ceil_f16_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ceil_f16_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ceil_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_ceil_f32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ceil_f32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ceil_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,     :ref:`src<amdgpu_synid9_src64_0>`
+    v_clrexcp
+    v_cos_f16                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cos_f16_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cos_f16_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cos_f32                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cos_f32_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cos_f32_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_f16_f32_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f16_f32_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_i16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_f16_i16_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f16_i16_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_u16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_f16_u16_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f16_u16_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_f16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_f32_f16_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_f16_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_f64                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src64_0>`
+    v_cvt_f32_i32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_f32_i32_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_i32_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_u32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_f32_u32_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_u32_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte0                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_f32_ubyte0_dpp            :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte0_sdwa           :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte1                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_f32_ubyte1_dpp            :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte1_sdwa           :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte2                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_f32_ubyte2_dpp            :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte2_sdwa           :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte3                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_f32_ubyte3_dpp            :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte3_sdwa           :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f64_f32                   :ref:`vdst<amdgpu_synid9_vdst64_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_f64_i32                   :ref:`vdst<amdgpu_synid9_vdst64_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_f64_u32                   :ref:`vdst<amdgpu_synid9_vdst64_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_flr_i32_f32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_flr_i32_f32_dpp           :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_flr_i32_f32_sdwa          :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_i16_f16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_i16_f16_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_i16_f16_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_i32_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_i32_f32_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_i32_f32_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_i32_f64                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src64_0>`
+    v_cvt_norm_i16_f16              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_norm_i16_f16_dpp          :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_norm_i16_f16_sdwa         :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_norm_u16_f16              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_norm_u16_f16_dpp          :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_norm_u16_f16_sdwa         :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_off_f32_i4                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_off_f32_i4_dpp            :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_off_f32_i4_sdwa           :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_rpi_i32_f32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_rpi_i32_f32_dpp           :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_rpi_i32_f32_sdwa          :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_u16_f16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_u16_f16_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_u16_f16_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_u32_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_u32_f32_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_u32_f32_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_u32_f64                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src64_0>`
+    v_exp_f16                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_exp_f16_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_exp_f16_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_exp_f32                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_exp_f32_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_exp_f32_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_exp_legacy_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_exp_legacy_f32_dpp            :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_exp_legacy_f32_sdwa           :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbh_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_ffbh_i32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ffbh_i32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbh_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_ffbh_u32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ffbh_u32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbl_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_ffbl_b32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ffbl_b32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_floor_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_floor_f16_dpp                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_floor_f16_sdwa                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_floor_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_floor_f32_dpp                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_floor_f32_sdwa                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_floor_f64                     :ref:`vdst<amdgpu_synid9_vdst64_0>`,     :ref:`src<amdgpu_synid9_src64_0>`
+    v_fract_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_fract_f16_dpp                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_fract_f16_sdwa                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_fract_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_fract_f32_dpp                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_fract_f32_sdwa                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_fract_f64                     :ref:`vdst<amdgpu_synid9_vdst64_0>`,     :ref:`src<amdgpu_synid9_src64_0>`
+    v_frexp_exp_i16_f16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_frexp_exp_i16_f16_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_exp_i16_f16_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_exp_i32_f32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_frexp_exp_i32_f32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_exp_i32_f32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_exp_i32_f64             :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src64_0>`
+    v_frexp_mant_f16                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_frexp_mant_f16_dpp            :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_mant_f16_sdwa           :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_mant_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_frexp_mant_f32_dpp            :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_mant_f32_sdwa           :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_mant_f64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,     :ref:`src<amdgpu_synid9_src64_0>`
+    v_log_f16                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_log_f16_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_log_f16_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_log_f32                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_log_f32_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_log_f32_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_log_legacy_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_log_legacy_f32_dpp            :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_log_legacy_f32_sdwa           :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_mov_b32                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_mov_b32_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mov_b32_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_mov_fed_b32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_mov_fed_b32_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mov_fed_b32_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_nop
+    v_not_b32                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_not_b32_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_not_b32_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rcp_f16                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_rcp_f16_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rcp_f16_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rcp_f32                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_rcp_f32_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rcp_f32_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rcp_f64                       :ref:`vdst<amdgpu_synid9_vdst64_0>`,     :ref:`src<amdgpu_synid9_src64_0>`
+    v_rcp_iflag_f32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_rcp_iflag_f32_dpp             :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rcp_iflag_f32_sdwa            :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_readfirstlane_b32             :ref:`sdst<amdgpu_synid9_sdst32_2>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`
+    v_rndne_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_rndne_f16_dpp                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rndne_f16_sdwa                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rndne_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_rndne_f32_dpp                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rndne_f32_sdwa                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rndne_f64                     :ref:`vdst<amdgpu_synid9_vdst64_0>`,     :ref:`src<amdgpu_synid9_src64_0>`
+    v_rsq_f16                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_rsq_f16_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rsq_f16_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rsq_f32                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_rsq_f32_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rsq_f32_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rsq_f64                       :ref:`vdst<amdgpu_synid9_vdst64_0>`,     :ref:`src<amdgpu_synid9_src64_0>`
+    v_sat_pk_u8_i16                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_sat_pk_u8_i16_dpp             :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sat_pk_u8_i16_sdwa            :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_screen_partition_4se_b32      :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_screen_partition_4se_b32_dpp  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_screen_partition_4se_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sin_f16                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_sin_f16_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sin_f16_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sin_f32                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_sin_f32_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sin_f32_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sqrt_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_sqrt_f16_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sqrt_f16_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sqrt_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_sqrt_f32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sqrt_f32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sqrt_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,     :ref:`src<amdgpu_synid9_src64_0>`
+    v_swap_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`
+    v_trunc_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_trunc_f16_dpp                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_trunc_f16_sdwa                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_trunc_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_trunc_f32_dpp                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_trunc_f32_sdwa                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_trunc_f64                     :ref:`vdst<amdgpu_synid9_vdst64_0>`,     :ref:`src<amdgpu_synid9_src64_0>`
+
+VOP2
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST0**      **DST1**      **SRC0**        **SRC1**        **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_add_co_u32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_add_co_u32_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_co_u32_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_add_f16_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_f16_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_add_f32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_f32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_u16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_add_u16_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_u16_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_add_u32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_u32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_addc_co_u32                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`
+    v_addc_co_u32_dpp              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`            :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_addc_co_u32_sdwa             :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid9_vcc_64>`            :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_and_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_and_b32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_and_b32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ashrrev_i16                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_ashrrev_i16_dpp              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ashrrev_i16_sdwa             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ashrrev_i32                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_ashrrev_i32_dpp              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ashrrev_i32_sdwa             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cndmask_b32                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`
+    v_cndmask_b32_dpp              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`            :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cndmask_b32_sdwa             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid9_vcc_64>`            :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ldexp_f16                    :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`i16<amdgpu_synid9_type_dev>`
+    v_ldexp_f16_dpp                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`i16<amdgpu_synid9_type_dev>`                  :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ldexp_f16_sdwa               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`i16<amdgpu_synid9_type_dev>`                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshlrev_b16                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_lshlrev_b16_dpp              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshlrev_b16_sdwa             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshlrev_b32                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_lshlrev_b32_dpp              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshlrev_b32_sdwa             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b16                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_lshrrev_b16_dpp              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshrrev_b16_sdwa             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b32                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_lshrrev_b32_dpp              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshrrev_b32_sdwa             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mac_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_mac_f16_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mac_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_mac_f32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_madak_f16                    :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`imm32<amdgpu_synid9_fimm16>`
+    v_madak_f32                    :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`imm32<amdgpu_synid9_fimm32>`
+    v_madmk_f16                    :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`imm32<amdgpu_synid9_fimm16>`,      :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`
+    v_madmk_f32                    :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`imm32<amdgpu_synid9_fimm32>`,      :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`
+    v_max_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_max_f16_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_f16_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_max_f32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_f32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_max_i16_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_i16_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_max_i32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_i32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_u16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_max_u16_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_u16_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_max_u32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_u32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_min_f16_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_f16_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_min_f32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_f32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_min_i16_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_i16_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_min_i32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_i32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_u16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_min_u16_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_u16_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_min_u32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_u32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_mul_f16_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_f16_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_mul_f32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_f32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_hi_i32_i24               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_mul_hi_i32_i24_dpp           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_hi_i32_i24_sdwa          :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_hi_u32_u24               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_mul_hi_u32_u24_dpp           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_hi_u32_u24_sdwa          :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_i32_i24                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_mul_i32_i24_dpp              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_i32_i24_sdwa             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_legacy_f32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_mul_legacy_f32_dpp           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_legacy_f32_sdwa          :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_lo_u16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_mul_lo_u16_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_lo_u16_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_u32_u24                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_mul_u32_u24_dpp              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_u32_u24_sdwa             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_or_b32                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_or_b32_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_or_b32_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_co_u32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_sub_co_u32_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_co_u32_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_sub_f16_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_f16_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_sub_f32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_f32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_u16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_sub_u16_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_u16_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_sub_u32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_u32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subb_co_u32                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`
+    v_subb_co_u32_dpp              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`            :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subb_co_u32_sdwa             :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid9_vcc_64>`            :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subbrev_co_u32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`
+    v_subbrev_co_u32_dpp           :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`            :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subbrev_co_u32_sdwa          :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid9_vcc_64>`            :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_co_u32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subrev_co_u32_dpp            :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_co_u32_sdwa           :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_f16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subrev_f16_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_f16_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subrev_f32_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_f32_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_u16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subrev_u16_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_u16_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_u32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subrev_u32_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_u32_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_xor_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_xor_b32_dpp                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_xor_b32_sdwa                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`                    :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+
+VOP3
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST0**       **DST1**      **SRC0**         **SRC1**        **SRC2**               **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_add3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_add_co_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_add_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`                           :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_add_lshl_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_add_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_add_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_addc_co_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
+    v_alignbit_b32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_alignbyte_b32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_and_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_and_or_b32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_ashrrev_i16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`
+    v_ashrrev_i32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`
+    v_ashrrev_i64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
+    v_bcnt_u32_b32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_bfe_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`
+    v_bfe_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_bfi_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_bfm_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_bfrev_b32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`
+    v_ceil_f16_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_ceil_f32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ceil_f64_e64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_clrexcp_e64
+    v_cmp_class_f16_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmp_class_f32_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmp_class_f64_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmp_eq_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_eq_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_eq_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_eq_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_eq_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_eq_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_f_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_i16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_f_i32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_f_i64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_f_u16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_f_u32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_f_u64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_ge_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_ge_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_ge_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_ge_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_ge_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_ge_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_gt_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_gt_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_gt_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_gt_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_gt_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_gt_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_le_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_le_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_le_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_le_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_le_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_le_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_lg_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_lt_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_lt_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_lt_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_lt_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_lt_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_ne_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_ne_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_ne_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_ne_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_ne_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_ne_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_neq_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_t_i16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_t_i32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_t_i64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_t_u16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_t_u32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_t_u64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmp_tru_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_class_f16_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmpx_class_f32_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmpx_class_f64_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmpx_eq_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_eq_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_eq_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_eq_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_eq_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_eq_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_f_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_f_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_f_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_f_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_f_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_f_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_ge_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_ge_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_ge_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_ge_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_ge_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_ge_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_gt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_gt_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_gt_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_gt_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_gt_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_gt_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_le_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_le_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_le_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_le_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_le_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_le_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_lg_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_lt_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_lt_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_lt_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_lt_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_lt_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_ne_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_ne_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_ne_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_ne_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_ne_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_ne_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_neq_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_t_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_t_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_t_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_t_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_t_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_t_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
+    v_cmpx_tru_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cndmask_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
+    v_cos_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_cos_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubeid_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubema_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubesc_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubetc_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_i16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f16_u16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_f64_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_i32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte0_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte1_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte2_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte3_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_f32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_i32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src<amdgpu_synid9_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_u32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src<amdgpu_synid9_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_flr_i32_f32_e64          :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_i16_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_i32_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_i32_f64_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_norm_i16_f16_e64         :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_norm_u16_f16_e64         :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_off_f32_i4_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`                                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_i16_i32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cvt_pk_u16_u32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cvt_pk_u8_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`
+    v_cvt_pkaccum_u8_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`
+    v_cvt_pknorm_i16_f16           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>`
+    v_cvt_pknorm_i16_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_pknorm_u16_f16           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>`
+    v_cvt_pknorm_u16_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_pkrtz_f16_f32            :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_rpi_i32_f32_e64          :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_u16_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_u32_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_u32_f64_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fixup_f16                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fixup_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_legacy_f16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fmas_f32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_scale_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_div_scale_f64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`,       :ref:`src2<amdgpu_synid9_src64_1>`
+    v_exp_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_exp_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_i32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`
+    v_ffbh_u32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`
+    v_ffbl_b32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`
+    v_floor_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_floor_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_floor_f64_e64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_legacy_f16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>`
+    v_fract_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_fract_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f64_e64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_exp_i16_f16_e64        :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_frexp_exp_i32_f32_e64        :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_frexp_exp_i32_f64_e64        :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_frexp_mant_f16_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_frexp_mant_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f64_e64           :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_mov_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`param<amdgpu_synid9_param>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1_f32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1ll_f16              :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`f32<amdgpu_synid9_type_dev>`,            :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`,  :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`                       :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1lv_f16              :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`f32<amdgpu_synid9_type_dev>`,            :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f16x2<amdgpu_synid9_type_dev>`      :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p2_f16                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`        :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_interp_p2_f32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p2_legacy_f16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`        :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_ldexp_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`i16<amdgpu_synid9_type_dev>`                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_ldexp_f32                    :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`i32<amdgpu_synid9_type_dev>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f64                    :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`i32<amdgpu_synid9_type_dev>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lerp_u8                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,            :ref:`src0<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_log_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_log_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_log_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lshl_add_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_lshl_or_b32                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_1>`
+    v_lshlrev_b16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`
+    v_lshlrev_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`
+    v_lshlrev_b64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
+    v_lshrrev_b16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`
+    v_lshrrev_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`
+    v_lshrrev_b64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
+    v_mac_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_mac_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`               :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i16                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`::ref:`i32<amdgpu_synid9_type_dev>`           :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i24                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`::ref:`i32<amdgpu_synid9_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i64_i32                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src64_1>`::ref:`i64<amdgpu_synid9_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_legacy_f16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_legacy_f32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_legacy_i16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`               :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_legacy_u16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`               :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`               :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u16                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`           :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u24                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u64_u32                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src64_1>`::ref:`u64<amdgpu_synid9_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`               :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>`
+    v_max3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_max3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`               :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>`
+    v_max3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_max_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_i16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_max_i32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_max_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_max_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_mbcnt_hi_u32_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_mbcnt_lo_u32_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_med3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_med3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`               :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>`
+    v_med3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_med3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`               :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>`
+    v_med3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_min3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`             :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`               :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>`
+    v_min3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_min3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`               :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>`
+    v_min3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_min_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_i16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_min_i32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_min_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_min_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_mov_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`
+    v_mov_fed_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`
+    v_mqsad_pk_u16_u8              :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`,            :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_mqsad_u32_u8                 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b128<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`vsrc2<amdgpu_synid9_vsrc128_0>`::ref:`b128<amdgpu_synid9_type_dev>`         :ref:`clamp<amdgpu_synid_clamp>`
+    v_msad_u8                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,            :ref:`src0<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_i32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_mul_hi_i32_i24_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_mul_hi_u32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_mul_hi_u32_u24_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_mul_i32_i24_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_mul_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_u16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_mul_lo_u32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_mul_u32_u24_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_nop_e64
+    v_not_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`
+    v_or3_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_or_b32_e64                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_pack_b32_f16                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>`
+    v_perm_b32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_qsad_pk_u16_u8               :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`,            :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_f64_e64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_iflag_f32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_readlane_b32                 :ref:`sdst<amdgpu_synid9_sdst32_2>`,                :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_3>`
+    v_rndne_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_rndne_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f64_e64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_rsq_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f64_e64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_hi_u8                    :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,            :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u8x4<amdgpu_synid9_type_dev>`,   :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u8x4<amdgpu_synid9_type_dev>`,  :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,            :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`,  :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`               :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u8                       :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,            :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u8x4<amdgpu_synid9_type_dev>`,   :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u8x4<amdgpu_synid9_type_dev>`,  :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_sat_pk_u8_i16_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`
+    v_screen_partition_4se_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`
+    v_sin_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_sin_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f16_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_sqrt_f32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f64_e64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_co_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_sub_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`                           :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_sub_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_sub_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_subb_co_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
+    v_subbrev_co_u32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
+    v_subrev_co_u32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_subrev_f16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_u16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_subrev_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_trig_preop_f64               :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>`
+    v_trunc_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f64_e64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,                :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_writelane_b32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`ssrc0<amdgpu_synid9_ssrc32_4>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_3>`
+    v_xad_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_xor_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,                :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+
+VOP3P
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**        **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_mad_mix_f32                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`,  :ref:`src2<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`        :ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_mixhi_f16                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`,  :ref:`src2<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`        :ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_mixlo_f16                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`,  :ref:`src2<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`        :ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_f16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_i16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_u16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_ashrrev_i16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_fma_f16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`,     :ref:`src2<amdgpu_synid9_src32_1>`           :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_lshlrev_b16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_lshrrev_b16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_mad_i16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`,     :ref:`src2<amdgpu_synid9_src32_1>`           :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_mad_u16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`,     :ref:`src2<amdgpu_synid9_src32_1>`           :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_max_f16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_max_i16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_max_u16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_min_f16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_min_i16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_min_u16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_mul_f16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_mul_lo_u16                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_sub_i16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_sub_u16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                     :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+
+VOPC
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**             **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_cmp_class_f16                :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmp_class_f16_sdwa           :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`b32<amdgpu_synid9_type_dev>`      :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_class_f32                :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmp_class_f32_sdwa           :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`b32<amdgpu_synid9_type_dev>`      :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_class_f64                :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmp_eq_f16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_eq_f16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_eq_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_eq_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_eq_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_eq_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_eq_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_eq_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_eq_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_f_f16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_f_f16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_f32                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_f_f32_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_f64                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_f_i16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_f_i16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_i32                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_f_i32_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_i64                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_f_u16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_f_u16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_u32                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_f_u32_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_u64                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_ge_f16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ge_f16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ge_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_ge_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ge_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ge_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_ge_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ge_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ge_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_gt_f16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_gt_f16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_gt_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_gt_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_gt_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_gt_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_gt_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_gt_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_gt_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_le_f16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_le_f16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_le_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_le_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_le_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_le_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_le_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_le_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_le_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_lg_f16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_lg_f16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lg_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_lg_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lg_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_lt_f16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_lt_f16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_lt_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_lt_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_lt_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_lt_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_lt_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_lt_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_lt_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_ne_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ne_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ne_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_ne_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ne_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ne_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_neq_f16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_neq_f16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_neq_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_neq_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_neq_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_nge_f16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_nge_f16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nge_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_nge_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nge_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_ngt_f16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ngt_f16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ngt_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ngt_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ngt_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_nle_f16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_nle_f16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nle_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_nle_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nle_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_nlg_f16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_nlg_f16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlg_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_nlg_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlg_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_nlt_f16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_nlt_f16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlt_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_nlt_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlt_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_o_f16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_o_f16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_o_f32                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_o_f32_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_o_f64                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_t_i16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_t_i16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_i32                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_t_i32_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_i64                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_t_u16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_t_u16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_u32                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_t_u32_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_u64                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_tru_f16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_tru_f16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_tru_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_tru_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_tru_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmp_u_f16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_u_f16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_u_f32                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_u_f32_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_u_f64                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_class_f16               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmpx_class_f16_sdwa          :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`b32<amdgpu_synid9_type_dev>`      :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_class_f32               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmpx_class_f32_sdwa          :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`b32<amdgpu_synid9_type_dev>`      :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_class_f64               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmpx_eq_f16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_eq_f16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_eq_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_eq_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_eq_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_i32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_eq_i32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_i64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_eq_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_eq_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_u32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_eq_u32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_u64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_f_f16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_f_f16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_f_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_f_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_f_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_f_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_f_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_f_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_f_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_ge_f16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ge_f16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ge_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_ge_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ge_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_i32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ge_i32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_i64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_ge_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ge_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_u32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ge_u32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_u64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_gt_f16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_gt_f16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_gt_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_gt_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_gt_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_i32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_gt_i32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_i64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_gt_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_gt_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_u32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_gt_u32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_u64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_le_f16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_le_f16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_le_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_le_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_le_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_i32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_le_i32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_i64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_le_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_le_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_u32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_le_u32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_u64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_lg_f16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_lg_f16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lg_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_lg_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lg_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_lt_f16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_lt_f16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_lt_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_lt_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_lt_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_i32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_lt_i32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_i64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_lt_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_lt_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_u32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_lt_u32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_u64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_ne_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ne_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_i32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ne_i32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_i64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_ne_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ne_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_u32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ne_u32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_u64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_neq_f16                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_neq_f16_sdwa            :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_neq_f32                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_neq_f32_sdwa            :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_neq_f64                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_nge_f16                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_nge_f16_sdwa            :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nge_f32                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_nge_f32_sdwa            :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nge_f64                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_ngt_f16                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ngt_f16_sdwa            :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ngt_f32                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ngt_f32_sdwa            :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ngt_f64                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_nle_f16                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_nle_f16_sdwa            :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nle_f32                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_nle_f32_sdwa            :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nle_f64                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_nlg_f16                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_nlg_f16_sdwa            :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlg_f32                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_nlg_f32_sdwa            :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlg_f64                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_nlt_f16                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_nlt_f16_sdwa            :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlt_f32                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_nlt_f32_sdwa            :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlt_f64                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_o_f16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_o_f16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_o_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_o_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_o_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_t_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_t_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_t_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_t_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_t_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_t_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_tru_f16                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_tru_f16_sdwa            :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_tru_f32                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_tru_f32_sdwa            :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_tru_f64                 :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+    v_cmpx_u_f16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_u_f16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_u_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_u_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_u_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+
+.. |---| unicode:: U+02014 .. em dash
+
+
+.. toctree::
+    :hidden:
+
+    gfx9_attr
+    gfx9_bimm16
+    gfx9_bimm32
+    gfx9_fimm16
+    gfx9_fimm32
+    gfx9_hwreg
+    gfx9_imm4
+    gfx9_label
+    gfx9_msg
+    gfx9_param
+    gfx9_perm_smem
+    gfx9_simm16
+    gfx9_tgt
+    gfx9_uimm16
+    gfx9_waitcnt
+    gfx9_addr_buf
+    gfx9_addr_ds
+    gfx9_addr_flat
+    gfx9_addr_mimg
+    gfx9_base_smem_addr
+    gfx9_base_smem_buf
+    gfx9_base_smem_scratch
+    gfx9_data_buf_atomic128
+    gfx9_data_buf_atomic32
+    gfx9_data_buf_atomic64
+    gfx9_data_mimg_atomic_cmp
+    gfx9_data_mimg_atomic_reg
+    gfx9_data_mimg_store
+    gfx9_data_mimg_store_d16
+    gfx9_data_smem_atomic128
+    gfx9_data_smem_atomic32
+    gfx9_data_smem_atomic64
+    gfx9_dst_buf_128
+    gfx9_dst_buf_32
+    gfx9_dst_buf_64
+    gfx9_dst_buf_96
+    gfx9_dst_buf_lds
+    gfx9_dst_flat_atomic32
+    gfx9_dst_flat_atomic64
+    gfx9_dst_mimg_gather4
+    gfx9_dst_mimg_regular
+    gfx9_dst_mimg_regular_d16
+    gfx9_offset_buf
+    gfx9_offset_smem_buf
+    gfx9_offset_smem_plain
+    gfx9_rsrc_buf
+    gfx9_rsrc_mimg
+    gfx9_saddr_flat_global
+    gfx9_saddr_flat_scratch
+    gfx9_samp_mimg
+    gfx9_sdata128_0
+    gfx9_sdata32_0
+    gfx9_sdata64_0
+    gfx9_sdst128_0
+    gfx9_sdst256_0
+    gfx9_sdst32_0
+    gfx9_sdst32_1
+    gfx9_sdst32_2
+    gfx9_sdst512_0
+    gfx9_sdst64_0
+    gfx9_sdst64_1
+    gfx9_src32_0
+    gfx9_src32_1
+    gfx9_src64_0
+    gfx9_src64_1
+    gfx9_src_exp
+    gfx9_ssrc32_0
+    gfx9_ssrc32_1
+    gfx9_ssrc32_2
+    gfx9_ssrc32_3
+    gfx9_ssrc32_4
+    gfx9_ssrc64_0
+    gfx9_ssrc64_1
+    gfx9_ssrc64_2
+    gfx9_ssrc64_3
+    gfx9_vaddr_flat_global
+    gfx9_vaddr_flat_scratch
+    gfx9_vcc_64
+    gfx9_vdata128_0
+    gfx9_vdata32_0
+    gfx9_vdata64_0
+    gfx9_vdata96_0
+    gfx9_vdst128_0
+    gfx9_vdst32_0
+    gfx9_vdst64_0
+    gfx9_vdst96_0
+    gfx9_vsrc128_0
+    gfx9_vsrc32_0
+    gfx9_vsrc64_0
+    gfx9_mad_type_dev
+    gfx9_mod_dpp_sdwa_abs_neg
+    gfx9_mod_sdwa_sext
+    gfx9_mod_vop3_abs_neg
+    gfx9_opt
+    gfx9_ret
+    gfx9_type_dev

diff --git a/docs/AMDGPU/gfx7_addr_buf.rst b/docs/AMDGPU/gfx7_addr_buf.rst
new file mode 100644 (file)
index 0000000..22dc7d3
--- /dev/null
+++ b/docs/AMDGPU/gfx7_addr_buf.rst
@@ -0,0 +1,24 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_addr_buf:
+
+vaddr
+===========================
+
+This is an optional operand which may specify a 64-bit address, offset and/or index.
+
+*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`addr64<amdgpu_synid_addr64>`, :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
+
+* If only :ref:`addr64<amdgpu_synid_addr64>` is specified, this operand supplies a 64-bit address. Size is 2 dwords.
+* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
+* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
+* If both :ref:`idxen<amdgpu_synid_idxen>` and :ref:`offen<amdgpu_synid_offen>` are specified, index is in the first register and offset is in the second. Size is 2 dwords.
+* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
+* All other combinations of these modifiers are illegal.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`

diff --git a/docs/AMDGPU/gfx7_addr_ds.rst b/docs/AMDGPU/gfx7_addr_ds.rst
new file mode 100644 (file)
index 0000000..c9cab7d
--- /dev/null
+++ b/docs/AMDGPU/gfx7_addr_ds.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_addr_ds:
+
+vaddr
+===========================
+
+An offset from the start of GDS/LDS memory.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_addr_flat.rst b/docs/AMDGPU/gfx7_addr_flat.rst
new file mode 100644 (file)
index 0000000..93deea6
--- /dev/null
+++ b/docs/AMDGPU/gfx7_addr_flat.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_addr_flat:
+
+vaddr
+===========================
+
+A 64-bit flat address.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_addr_mimg.rst b/docs/AMDGPU/gfx7_addr_mimg.rst
new file mode 100644 (file)
index 0000000..76eb484
--- /dev/null
+++ b/docs/AMDGPU/gfx7_addr_mimg.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_addr_mimg:
+
+vaddr
+===========================
+
+Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
+
+*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode and specific image being handled.
+
+    Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
+
+    Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_attr.rst b/docs/AMDGPU/gfx7_attr.rst
new file mode 100644 (file)
index 0000000..13096f2
--- /dev/null
+++ b/docs/AMDGPU/gfx7_attr.rst
@@ -0,0 +1,30 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_attr:
+
+attr
+===========================
+
+Interpolation attribute and channel:
+
+    ============== ===================================
+    Syntax         Description
+    ============== ===================================
+    attr{0..32}.x  Attribute 0..32 with *x* channel.
+    attr{0..32}.y  Attribute 0..32 with *y* channel.
+    attr{0..32}.z  Attribute 0..32 with *z* channel.
+    attr{0..32}.w  Attribute 0..32 with *w* channel.
+    ============== ===================================
+
+Examples:
+
+.. code-block:: nasm
+
+    v_interp_p1_f32 v1, v0, attr0.x
+    v_interp_p1_f32 v1, v0, attr32.w
+

diff --git a/docs/AMDGPU/gfx7_base_smem_addr.rst b/docs/AMDGPU/gfx7_base_smem_addr.rst
new file mode 100644 (file)
index 0000000..9cc3cc7
--- /dev/null
+++ b/docs/AMDGPU/gfx7_base_smem_addr.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_base_smem_addr:
+
+sbase
+===========================
+
+A 64-bit base address for scalar memory operations.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

diff --git a/docs/AMDGPU/gfx7_base_smem_buf.rst b/docs/AMDGPU/gfx7_base_smem_buf.rst
new file mode 100644 (file)
index 0000000..416cac7
--- /dev/null
+++ b/docs/AMDGPU/gfx7_base_smem_buf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_base_smem_buf:
+
+sbase
+===========================
+
+A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx7_bimm16.rst b/docs/AMDGPU/gfx7_bimm16.rst
new file mode 100644 (file)
index 0000000..eb43f9b
--- /dev/null
+++ b/docs/AMDGPU/gfx7_bimm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_bimm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits.
+

diff --git a/docs/AMDGPU/gfx7_bimm32.rst b/docs/AMDGPU/gfx7_bimm32.rst
new file mode 100644 (file)
index 0000000..4d8f89d
--- /dev/null
+++ b/docs/AMDGPU/gfx7_bimm32.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_bimm32:
+
+imm32
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits.
+

diff --git a/docs/AMDGPU/gfx7_data_buf_atomic128.rst b/docs/AMDGPU/gfx7_data_buf_atomic128.rst
new file mode 100644 (file)
index 0000000..33ff26c
--- /dev/null
+++ b/docs/AMDGPU/gfx7_data_buf_atomic128.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_data_buf_atomic128:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_data_buf_atomic32.rst b/docs/AMDGPU/gfx7_data_buf_atomic32.rst
new file mode 100644 (file)
index 0000000..df4a6e4
--- /dev/null
+++ b/docs/AMDGPU/gfx7_data_buf_atomic32.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_data_buf_atomic32:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_data_buf_atomic64.rst b/docs/AMDGPU/gfx7_data_buf_atomic64.rst
new file mode 100644 (file)
index 0000000..4892e41
--- /dev/null
+++ b/docs/AMDGPU/gfx7_data_buf_atomic64.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_data_buf_atomic64:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst b/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst
new file mode 100644 (file)
index 0000000..82c3337
--- /dev/null
+++ b/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst
@@ -0,0 +1,27 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_data_mimg_atomic_cmp:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+  Note. The surface data format is indicated in the image resource constant but not in the instruction.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst b/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst
new file mode 100644 (file)
index 0000000..729548d
--- /dev/null
+++ b/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst
@@ -0,0 +1,26 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_data_mimg_atomic_reg:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+  Note. The surface data format is indicated in the image resource constant but not in the instruction.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_data_mimg_store.rst b/docs/AMDGPU/gfx7_data_mimg_store.rst
new file mode 100644 (file)
index 0000000..1858547
--- /dev/null
+++ b/docs/AMDGPU/gfx7_data_mimg_store.rst
@@ -0,0 +1,18 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_data_mimg_store:
+
+vdata
+===========================
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` which may specify from 1 to 4 data elements. Each data element occupies 1 dword.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_dst_buf_128.rst b/docs/AMDGPU/gfx7_dst_buf_128.rst
new file mode 100644 (file)
index 0000000..701616e
--- /dev/null
+++ b/docs/AMDGPU/gfx7_dst_buf_128.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_dst_buf_128:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_dst_buf_64.rst b/docs/AMDGPU/gfx7_dst_buf_64.rst
new file mode 100644 (file)
index 0000000..de62a56
--- /dev/null
+++ b/docs/AMDGPU/gfx7_dst_buf_64.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_dst_buf_64:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_dst_buf_96.rst b/docs/AMDGPU/gfx7_dst_buf_96.rst
new file mode 100644 (file)
index 0000000..1abfcc0
--- /dev/null
+++ b/docs/AMDGPU/gfx7_dst_buf_96.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_dst_buf_96:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_dst_buf_lds.rst b/docs/AMDGPU/gfx7_dst_buf_lds.rst
new file mode 100644 (file)
index 0000000..435f6bb
--- /dev/null
+++ b/docs/AMDGPU/gfx7_dst_buf_lds.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_dst_buf_lds:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+If :ref:`lds<amdgpu_synid_lds>` is specified, this operand is ignored by H/W and data are stored directly into LDS.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+    Note that :ref:`tfe<amdgpu_synid_tfe>` and :ref:`lds<amdgpu_synid_lds>` cannot be used together.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_dst_flat_atomic32.rst b/docs/AMDGPU/gfx7_dst_flat_atomic32.rst
new file mode 100644 (file)
index 0000000..4a85656
--- /dev/null
+++ b/docs/AMDGPU/gfx7_dst_flat_atomic32.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_dst_flat_atomic32:
+
+vdst
+===========================
+
+Data returned by a 32-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_dst_flat_atomic64.rst b/docs/AMDGPU/gfx7_dst_flat_atomic64.rst
new file mode 100644 (file)
index 0000000..cb1fddd
--- /dev/null
+++ b/docs/AMDGPU/gfx7_dst_flat_atomic64.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_dst_flat_atomic64:
+
+vdst
+===========================
+
+Data returned by a 64-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_dst_mimg_gather4.rst b/docs/AMDGPU/gfx7_dst_mimg_gather4.rst
new file mode 100644 (file)
index 0000000..17fcff5
--- /dev/null
+++ b/docs/AMDGPU/gfx7_dst_mimg_gather4.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_dst_mimg_gather4:
+
+vdst
+===========================
+
+Image data to load by an *image_gather4* instruction.
+
+*Size:* 4 data elements by default. Each data element occupies 1 dword. :ref:`tfe<amdgpu_synid_tfe>` adds one more dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_dst_mimg_regular.rst b/docs/AMDGPU/gfx7_dst_mimg_regular.rst
new file mode 100644 (file)
index 0000000..aa165b8
--- /dev/null
+++ b/docs/AMDGPU/gfx7_dst_mimg_regular.rst
@@ -0,0 +1,20 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_dst_mimg_regular:
+
+vdst
+===========================
+
+Image data to load by an image instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_fimm32.rst b/docs/AMDGPU/gfx7_fimm32.rst
new file mode 100644 (file)
index 0000000..70c8189
--- /dev/null
+++ b/docs/AMDGPU/gfx7_fimm32.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_fimm32:
+
+imm32
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The value is converted to *f32* as described :ref:`here<amdgpu_synid_lit_conv>`.
+

diff --git a/docs/AMDGPU/gfx7_hwreg.rst b/docs/AMDGPU/gfx7_hwreg.rst
new file mode 100644 (file)
index 0000000..1b0c542
--- /dev/null
+++ b/docs/AMDGPU/gfx7_hwreg.rst
@@ -0,0 +1,60 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_hwreg:
+
+hwreg
+===========================
+
+Bits of a hardware register being accessed.
+
+The bits of this operand have the following meaning:
+
+    ============ ===================================
+    Bits         Description
+    ============ ===================================
+    5:0          Register *id*.
+    10:6         First bit *offset* (0..31).
+    15:11        *Size* in bits (1..32).
+    ============ ===================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below.
+
+    ==================================== ============================================================================
+    Syntax                               Description
+    ==================================== ============================================================================
+    hwreg({0..63})                       All bits of a register indicated by its *id*.
+    hwreg(<*name*>)                      All bits of a register indicated by its *name*.
+    hwreg({0..63}, {0..31}, {1..32})     Register bits indicated by register *id*, first bit *offset* and *size*.
+    hwreg(<*name*>, {0..31}, {1..32})    Register bits indicated by register *name*, first bit *offset* and *size*.
+    ==================================== ============================================================================
+
+Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
+
+Defined register *names* include:
+
+    =================== ==========================================
+    Name                Description
+    =================== ==========================================
+    HW_REG_MODE         Shader writeable mode bits.
+    HW_REG_STATUS       Shader read-only status.
+    HW_REG_TRAPSTS      Trap status.
+    HW_REG_HW_ID        Id of wave, simd, compute unit, etc.
+    HW_REG_GPR_ALLOC    Per-wave SGPR and VGPR allocation.
+    HW_REG_LDS_ALLOC    Per-wave LDS allocation.
+    HW_REG_IB_STS       Counters of outstanding instructions.
+    =================== ==========================================
+
+Examples:
+
+.. code-block:: nasm
+
+    s_getreg_b32 s2, 0x6
+    s_getreg_b32 s2, hwreg(15)
+    s_getreg_b32 s2, hwreg(51, 1, 31)
+    s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
+

diff --git a/docs/AMDGPU/gfx7_label.rst b/docs/AMDGPU/gfx7_label.rst
new file mode 100644 (file)
index 0000000..e0153e7
--- /dev/null
+++ b/docs/AMDGPU/gfx7_label.rst
@@ -0,0 +1,30 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_label:
+
+label
+===========================
+
+A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
+
+This operand may be specified as:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>`. The number is truncated to 16 bits.
+* An :ref:`absolute_expression<amdgpu_synid_absolute_expression>` which must start with an :ref:`integer_number<amdgpu_synid_integer_number>`. The value of the expression is truncated to 16 bits.
+* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
+
+Examples:
+
+.. code-block:: nasm
+
+  offset = 30
+  s_branch loop_end
+  s_branch 2 + offset
+  s_branch 32
+  loop_end:
+

diff --git a/docs/AMDGPU/gfx7_mod.rst b/docs/AMDGPU/gfx7_mod.rst
new file mode 100644 (file)
index 0000000..fcaa6ca
--- /dev/null
+++ b/docs/AMDGPU/gfx7_mod.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_mod:
+
+m
+===========================
+
+This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
+

diff --git a/docs/AMDGPU/gfx7_msg.rst b/docs/AMDGPU/gfx7_msg.rst
new file mode 100644 (file)
index 0000000..ad5fd7f
--- /dev/null
+++ b/docs/AMDGPU/gfx7_msg.rst
@@ -0,0 +1,72 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_msg:
+
+msg
+===========================
+
+A 16-bit message code. The bits of this operand have the following meaning:
+
+    ============ ======================================================
+    Bits         Description
+    ============ ======================================================
+    3:0          Message *type*.
+    6:4          Optional *operation*.
+    9:7          Optional *parameters*.
+    15:10        Unused.
+    ============ ======================================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below:
+
+    ======================================== ========================================================================
+    Syntax                                   Description
+    ======================================== ========================================================================
+    sendmsg(<*type*>)                        A message identified by its *type*.
+    sendmsg(<*type*>, <*op*>)                A message identified by its *type* and *operation*.
+    sendmsg(<*type*>, <*op*>, <*stream*>)    A message identified by its *type* and *operation* with a stream *id*.
+    ======================================== ========================================================================
+
+*Type* may be specified using message *name* or message *id*.
+
+*Op* may be specified using operation *name* or operation *id*.
+
+Stream *id* is an integer in the range 0..3.
+
+Message *id*, operation *id* and stream *id* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
+
+Each message type supports specific operations:
+
+    ================= ========== ============================== ============ ==========
+    Message name      Message Id Supported Operations           Operation Id Stream Id
+    ================= ========== ============================== ============ ==========
+    MSG_INTERRUPT     1          \-                             \-           \-
+    MSG_GS            2          GS_OP_CUT                      1            Optional
+    \                            GS_OP_EMIT                     2            Optional
+    \                            GS_OP_EMIT_CUT                 3            Optional
+    MSG_GS_DONE       3          GS_OP_NOP                      0            \-
+    \                            GS_OP_CUT                      1            Optional
+    \                            GS_OP_EMIT                     2            Optional
+    \                            GS_OP_EMIT_CUT                 3            Optional
+    MSG_SYSMSG        15         SYSMSG_OP_ECC_ERR_INTERRUPT    1            \-
+    \                            SYSMSG_OP_REG_RD               2            \-
+    \                            SYSMSG_OP_HOST_TRAP_ACK        3            \-
+    \                            SYSMSG_OP_TTRACE_PC            4            \-
+    ================= ========== ============================== ============ ==========
+
+Examples:
+
+.. code-block:: nasm
+
+    s_sendmsg 0x12
+    s_sendmsg sendmsg(MSG_INTERRUPT)
+    s_sendmsg sendmsg(2, GS_OP_CUT)
+    s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
+    s_sendmsg sendmsg(MSG_GS, 2)
+    s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
+    s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)
+

diff --git a/docs/AMDGPU/gfx7_offset_buf.rst b/docs/AMDGPU/gfx7_offset_buf.rst
new file mode 100644 (file)
index 0000000..c36df06
--- /dev/null
+++ b/docs/AMDGPU/gfx7_offset_buf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_offset_buf:
+
+soffset
+===========================
+
+An unsigned byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

diff --git a/docs/AMDGPU/gfx7_offset_smem.rst b/docs/AMDGPU/gfx7_offset_smem.rst
new file mode 100644 (file)
index 0000000..85ed5f1
--- /dev/null
+++ b/docs/AMDGPU/gfx7_offset_smem.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_offset_smem:
+
+soffset
+===========================
+
+An unsigned offset added to the base address to get memory address.
+
+* If offset is specified as a register, it supplies an unsigned byte offset but 2 lsb's are ignored.
+* If offset is specified as an :ref:`uimm32<amdgpu_synid_uimm32>`, it supplies a 32-bit unsigned byte offset but 2 lsb's are ignored.
+* If offset is specified as an :ref:`uimm8<amdgpu_synid_uimm8>`, it supplies an 8-bit unsigned dword offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`uimm8<amdgpu_synid_uimm8>`, :ref:`uimm32<amdgpu_synid_uimm32>`

diff --git a/docs/AMDGPU/gfx7_opt.rst b/docs/AMDGPU/gfx7_opt.rst
new file mode 100644 (file)
index 0000000..1a48733
--- /dev/null
+++ b/docs/AMDGPU/gfx7_opt.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_opt:
+
+opt
+===========================
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+

diff --git a/docs/AMDGPU/gfx7_param.rst b/docs/AMDGPU/gfx7_param.rst
new file mode 100644 (file)
index 0000000..13e533b
--- /dev/null
+++ b/docs/AMDGPU/gfx7_param.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_param:
+
+param
+===========================
+
+Interpolation parameter to read:
+
+    ============ ===================================
+    Syntax       Description
+    ============ ===================================
+    p0           Parameter *P0*.
+    p10          Parameter *P10*.
+    p20          Parameter *P20*.
+    ============ ===================================
+

diff --git a/docs/AMDGPU/gfx7_ret.rst b/docs/AMDGPU/gfx7_ret.rst
new file mode 100644 (file)
index 0000000..25301c2
--- /dev/null
+++ b/docs/AMDGPU/gfx7_ret.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_ret:
+
+dst
+===========================
+
+This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
+

diff --git a/docs/AMDGPU/gfx7_rsrc_buf.rst b/docs/AMDGPU/gfx7_rsrc_buf.rst
new file mode 100644 (file)
index 0000000..7ebcebc
--- /dev/null
+++ b/docs/AMDGPU/gfx7_rsrc_buf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_rsrc_buf:
+
+srsrc
+===========================
+
+Buffer resource constant which defines the address and characteristics of the buffer in memory.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx7_rsrc_mimg.rst b/docs/AMDGPU/gfx7_rsrc_mimg.rst
new file mode 100644 (file)
index 0000000..b0e40fe
--- /dev/null
+++ b/docs/AMDGPU/gfx7_rsrc_mimg.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_rsrc_mimg:
+
+srsrc
+===========================
+
+Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
+
+*Size:* 8 dwords by default, 4 dwords if :ref:`r128<amdgpu_synid_r128>` is specified.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx7_samp_mimg.rst b/docs/AMDGPU/gfx7_samp_mimg.rst
new file mode 100644 (file)
index 0000000..738cad4
--- /dev/null
+++ b/docs/AMDGPU/gfx7_samp_mimg.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_samp_mimg:
+
+ssamp
+===========================
+
+Sampler constant used to specify filtering options applied to the image data after it is read.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx7_sdst128_0.rst b/docs/AMDGPU/gfx7_sdst128_0.rst
new file mode 100644 (file)
index 0000000..735a30c
--- /dev/null
+++ b/docs/AMDGPU/gfx7_sdst128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_sdst128_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx7_sdst256_0.rst b/docs/AMDGPU/gfx7_sdst256_0.rst
new file mode 100644 (file)
index 0000000..c4e6f9f
--- /dev/null
+++ b/docs/AMDGPU/gfx7_sdst256_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_sdst256_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx7_sdst32_0.rst b/docs/AMDGPU/gfx7_sdst32_0.rst
new file mode 100644 (file)
index 0000000..183d89f
--- /dev/null
+++ b/docs/AMDGPU/gfx7_sdst32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_sdst32_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

diff --git a/docs/AMDGPU/gfx7_sdst32_1.rst b/docs/AMDGPU/gfx7_sdst32_1.rst
new file mode 100644 (file)
index 0000000..2e49e20
--- /dev/null
+++ b/docs/AMDGPU/gfx7_sdst32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_sdst32_1:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`

diff --git a/docs/AMDGPU/gfx7_sdst32_2.rst b/docs/AMDGPU/gfx7_sdst32_2.rst
new file mode 100644 (file)
index 0000000..8212e5d
--- /dev/null
+++ b/docs/AMDGPU/gfx7_sdst32_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_sdst32_2:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`trap<amdgpu_synid_trap>`

diff --git a/docs/AMDGPU/gfx7_sdst512_0.rst b/docs/AMDGPU/gfx7_sdst512_0.rst
new file mode 100644 (file)
index 0000000..d8c64b1
--- /dev/null
+++ b/docs/AMDGPU/gfx7_sdst512_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_sdst512_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`

diff --git a/docs/AMDGPU/gfx7_sdst64_0.rst b/docs/AMDGPU/gfx7_sdst64_0.rst
new file mode 100644 (file)
index 0000000..af60880
--- /dev/null
+++ b/docs/AMDGPU/gfx7_sdst64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_sdst64_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

diff --git a/docs/AMDGPU/gfx7_sdst64_1.rst b/docs/AMDGPU/gfx7_sdst64_1.rst
new file mode 100644 (file)
index 0000000..207df73
--- /dev/null
+++ b/docs/AMDGPU/gfx7_sdst64_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_sdst64_1:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`

diff --git a/docs/AMDGPU/gfx7_simm16.rst b/docs/AMDGPU/gfx7_simm16.rst
new file mode 100644 (file)
index 0000000..66e560e
--- /dev/null
+++ b/docs/AMDGPU/gfx7_simm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_simm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then sign-extended to 32 bits.
+

diff --git a/docs/AMDGPU/gfx7_src32_0.rst b/docs/AMDGPU/gfx7_src32_0.rst
new file mode 100644 (file)
index 0000000..22ff73d
--- /dev/null
+++ b/docs/AMDGPU/gfx7_src32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_src32_0:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

diff --git a/docs/AMDGPU/gfx7_src32_1.rst b/docs/AMDGPU/gfx7_src32_1.rst
new file mode 100644 (file)
index 0000000..0059459
--- /dev/null
+++ b/docs/AMDGPU/gfx7_src32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_src32_1:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`iconst<amdgpu_synid_iconst>`

diff --git a/docs/AMDGPU/gfx7_src32_2.rst b/docs/AMDGPU/gfx7_src32_2.rst
new file mode 100644 (file)
index 0000000..b939c45
--- /dev/null
+++ b/docs/AMDGPU/gfx7_src32_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_src32_2:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

diff --git a/docs/AMDGPU/gfx7_src32_3.rst b/docs/AMDGPU/gfx7_src32_3.rst
new file mode 100644 (file)
index 0000000..83aa9ca
--- /dev/null
+++ b/docs/AMDGPU/gfx7_src32_3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_src32_3:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`

diff --git a/docs/AMDGPU/gfx7_src64_0.rst b/docs/AMDGPU/gfx7_src64_0.rst
new file mode 100644 (file)
index 0000000..a19b6ee
--- /dev/null
+++ b/docs/AMDGPU/gfx7_src64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_src64_0:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

diff --git a/docs/AMDGPU/gfx7_src64_1.rst b/docs/AMDGPU/gfx7_src64_1.rst
new file mode 100644 (file)
index 0000000..c81864c
--- /dev/null
+++ b/docs/AMDGPU/gfx7_src64_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_src64_1:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

diff --git a/docs/AMDGPU/gfx7_src64_2.rst b/docs/AMDGPU/gfx7_src64_2.rst
new file mode 100644 (file)
index 0000000..189245e
--- /dev/null
+++ b/docs/AMDGPU/gfx7_src64_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_src64_2:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`iconst<amdgpu_synid_iconst>`

diff --git a/docs/AMDGPU/gfx7_src_exp.rst b/docs/AMDGPU/gfx7_src_exp.rst
new file mode 100644 (file)
index 0000000..6d155a5
--- /dev/null
+++ b/docs/AMDGPU/gfx7_src_exp.rst
@@ -0,0 +1,28 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_src_exp:
+
+vsrc
+===========================
+
+Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+:ref:`compr<amdgpu_synid_compr>` modifier indicates use of compressed (16-bit) data. This limits number of source operands from 4 to 2:
+
+* src0 and src1 must specify the first register (or :ref:`off<amdgpu_synid_off>`).
+* src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
+
+An example:
+
+.. code-block:: nasm
+
+  exp mrtz v3, v3, off, off compr
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`

diff --git a/docs/AMDGPU/gfx7_ssrc32_0.rst b/docs/AMDGPU/gfx7_ssrc32_0.rst
new file mode 100644 (file)
index 0000000..843db24
--- /dev/null
+++ b/docs/AMDGPU/gfx7_ssrc32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_ssrc32_0:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

diff --git a/docs/AMDGPU/gfx7_ssrc32_1.rst b/docs/AMDGPU/gfx7_ssrc32_1.rst
new file mode 100644 (file)
index 0000000..6e626d8
--- /dev/null
+++ b/docs/AMDGPU/gfx7_ssrc32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_ssrc32_1:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`

diff --git a/docs/AMDGPU/gfx7_ssrc32_2.rst b/docs/AMDGPU/gfx7_ssrc32_2.rst
new file mode 100644 (file)
index 0000000..c7ff032
--- /dev/null
+++ b/docs/AMDGPU/gfx7_ssrc32_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_ssrc32_2:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

diff --git a/docs/AMDGPU/gfx7_ssrc32_3.rst b/docs/AMDGPU/gfx7_ssrc32_3.rst
new file mode 100644 (file)
index 0000000..68a2415
--- /dev/null
+++ b/docs/AMDGPU/gfx7_ssrc32_3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_ssrc32_3:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`

diff --git a/docs/AMDGPU/gfx7_ssrc32_4.rst b/docs/AMDGPU/gfx7_ssrc32_4.rst
new file mode 100644 (file)
index 0000000..669ae4e
--- /dev/null
+++ b/docs/AMDGPU/gfx7_ssrc32_4.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_ssrc32_4:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`

diff --git a/docs/AMDGPU/gfx7_ssrc64_0.rst b/docs/AMDGPU/gfx7_ssrc64_0.rst
new file mode 100644 (file)
index 0000000..283e7ea
--- /dev/null
+++ b/docs/AMDGPU/gfx7_ssrc64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_ssrc64_0:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

diff --git a/docs/AMDGPU/gfx7_ssrc64_1.rst b/docs/AMDGPU/gfx7_ssrc64_1.rst
new file mode 100644 (file)
index 0000000..42dc8c5
--- /dev/null
+++ b/docs/AMDGPU/gfx7_ssrc64_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_ssrc64_1:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

diff --git a/docs/AMDGPU/gfx7_ssrc64_2.rst b/docs/AMDGPU/gfx7_ssrc64_2.rst
new file mode 100644 (file)
index 0000000..344147f
--- /dev/null
+++ b/docs/AMDGPU/gfx7_ssrc64_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_ssrc64_2:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

diff --git a/docs/AMDGPU/gfx7_ssrc64_3.rst b/docs/AMDGPU/gfx7_ssrc64_3.rst
new file mode 100644 (file)
index 0000000..173f550
--- /dev/null
+++ b/docs/AMDGPU/gfx7_ssrc64_3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_ssrc64_3:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`

diff --git a/docs/AMDGPU/gfx7_tgt.rst b/docs/AMDGPU/gfx7_tgt.rst
new file mode 100644 (file)
index 0000000..c407c0c
--- /dev/null
+++ b/docs/AMDGPU/gfx7_tgt.rst
@@ -0,0 +1,24 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_tgt:
+
+tgt
+===========================
+
+An export target:
+
+    ============== ===================================
+    Syntax         Description
+    ============== ===================================
+    pos{0..3}      Copy vertex position 0..3.
+    param{0..31}   Copy vertex parameter 0..31.
+    mrt{0..7}      Copy pixel color to the MRTs 0..7.
+    mrtz           Copy pixel depth (Z) data.
+    null           Copy nothing.
+    ============== ===================================
+

diff --git a/docs/AMDGPU/gfx7_type_dev.rst b/docs/AMDGPU/gfx7_type_dev.rst
new file mode 100644 (file)
index 0000000..6eab0e1
--- /dev/null
+++ b/docs/AMDGPU/gfx7_type_dev.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_type_dev:
+
+Type deviation
+===========================
+
+*Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.
+

diff --git a/docs/AMDGPU/gfx7_uimm16.rst b/docs/AMDGPU/gfx7_uimm16.rst
new file mode 100644 (file)
index 0000000..bd0d4c2
--- /dev/null
+++ b/docs/AMDGPU/gfx7_uimm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_uimm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then zero-extended to 32 bits.
+

diff --git a/docs/AMDGPU/gfx7_vcc_64.rst b/docs/AMDGPU/gfx7_vcc_64.rst
new file mode 100644 (file)
index 0000000..b1285e0
--- /dev/null
+++ b/docs/AMDGPU/gfx7_vcc_64.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_vcc_64:
+
+vcc
+===========================
+
+Vector condition code.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`vcc<amdgpu_synid_vcc>`

diff --git a/docs/AMDGPU/gfx7_vdata128_0.rst b/docs/AMDGPU/gfx7_vdata128_0.rst
new file mode 100644 (file)
index 0000000..5ed2b82
--- /dev/null
+++ b/docs/AMDGPU/gfx7_vdata128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_vdata128_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_vdata32_0.rst b/docs/AMDGPU/gfx7_vdata32_0.rst
new file mode 100644 (file)
index 0000000..1615abb
--- /dev/null
+++ b/docs/AMDGPU/gfx7_vdata32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_vdata32_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_vdata64_0.rst b/docs/AMDGPU/gfx7_vdata64_0.rst
new file mode 100644 (file)
index 0000000..fceea9f
--- /dev/null
+++ b/docs/AMDGPU/gfx7_vdata64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_vdata64_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_vdata96_0.rst b/docs/AMDGPU/gfx7_vdata96_0.rst
new file mode 100644 (file)
index 0000000..b9fe599
--- /dev/null
+++ b/docs/AMDGPU/gfx7_vdata96_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_vdata96_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_vdst128_0.rst b/docs/AMDGPU/gfx7_vdst128_0.rst
new file mode 100644 (file)
index 0000000..c18652e
--- /dev/null
+++ b/docs/AMDGPU/gfx7_vdst128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_vdst128_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_vdst32_0.rst b/docs/AMDGPU/gfx7_vdst32_0.rst
new file mode 100644 (file)
index 0000000..e936203
--- /dev/null
+++ b/docs/AMDGPU/gfx7_vdst32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_vdst32_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_vdst64_0.rst b/docs/AMDGPU/gfx7_vdst64_0.rst
new file mode 100644 (file)
index 0000000..4cacaa0
--- /dev/null
+++ b/docs/AMDGPU/gfx7_vdst64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_vdst64_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_vdst96_0.rst b/docs/AMDGPU/gfx7_vdst96_0.rst
new file mode 100644 (file)
index 0000000..3c5bf88
--- /dev/null
+++ b/docs/AMDGPU/gfx7_vdst96_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_vdst96_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_vsrc128_0.rst b/docs/AMDGPU/gfx7_vsrc128_0.rst
new file mode 100644 (file)
index 0000000..9752379
--- /dev/null
+++ b/docs/AMDGPU/gfx7_vsrc128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_vsrc128_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_vsrc32_0.rst b/docs/AMDGPU/gfx7_vsrc32_0.rst
new file mode 100644 (file)
index 0000000..93b12b0
--- /dev/null
+++ b/docs/AMDGPU/gfx7_vsrc32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_vsrc32_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_vsrc64_0.rst b/docs/AMDGPU/gfx7_vsrc64_0.rst
new file mode 100644 (file)
index 0000000..d8c9d45
--- /dev/null
+++ b/docs/AMDGPU/gfx7_vsrc64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_vsrc64_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx7_waitcnt.rst b/docs/AMDGPU/gfx7_waitcnt.rst
new file mode 100644 (file)
index 0000000..c89a320
--- /dev/null
+++ b/docs/AMDGPU/gfx7_waitcnt.rst
@@ -0,0 +1,55 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_waitcnt:
+
+waitcnt
+===========================
+
+Counts of outstanding instructions to wait for.
+
+The bits of this operand have the following meaning:
+
+    ============ ======================================================
+    Bits         Description
+    ============ ======================================================
+    3:0          VM_CNT: vector memory operations count.
+    6:4          EXP_CNT: export count.
+    12:8         LGKM_CNT: LDS, GDS, Constant and Message count.
+    ============ ======================================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>`
+or as a combination of the following symbolic helpers:
+
+    ====================== ======================================================================
+    Syntax                 Description
+    ====================== ======================================================================
+    vmcnt(<*N*>)           VM_CNT value. *N* must not exceed the largest VM_CNT value.
+    expcnt(<*N*>)          EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
+    lgkmcnt(<*N*>)         LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
+    vmcnt_sat(<*N*>)       VM_CNT value computed as min(*N*, the largest VM_CNT value).
+    expcnt_sat(<*N*>)      EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
+    lgkmcnt_sat(<*N*>)     LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
+    ====================== ======================================================================
+
+These helpers may be specified in any order. Ampersands and commas may be used as optional separators.
+
+*N* is either an
+:ref:`integer number<amdgpu_synid_integer_number>` or an
+:ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. code-block:: nasm
+
+    s_waitcnt 0
+    s_waitcnt vmcnt(1)
+    s_waitcnt expcnt(2) lgkmcnt(3)
+    s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3)
+    s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
+    s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
+

diff --git a/docs/AMDGPU/gfx8_addr_buf.rst b/docs/AMDGPU/gfx8_addr_buf.rst
new file mode 100644 (file)
index 0000000..74aa275
--- /dev/null
+++ b/docs/AMDGPU/gfx8_addr_buf.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_addr_buf:
+
+vaddr
+===========================
+
+This is an optional operand which may specify offset and/or index.
+
+*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
+
+* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
+* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
+* If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords.
+* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`

diff --git a/docs/AMDGPU/gfx8_addr_ds.rst b/docs/AMDGPU/gfx8_addr_ds.rst
new file mode 100644 (file)
index 0000000..7115ff0
--- /dev/null
+++ b/docs/AMDGPU/gfx8_addr_ds.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_addr_ds:
+
+vaddr
+===========================
+
+An offset from the start of GDS/LDS memory.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_addr_flat.rst b/docs/AMDGPU/gfx8_addr_flat.rst
new file mode 100644 (file)
index 0000000..53dfcc3
--- /dev/null
+++ b/docs/AMDGPU/gfx8_addr_flat.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_addr_flat:
+
+vaddr
+===========================
+
+A 64-bit flat address.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_addr_mimg.rst b/docs/AMDGPU/gfx8_addr_mimg.rst
new file mode 100644 (file)
index 0000000..f1052ba
--- /dev/null
+++ b/docs/AMDGPU/gfx8_addr_mimg.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_addr_mimg:
+
+vaddr
+===========================
+
+Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
+
+*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode and specific image being handled.
+
+    Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
+
+    Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_attr.rst b/docs/AMDGPU/gfx8_attr.rst
new file mode 100644 (file)
index 0000000..3f28033
--- /dev/null
+++ b/docs/AMDGPU/gfx8_attr.rst
@@ -0,0 +1,30 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_attr:
+
+attr
+===========================
+
+Interpolation attribute and channel:
+
+    ============== ===================================
+    Syntax         Description
+    ============== ===================================
+    attr{0..32}.x  Attribute 0..32 with *x* channel.
+    attr{0..32}.y  Attribute 0..32 with *y* channel.
+    attr{0..32}.z  Attribute 0..32 with *z* channel.
+    attr{0..32}.w  Attribute 0..32 with *w* channel.
+    ============== ===================================
+
+Examples:
+
+.. code-block:: nasm
+
+    v_interp_p1_f32 v1, v0, attr0.x
+    v_interp_p1_f32 v1, v0, attr32.w
+

diff --git a/docs/AMDGPU/gfx8_base_smem_addr.rst b/docs/AMDGPU/gfx8_base_smem_addr.rst
new file mode 100644 (file)
index 0000000..81ef255
--- /dev/null
+++ b/docs/AMDGPU/gfx8_base_smem_addr.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_base_smem_addr:
+
+sbase
+===========================
+
+A 64-bit base address for scalar memory operations.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

diff --git a/docs/AMDGPU/gfx8_base_smem_buf.rst b/docs/AMDGPU/gfx8_base_smem_buf.rst
new file mode 100644 (file)
index 0000000..fb243d0
--- /dev/null
+++ b/docs/AMDGPU/gfx8_base_smem_buf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_base_smem_buf:
+
+sbase
+===========================
+
+A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx8_bimm16.rst b/docs/AMDGPU/gfx8_bimm16.rst
new file mode 100644 (file)
index 0000000..ed50e55
--- /dev/null
+++ b/docs/AMDGPU/gfx8_bimm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_bimm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits.
+

diff --git a/docs/AMDGPU/gfx8_bimm32.rst b/docs/AMDGPU/gfx8_bimm32.rst
new file mode 100644 (file)
index 0000000..d03c27b
--- /dev/null
+++ b/docs/AMDGPU/gfx8_bimm32.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_bimm32:
+
+imm32
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits.
+

diff --git a/docs/AMDGPU/gfx8_data_buf_atomic128.rst b/docs/AMDGPU/gfx8_data_buf_atomic128.rst
new file mode 100644 (file)
index 0000000..40b6d3a
--- /dev/null
+++ b/docs/AMDGPU/gfx8_data_buf_atomic128.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_data_buf_atomic128:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_data_buf_atomic32.rst b/docs/AMDGPU/gfx8_data_buf_atomic32.rst
new file mode 100644 (file)
index 0000000..5112182
--- /dev/null
+++ b/docs/AMDGPU/gfx8_data_buf_atomic32.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_data_buf_atomic32:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_data_buf_atomic64.rst b/docs/AMDGPU/gfx8_data_buf_atomic64.rst
new file mode 100644 (file)
index 0000000..107998e
--- /dev/null
+++ b/docs/AMDGPU/gfx8_data_buf_atomic64.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_data_buf_atomic64:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_data_buf_d16_128.rst b/docs/AMDGPU/gfx8_data_buf_d16_128.rst
new file mode 100644 (file)
index 0000000..3c98a36
--- /dev/null
+++ b/docs/AMDGPU/gfx8_data_buf_d16_128.rst
@@ -0,0 +1,20 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_data_buf_d16_128:
+
+vdata
+===========================
+
+16-bit data to store by a buffer instruction.
+
+*Size:* depends on GFX8 GPU revision:
+
+* 4 dwords for GFX8.0. This H/W supports no packing.
+* 2 dwords for GFX8.1+. This H/W supports data packing.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_data_buf_d16_32.rst b/docs/AMDGPU/gfx8_data_buf_d16_32.rst
new file mode 100644 (file)
index 0000000..6432875
--- /dev/null
+++ b/docs/AMDGPU/gfx8_data_buf_d16_32.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_data_buf_d16_32:
+
+vdata
+===========================
+
+16-bit data to store by a buffer instruction.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_data_buf_d16_64.rst b/docs/AMDGPU/gfx8_data_buf_d16_64.rst
new file mode 100644 (file)
index 0000000..932ce69
--- /dev/null
+++ b/docs/AMDGPU/gfx8_data_buf_d16_64.rst
@@ -0,0 +1,20 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_data_buf_d16_64:
+
+vdata
+===========================
+
+16-bit data to store by a buffer instruction.
+
+*Size:* depends on GFX8 GPU revision:
+
+* 2 dwords for GFX8.0. This H/W supports no packing.
+* 1 dword for GFX8.1+. This H/W supports data packing.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_data_buf_d16_96.rst b/docs/AMDGPU/gfx8_data_buf_d16_96.rst
new file mode 100644 (file)
index 0000000..b9e6915
--- /dev/null
+++ b/docs/AMDGPU/gfx8_data_buf_d16_96.rst
@@ -0,0 +1,20 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_data_buf_d16_96:
+
+vdata
+===========================
+
+16-bit data to store by a buffer instruction.
+
+*Size:* depends on GFX8 GPU revision:
+
+* 3 dwords for GFX8.0. This H/W supports no packing.
+* 2 dwords for GFX8.1+. This H/W supports data packing.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst b/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst
new file mode 100644 (file)
index 0000000..80222ea
--- /dev/null
+++ b/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst
@@ -0,0 +1,27 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_data_mimg_atomic_cmp:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+  Note. The surface data format is indicated in the image resource constant but not in the instruction.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst b/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst
new file mode 100644 (file)
index 0000000..8baf926
--- /dev/null
+++ b/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst
@@ -0,0 +1,26 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_data_mimg_atomic_reg:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+  Note. The surface data format is indicated in the image resource constant but not in the instruction.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_data_mimg_store.rst b/docs/AMDGPU/gfx8_data_mimg_store.rst
new file mode 100644 (file)
index 0000000..65a1a49
--- /dev/null
+++ b/docs/AMDGPU/gfx8_data_mimg_store.rst
@@ -0,0 +1,18 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_data_mimg_store:
+
+vdata
+===========================
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` which may specify from 1 to 4 data elements. Each data element occupies 1 dword.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_data_mimg_store_d16.rst b/docs/AMDGPU/gfx8_data_mimg_store_d16.rst
new file mode 100644 (file)
index 0000000..7524c88
--- /dev/null
+++ b/docs/AMDGPU/gfx8_data_mimg_store_d16.rst
@@ -0,0 +1,24 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_data_mimg_store_d16:
+
+vdata
+===========================
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` has different meaning for GFX8.0 and GFX8.1:
+
+  * For GFX8.0 this modifier does not affect size of data elements in registers. Data in registers are stored in low 16 bits, high 16 bits are unused. There is no packing.
+  * Starting from GFX8.1 this modifier specifies that data elements in registers are packed; each value occupies 16 bits.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_dst_buf_128.rst b/docs/AMDGPU/gfx8_dst_buf_128.rst
new file mode 100644 (file)
index 0000000..d076c70
--- /dev/null
+++ b/docs/AMDGPU/gfx8_dst_buf_128.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_dst_buf_128:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_dst_buf_64.rst b/docs/AMDGPU/gfx8_dst_buf_64.rst
new file mode 100644 (file)
index 0000000..f5da65b
--- /dev/null
+++ b/docs/AMDGPU/gfx8_dst_buf_64.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_dst_buf_64:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_dst_buf_96.rst b/docs/AMDGPU/gfx8_dst_buf_96.rst
new file mode 100644 (file)
index 0000000..0012c1a
--- /dev/null
+++ b/docs/AMDGPU/gfx8_dst_buf_96.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_dst_buf_96:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_dst_buf_d16_128.rst b/docs/AMDGPU/gfx8_dst_buf_d16_128.rst
new file mode 100644 (file)
index 0000000..0f5318d
--- /dev/null
+++ b/docs/AMDGPU/gfx8_dst_buf_d16_128.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_dst_buf_d16_128:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer and converted to a 16-bit format.
+
+*Size:* depends on GFX8 GPU revision and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* 4 dwords for GFX8.0. This H/W supports no packing.
+* 2 dwords for GFX8.1+. This H/W supports data packing.
+* :ref:`tfe<amdgpu_synid_tfe>` adds one dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_dst_buf_d16_32.rst b/docs/AMDGPU/gfx8_dst_buf_d16_32.rst
new file mode 100644 (file)
index 0000000..6288c2d
--- /dev/null
+++ b/docs/AMDGPU/gfx8_dst_buf_d16_32.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_dst_buf_d16_32:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer and converted to a 16-bit format.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_dst_buf_d16_64.rst b/docs/AMDGPU/gfx8_dst_buf_d16_64.rst
new file mode 100644 (file)
index 0000000..b46310f
--- /dev/null
+++ b/docs/AMDGPU/gfx8_dst_buf_d16_64.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_dst_buf_d16_64:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer and converted to a 16-bit format.
+
+*Size:* depends on GFX8 GPU revision and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* 2 dwords for GFX8.0. This H/W supports no packing.
+* 1 dword for GFX8.1+. This H/W supports data packing.
+* :ref:`tfe<amdgpu_synid_tfe>` adds one dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_dst_buf_d16_96.rst b/docs/AMDGPU/gfx8_dst_buf_d16_96.rst
new file mode 100644 (file)
index 0000000..15e7e89
--- /dev/null
+++ b/docs/AMDGPU/gfx8_dst_buf_d16_96.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_dst_buf_d16_96:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer and converted to a 16-bit format.
+
+*Size:* depends on GFX8 GPU revision and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* 3 dwords for GFX8.0. This H/W supports no packing.
+* 2 dwords for GFX8.1+. This H/W supports data packing.
+* :ref:`tfe<amdgpu_synid_tfe>` adds one dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_dst_buf_lds.rst b/docs/AMDGPU/gfx8_dst_buf_lds.rst
new file mode 100644 (file)
index 0000000..b1cb145
--- /dev/null
+++ b/docs/AMDGPU/gfx8_dst_buf_lds.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_dst_buf_lds:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+If :ref:`lds<amdgpu_synid_lds>` is specified, this operand is ignored by H/W and data are stored directly into LDS.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+    Note that :ref:`tfe<amdgpu_synid_tfe>` and :ref:`lds<amdgpu_synid_lds>` cannot be used together.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_dst_flat_atomic32.rst b/docs/AMDGPU/gfx8_dst_flat_atomic32.rst
new file mode 100644 (file)
index 0000000..a8ae464
--- /dev/null
+++ b/docs/AMDGPU/gfx8_dst_flat_atomic32.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_dst_flat_atomic32:
+
+vdst
+===========================
+
+Data returned by a 32-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_dst_flat_atomic64.rst b/docs/AMDGPU/gfx8_dst_flat_atomic64.rst
new file mode 100644 (file)
index 0000000..5b46e88
--- /dev/null
+++ b/docs/AMDGPU/gfx8_dst_flat_atomic64.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_dst_flat_atomic64:
+
+vdst
+===========================
+
+Data returned by a 64-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_dst_mimg_gather4.rst b/docs/AMDGPU/gfx8_dst_mimg_gather4.rst
new file mode 100644 (file)
index 0000000..6fc0192
--- /dev/null
+++ b/docs/AMDGPU/gfx8_dst_mimg_gather4.rst
@@ -0,0 +1,26 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_dst_mimg_gather4:
+
+vdst
+===========================
+
+Image data to load by an *image_gather4* instruction.
+
+*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+
+:ref:`d16<amdgpu_synid_d16>` and :ref:`tfe<amdgpu_synid_tfe>` affect operand size as follows:
+
+* :ref:`d16<amdgpu_synid_d16>` has different meaning for GFX8.0 and GFX8.1:
+
+  * For GFX8.0 this modifier does not affect size of data elements in registers. Data in registers are stored in low 16 bits, high 16 bits are unused. There is no packing.
+  * Starting from GFX8.1 this modifier specifies that data elements in registers are packed; each value occupies 16 bits.
+
+* :ref:`tfe<amdgpu_synid_tfe>` adds one dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_dst_mimg_regular.rst b/docs/AMDGPU/gfx8_dst_mimg_regular.rst
new file mode 100644 (file)
index 0000000..be1037a
--- /dev/null
+++ b/docs/AMDGPU/gfx8_dst_mimg_regular.rst
@@ -0,0 +1,20 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_dst_mimg_regular:
+
+vdst
+===========================
+
+Image data to load by an image instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_dst_mimg_regular_d16.rst b/docs/AMDGPU/gfx8_dst_mimg_regular_d16.rst
new file mode 100644 (file)
index 0000000..4eb7037
--- /dev/null
+++ b/docs/AMDGPU/gfx8_dst_mimg_regular_d16.rst
@@ -0,0 +1,26 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_dst_mimg_regular_d16:
+
+vdst
+===========================
+
+Image data to load by an image instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`, :ref:`tfe<amdgpu_synid_tfe>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` has different meaning for GFX8.0 and GFX8.1:
+
+  * For GFX8.0 this modifier does not affect size of data elements in registers. Data in registers are stored in low 16 bits, high 16 bits are unused. There is no packing.
+  * Starting from GFX8.1 this modifier specifies that data elements in registers are packed; each value occupies 16 bits.
+
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_fimm16.rst b/docs/AMDGPU/gfx8_fimm16.rst
new file mode 100644 (file)
index 0000000..5e387f5
--- /dev/null
+++ b/docs/AMDGPU/gfx8_fimm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_fimm16:
+
+imm32
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The number is converted to *f16* as described :ref:`here<amdgpu_synid_lit_conv>`.
+

diff --git a/docs/AMDGPU/gfx8_fimm32.rst b/docs/AMDGPU/gfx8_fimm32.rst
new file mode 100644 (file)
index 0000000..e29e770
--- /dev/null
+++ b/docs/AMDGPU/gfx8_fimm32.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_fimm32:
+
+imm32
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The value is converted to *f32* as described :ref:`here<amdgpu_synid_lit_conv>`.
+

diff --git a/docs/AMDGPU/gfx8_hwreg.rst b/docs/AMDGPU/gfx8_hwreg.rst
new file mode 100644 (file)
index 0000000..d9b4299
--- /dev/null
+++ b/docs/AMDGPU/gfx8_hwreg.rst
@@ -0,0 +1,60 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_hwreg:
+
+hwreg
+===========================
+
+Bits of a hardware register being accessed.
+
+The bits of this operand have the following meaning:
+
+    ============ ===================================
+    Bits         Description
+    ============ ===================================
+    5:0          Register *id*.
+    10:6         First bit *offset* (0..31).
+    15:11        *Size* in bits (1..32).
+    ============ ===================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below.
+
+    ==================================== ============================================================================
+    Syntax                               Description
+    ==================================== ============================================================================
+    hwreg({0..63})                       All bits of a register indicated by its *id*.
+    hwreg(<*name*>)                      All bits of a register indicated by its *name*.
+    hwreg({0..63}, {0..31}, {1..32})     Register bits indicated by register *id*, first bit *offset* and *size*.
+    hwreg(<*name*>, {0..31}, {1..32})    Register bits indicated by register *name*, first bit *offset* and *size*.
+    ==================================== ============================================================================
+
+Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
+
+Defined register *names* include:
+
+    =================== ==========================================
+    Name                Description
+    =================== ==========================================
+    HW_REG_MODE         Shader writeable mode bits.
+    HW_REG_STATUS       Shader read-only status.
+    HW_REG_TRAPSTS      Trap status.
+    HW_REG_HW_ID        Id of wave, simd, compute unit, etc.
+    HW_REG_GPR_ALLOC    Per-wave SGPR and VGPR allocation.
+    HW_REG_LDS_ALLOC    Per-wave LDS allocation.
+    HW_REG_IB_STS       Counters of outstanding instructions.
+    =================== ==========================================
+
+Examples:
+
+.. code-block:: nasm
+
+    s_getreg_b32 s2, 0x6
+    s_getreg_b32 s2, hwreg(15)
+    s_getreg_b32 s2, hwreg(51, 1, 31)
+    s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
+

diff --git a/docs/AMDGPU/gfx8_imm4.rst b/docs/AMDGPU/gfx8_imm4.rst
new file mode 100644 (file)
index 0000000..a03de76
--- /dev/null
+++ b/docs/AMDGPU/gfx8_imm4.rst
@@ -0,0 +1,25 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_imm4:
+
+imm4
+===========================
+
+A positive :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 4 bits.
+
+This operand is a mask which controls indexing mode for operands of subsequent instructions. Value 1 enables indexing and value 0 disables it.
+
+    ============ ========================================
+    Bit          Meaning
+    ============ ========================================
+    0            Enables or disables *src0* indexing.
+    1            Enables or disables *src1* indexing.
+    2            Enables or disables *src2* indexing.
+    3            Enables or disables *dst* indexing.
+    ============ ========================================
+

diff --git a/docs/AMDGPU/gfx8_label.rst b/docs/AMDGPU/gfx8_label.rst
new file mode 100644 (file)
index 0000000..af63ad9
--- /dev/null
+++ b/docs/AMDGPU/gfx8_label.rst
@@ -0,0 +1,30 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_label:
+
+label
+===========================
+
+A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
+
+This operand may be specified as:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>`. The number is truncated to 16 bits.
+* An :ref:`absolute_expression<amdgpu_synid_absolute_expression>` which must start with an :ref:`integer_number<amdgpu_synid_integer_number>`. The value of the expression is truncated to 16 bits.
+* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
+
+Examples:
+
+.. code-block:: nasm
+
+  offset = 30
+  s_branch loop_end
+  s_branch 2 + offset
+  s_branch 32
+  loop_end:
+

diff --git a/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst b/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst
new file mode 100644 (file)
index 0000000..be7b4b5
--- /dev/null
+++ b/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_mod_dpp_sdwa_abs_neg:
+
+m
+===========================
+
+This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
+

diff --git a/docs/AMDGPU/gfx8_mod_sdwa_sext.rst b/docs/AMDGPU/gfx8_mod_sdwa_sext.rst
new file mode 100644 (file)
index 0000000..b48c521
--- /dev/null
+++ b/docs/AMDGPU/gfx8_mod_sdwa_sext.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_mod_sdwa_sext:
+
+m
+===========================
+
+This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
+

diff --git a/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst b/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst
new file mode 100644 (file)
index 0000000..960e8b1
--- /dev/null
+++ b/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_mod_vop3_abs_neg:
+
+m
+===========================
+
+This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
+

diff --git a/docs/AMDGPU/gfx8_msg.rst b/docs/AMDGPU/gfx8_msg.rst
new file mode 100644 (file)
index 0000000..8140bc2
--- /dev/null
+++ b/docs/AMDGPU/gfx8_msg.rst
@@ -0,0 +1,72 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_msg:
+
+msg
+===========================
+
+A 16-bit message code. The bits of this operand have the following meaning:
+
+    ============ ======================================================
+    Bits         Description
+    ============ ======================================================
+    3:0          Message *type*.
+    6:4          Optional *operation*.
+    9:7          Optional *parameters*.
+    15:10        Unused.
+    ============ ======================================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below:
+
+    ======================================== ========================================================================
+    Syntax                                   Description
+    ======================================== ========================================================================
+    sendmsg(<*type*>)                        A message identified by its *type*.
+    sendmsg(<*type*>, <*op*>)                A message identified by its *type* and *operation*.
+    sendmsg(<*type*>, <*op*>, <*stream*>)    A message identified by its *type* and *operation* with a stream *id*.
+    ======================================== ========================================================================
+
+*Type* may be specified using message *name* or message *id*.
+
+*Op* may be specified using operation *name* or operation *id*.
+
+Stream *id* is an integer in the range 0..3.
+
+Message *id*, operation *id* and stream *id* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
+
+Each message type supports specific operations:
+
+    ================= ========== ============================== ============ ==========
+    Message name      Message Id Supported Operations           Operation Id Stream Id
+    ================= ========== ============================== ============ ==========
+    MSG_INTERRUPT     1          \-                             \-           \-
+    MSG_GS            2          GS_OP_CUT                      1            Optional
+    \                            GS_OP_EMIT                     2            Optional
+    \                            GS_OP_EMIT_CUT                 3            Optional
+    MSG_GS_DONE       3          GS_OP_NOP                      0            \-
+    \                            GS_OP_CUT                      1            Optional
+    \                            GS_OP_EMIT                     2            Optional
+    \                            GS_OP_EMIT_CUT                 3            Optional
+    MSG_SYSMSG        15         SYSMSG_OP_ECC_ERR_INTERRUPT    1            \-
+    \                            SYSMSG_OP_REG_RD               2            \-
+    \                            SYSMSG_OP_HOST_TRAP_ACK        3            \-
+    \                            SYSMSG_OP_TTRACE_PC            4            \-
+    ================= ========== ============================== ============ ==========
+
+Examples:
+
+.. code-block:: nasm
+
+    s_sendmsg 0x12
+    s_sendmsg sendmsg(MSG_INTERRUPT)
+    s_sendmsg sendmsg(2, GS_OP_CUT)
+    s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
+    s_sendmsg sendmsg(MSG_GS, 2)
+    s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
+    s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)
+

diff --git a/docs/AMDGPU/gfx8_offset_buf.rst b/docs/AMDGPU/gfx8_offset_buf.rst
new file mode 100644 (file)
index 0000000..42c4524
--- /dev/null
+++ b/docs/AMDGPU/gfx8_offset_buf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_offset_buf:
+
+soffset
+===========================
+
+An unsigned byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

diff --git a/docs/AMDGPU/gfx8_offset_smem_load.rst b/docs/AMDGPU/gfx8_offset_smem_load.rst
new file mode 100644 (file)
index 0000000..5c30a87
--- /dev/null
+++ b/docs/AMDGPU/gfx8_offset_smem_load.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_offset_smem_load:
+
+soffset
+===========================
+
+An unsigned byte offset added to the base address to get memory address.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`

diff --git a/docs/AMDGPU/gfx8_offset_smem_store.rst b/docs/AMDGPU/gfx8_offset_smem_store.rst
new file mode 100644 (file)
index 0000000..9ff90f9
--- /dev/null
+++ b/docs/AMDGPU/gfx8_offset_smem_store.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_offset_smem_store:
+
+soffset
+===========================
+
+An unsigned byte offset added to the base address to get memory address.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`

diff --git a/docs/AMDGPU/gfx8_opt.rst b/docs/AMDGPU/gfx8_opt.rst
new file mode 100644 (file)
index 0000000..417d7fa
--- /dev/null
+++ b/docs/AMDGPU/gfx8_opt.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_opt:
+
+opt
+===========================
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+

diff --git a/docs/AMDGPU/gfx8_param.rst b/docs/AMDGPU/gfx8_param.rst
new file mode 100644 (file)
index 0000000..0bd8854
--- /dev/null
+++ b/docs/AMDGPU/gfx8_param.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_param:
+
+param
+===========================
+
+Interpolation parameter to read:
+
+    ============ ===================================
+    Syntax       Description
+    ============ ===================================
+    p0           Parameter *P0*.
+    p10          Parameter *P10*.
+    p20          Parameter *P20*.
+    ============ ===================================
+

diff --git a/docs/AMDGPU/gfx8_perm_smem.rst b/docs/AMDGPU/gfx8_perm_smem.rst
new file mode 100644 (file)
index 0000000..0035ac8
--- /dev/null
+++ b/docs/AMDGPU/gfx8_perm_smem.rst
@@ -0,0 +1,24 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_perm_smem:
+
+imm3
+===========================
+
+A bit mask which indicates request permissions.
+
+This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 7 bits, but only 3 low bits are significant.
+
+    ============ ==============================
+    Bit Number   Description
+    ============ ==============================
+    0            Request *read* permission.
+    1            Request *write* permission.
+    2            Request *execute* permission.
+    ============ ==============================
+

diff --git a/docs/AMDGPU/gfx8_ret.rst b/docs/AMDGPU/gfx8_ret.rst
new file mode 100644 (file)
index 0000000..91fdaf3
--- /dev/null
+++ b/docs/AMDGPU/gfx8_ret.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_ret:
+
+dst
+===========================
+
+This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
+

diff --git a/docs/AMDGPU/gfx8_rsrc_buf.rst b/docs/AMDGPU/gfx8_rsrc_buf.rst
new file mode 100644 (file)
index 0000000..ecdb0a0
--- /dev/null
+++ b/docs/AMDGPU/gfx8_rsrc_buf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_rsrc_buf:
+
+srsrc
+===========================
+
+Buffer resource constant which defines the address and characteristics of the buffer in memory.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx8_rsrc_mimg.rst b/docs/AMDGPU/gfx8_rsrc_mimg.rst
new file mode 100644 (file)
index 0000000..3ca2559
--- /dev/null
+++ b/docs/AMDGPU/gfx8_rsrc_mimg.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_rsrc_mimg:
+
+srsrc
+===========================
+
+Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
+
+*Size:* 8 dwords by default, 4 dwords if :ref:`r128<amdgpu_synid_r128>` is specified.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx8_samp_mimg.rst b/docs/AMDGPU/gfx8_samp_mimg.rst
new file mode 100644 (file)
index 0000000..c4b2712
--- /dev/null
+++ b/docs/AMDGPU/gfx8_samp_mimg.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_samp_mimg:
+
+ssamp
+===========================
+
+Sampler constant used to specify filtering options applied to the image data after it is read.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx8_sdata128_0.rst b/docs/AMDGPU/gfx8_sdata128_0.rst
new file mode 100644 (file)
index 0000000..a52703c
--- /dev/null
+++ b/docs/AMDGPU/gfx8_sdata128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_sdata128_0:
+
+sdata
+===========================
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx8_sdata32_0.rst b/docs/AMDGPU/gfx8_sdata32_0.rst
new file mode 100644 (file)
index 0000000..9ccd7bd
--- /dev/null
+++ b/docs/AMDGPU/gfx8_sdata32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_sdata32_0:
+
+sdata
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

diff --git a/docs/AMDGPU/gfx8_sdata64_0.rst b/docs/AMDGPU/gfx8_sdata64_0.rst
new file mode 100644 (file)
index 0000000..8718449
--- /dev/null
+++ b/docs/AMDGPU/gfx8_sdata64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_sdata64_0:
+
+sdata
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

diff --git a/docs/AMDGPU/gfx8_sdst128_0.rst b/docs/AMDGPU/gfx8_sdst128_0.rst
new file mode 100644 (file)
index 0000000..277e3db
--- /dev/null
+++ b/docs/AMDGPU/gfx8_sdst128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_sdst128_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx8_sdst256_0.rst b/docs/AMDGPU/gfx8_sdst256_0.rst
new file mode 100644 (file)
index 0000000..2e54b9b
--- /dev/null
+++ b/docs/AMDGPU/gfx8_sdst256_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_sdst256_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx8_sdst32_0.rst b/docs/AMDGPU/gfx8_sdst32_0.rst
new file mode 100644 (file)
index 0000000..44e6cdc
--- /dev/null
+++ b/docs/AMDGPU/gfx8_sdst32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_sdst32_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

diff --git a/docs/AMDGPU/gfx8_sdst32_1.rst b/docs/AMDGPU/gfx8_sdst32_1.rst
new file mode 100644 (file)
index 0000000..7156225
--- /dev/null
+++ b/docs/AMDGPU/gfx8_sdst32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_sdst32_1:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`

diff --git a/docs/AMDGPU/gfx8_sdst32_2.rst b/docs/AMDGPU/gfx8_sdst32_2.rst
new file mode 100644 (file)
index 0000000..af446d3
--- /dev/null
+++ b/docs/AMDGPU/gfx8_sdst32_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_sdst32_2:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`trap<amdgpu_synid_trap>`

diff --git a/docs/AMDGPU/gfx8_sdst512_0.rst b/docs/AMDGPU/gfx8_sdst512_0.rst
new file mode 100644 (file)
index 0000000..95b82a7
--- /dev/null
+++ b/docs/AMDGPU/gfx8_sdst512_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_sdst512_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`

diff --git a/docs/AMDGPU/gfx8_sdst64_0.rst b/docs/AMDGPU/gfx8_sdst64_0.rst
new file mode 100644 (file)
index 0000000..9195778
--- /dev/null
+++ b/docs/AMDGPU/gfx8_sdst64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_sdst64_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

diff --git a/docs/AMDGPU/gfx8_sdst64_1.rst b/docs/AMDGPU/gfx8_sdst64_1.rst
new file mode 100644 (file)
index 0000000..165e0c0
--- /dev/null
+++ b/docs/AMDGPU/gfx8_sdst64_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_sdst64_1:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`

diff --git a/docs/AMDGPU/gfx8_simm16.rst b/docs/AMDGPU/gfx8_simm16.rst
new file mode 100644 (file)
index 0000000..730f239
--- /dev/null
+++ b/docs/AMDGPU/gfx8_simm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_simm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then sign-extended to 32 bits.
+

diff --git a/docs/AMDGPU/gfx8_src32_0.rst b/docs/AMDGPU/gfx8_src32_0.rst
new file mode 100644 (file)
index 0000000..a9c11fe
--- /dev/null
+++ b/docs/AMDGPU/gfx8_src32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_src32_0:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

diff --git a/docs/AMDGPU/gfx8_src32_1.rst b/docs/AMDGPU/gfx8_src32_1.rst
new file mode 100644 (file)
index 0000000..67dcdc8
--- /dev/null
+++ b/docs/AMDGPU/gfx8_src32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_src32_1:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

diff --git a/docs/AMDGPU/gfx8_src64_0.rst b/docs/AMDGPU/gfx8_src64_0.rst
new file mode 100644 (file)
index 0000000..573fd68
--- /dev/null
+++ b/docs/AMDGPU/gfx8_src64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_src64_0:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

diff --git a/docs/AMDGPU/gfx8_src64_1.rst b/docs/AMDGPU/gfx8_src64_1.rst
new file mode 100644 (file)
index 0000000..d2c78b7
--- /dev/null
+++ b/docs/AMDGPU/gfx8_src64_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_src64_1:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

diff --git a/docs/AMDGPU/gfx8_src_exp.rst b/docs/AMDGPU/gfx8_src_exp.rst
new file mode 100644 (file)
index 0000000..92340c5
--- /dev/null
+++ b/docs/AMDGPU/gfx8_src_exp.rst
@@ -0,0 +1,28 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_src_exp:
+
+vsrc
+===========================
+
+Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+:ref:`compr<amdgpu_synid_compr>` modifier indicates use of compressed (16-bit) data. This limits number of source operands from 4 to 2:
+
+* src0 and src1 must specify the first register (or :ref:`off<amdgpu_synid_off>`).
+* src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
+
+An example:
+
+.. code-block:: nasm
+
+  exp mrtz v3, v3, off, off compr
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`

diff --git a/docs/AMDGPU/gfx8_ssrc32_0.rst b/docs/AMDGPU/gfx8_ssrc32_0.rst
new file mode 100644 (file)
index 0000000..82d18b1
--- /dev/null
+++ b/docs/AMDGPU/gfx8_ssrc32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_ssrc32_0:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

diff --git a/docs/AMDGPU/gfx8_ssrc32_1.rst b/docs/AMDGPU/gfx8_ssrc32_1.rst
new file mode 100644 (file)
index 0000000..203d9c5
--- /dev/null
+++ b/docs/AMDGPU/gfx8_ssrc32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_ssrc32_1:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

diff --git a/docs/AMDGPU/gfx8_ssrc32_2.rst b/docs/AMDGPU/gfx8_ssrc32_2.rst
new file mode 100644 (file)
index 0000000..9b893e9
--- /dev/null
+++ b/docs/AMDGPU/gfx8_ssrc32_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_ssrc32_2:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`

diff --git a/docs/AMDGPU/gfx8_ssrc32_3.rst b/docs/AMDGPU/gfx8_ssrc32_3.rst
new file mode 100644 (file)
index 0000000..131765f
--- /dev/null
+++ b/docs/AMDGPU/gfx8_ssrc32_3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_ssrc32_3:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`

diff --git a/docs/AMDGPU/gfx8_ssrc32_4.rst b/docs/AMDGPU/gfx8_ssrc32_4.rst
new file mode 100644 (file)
index 0000000..02d90a4
--- /dev/null
+++ b/docs/AMDGPU/gfx8_ssrc32_4.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_ssrc32_4:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

diff --git a/docs/AMDGPU/gfx8_ssrc64_0.rst b/docs/AMDGPU/gfx8_ssrc64_0.rst
new file mode 100644 (file)
index 0000000..b8389dc
--- /dev/null
+++ b/docs/AMDGPU/gfx8_ssrc64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_ssrc64_0:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

diff --git a/docs/AMDGPU/gfx8_ssrc64_1.rst b/docs/AMDGPU/gfx8_ssrc64_1.rst
new file mode 100644 (file)
index 0000000..c4fddf4
--- /dev/null
+++ b/docs/AMDGPU/gfx8_ssrc64_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_ssrc64_1:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

diff --git a/docs/AMDGPU/gfx8_ssrc64_2.rst b/docs/AMDGPU/gfx8_ssrc64_2.rst
new file mode 100644 (file)
index 0000000..209dffc
--- /dev/null
+++ b/docs/AMDGPU/gfx8_ssrc64_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_ssrc64_2:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

diff --git a/docs/AMDGPU/gfx8_ssrc64_3.rst b/docs/AMDGPU/gfx8_ssrc64_3.rst
new file mode 100644 (file)
index 0000000..9ab5436
--- /dev/null
+++ b/docs/AMDGPU/gfx8_ssrc64_3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_ssrc64_3:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`

diff --git a/docs/AMDGPU/gfx8_tgt.rst b/docs/AMDGPU/gfx8_tgt.rst
new file mode 100644 (file)
index 0000000..1be54a7
--- /dev/null
+++ b/docs/AMDGPU/gfx8_tgt.rst
@@ -0,0 +1,24 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_tgt:
+
+tgt
+===========================
+
+An export target:
+
+    ============== ===================================
+    Syntax         Description
+    ============== ===================================
+    pos{0..3}      Copy vertex position 0..3.
+    param{0..31}   Copy vertex parameter 0..31.
+    mrt{0..7}      Copy pixel color to the MRTs 0..7.
+    mrtz           Copy pixel depth (Z) data.
+    null           Copy nothing.
+    ============== ===================================
+

diff --git a/docs/AMDGPU/gfx8_type_dev.rst b/docs/AMDGPU/gfx8_type_dev.rst
new file mode 100644 (file)
index 0000000..2f5b36f
--- /dev/null
+++ b/docs/AMDGPU/gfx8_type_dev.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_type_dev:
+
+Type deviation
+===========================
+
+*Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.
+

diff --git a/docs/AMDGPU/gfx8_uimm16.rst b/docs/AMDGPU/gfx8_uimm16.rst
new file mode 100644 (file)
index 0000000..a20abcc
--- /dev/null
+++ b/docs/AMDGPU/gfx8_uimm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_uimm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then zero-extended to 32 bits.
+

diff --git a/docs/AMDGPU/gfx8_vcc_64.rst b/docs/AMDGPU/gfx8_vcc_64.rst
new file mode 100644 (file)
index 0000000..e31df0e
--- /dev/null
+++ b/docs/AMDGPU/gfx8_vcc_64.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_vcc_64:
+
+vcc
+===========================
+
+Vector condition code.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`vcc<amdgpu_synid_vcc>`

diff --git a/docs/AMDGPU/gfx8_vdata128_0.rst b/docs/AMDGPU/gfx8_vdata128_0.rst
new file mode 100644 (file)
index 0000000..bf7e3db
--- /dev/null
+++ b/docs/AMDGPU/gfx8_vdata128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_vdata128_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_vdata32_0.rst b/docs/AMDGPU/gfx8_vdata32_0.rst
new file mode 100644 (file)
index 0000000..b89d65b
--- /dev/null
+++ b/docs/AMDGPU/gfx8_vdata32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_vdata32_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_vdata64_0.rst b/docs/AMDGPU/gfx8_vdata64_0.rst
new file mode 100644 (file)
index 0000000..4380544
--- /dev/null
+++ b/docs/AMDGPU/gfx8_vdata64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_vdata64_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_vdata96_0.rst b/docs/AMDGPU/gfx8_vdata96_0.rst
new file mode 100644 (file)
index 0000000..b8ad22d
--- /dev/null
+++ b/docs/AMDGPU/gfx8_vdata96_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_vdata96_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_vdst128_0.rst b/docs/AMDGPU/gfx8_vdst128_0.rst
new file mode 100644 (file)
index 0000000..1eccc95
--- /dev/null
+++ b/docs/AMDGPU/gfx8_vdst128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_vdst128_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_vdst32_0.rst b/docs/AMDGPU/gfx8_vdst32_0.rst
new file mode 100644 (file)
index 0000000..781fcb6
--- /dev/null
+++ b/docs/AMDGPU/gfx8_vdst32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_vdst32_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_vdst64_0.rst b/docs/AMDGPU/gfx8_vdst64_0.rst
new file mode 100644 (file)
index 0000000..af2dfe9
--- /dev/null
+++ b/docs/AMDGPU/gfx8_vdst64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_vdst64_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_vdst96_0.rst b/docs/AMDGPU/gfx8_vdst96_0.rst
new file mode 100644 (file)
index 0000000..4895b65
--- /dev/null
+++ b/docs/AMDGPU/gfx8_vdst96_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_vdst96_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_vsrc128_0.rst b/docs/AMDGPU/gfx8_vsrc128_0.rst
new file mode 100644 (file)
index 0000000..25b1794
--- /dev/null
+++ b/docs/AMDGPU/gfx8_vsrc128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_vsrc128_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_vsrc32_0.rst b/docs/AMDGPU/gfx8_vsrc32_0.rst
new file mode 100644 (file)
index 0000000..524f36a
--- /dev/null
+++ b/docs/AMDGPU/gfx8_vsrc32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_vsrc32_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_vsrc64_0.rst b/docs/AMDGPU/gfx8_vsrc64_0.rst
new file mode 100644 (file)
index 0000000..7c2c39f
--- /dev/null
+++ b/docs/AMDGPU/gfx8_vsrc64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_vsrc64_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx8_waitcnt.rst b/docs/AMDGPU/gfx8_waitcnt.rst
new file mode 100644 (file)
index 0000000..d164788
--- /dev/null
+++ b/docs/AMDGPU/gfx8_waitcnt.rst
@@ -0,0 +1,55 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_waitcnt:
+
+waitcnt
+===========================
+
+Counts of outstanding instructions to wait for.
+
+The bits of this operand have the following meaning:
+
+    ============ ======================================================
+    Bits         Description
+    ============ ======================================================
+    3:0          VM_CNT: vector memory operations count.
+    6:4          EXP_CNT: export count.
+    11:8         LGKM_CNT: LDS, GDS, Constant and Message count.
+    ============ ======================================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>`
+or as a combination of the following symbolic helpers:
+
+    ====================== ======================================================================
+    Syntax                 Description
+    ====================== ======================================================================
+    vmcnt(<*N*>)           VM_CNT value. *N* must not exceed the largest VM_CNT value.
+    expcnt(<*N*>)          EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
+    lgkmcnt(<*N*>)         LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
+    vmcnt_sat(<*N*>)       VM_CNT value computed as min(*N*, the largest VM_CNT value).
+    expcnt_sat(<*N*>)      EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
+    lgkmcnt_sat(<*N*>)     LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
+    ====================== ======================================================================
+
+These helpers may be specified in any order. Ampersands and commas may be used as optional separators.
+
+*N* is either an
+:ref:`integer number<amdgpu_synid_integer_number>` or an
+:ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. code-block:: nasm
+
+    s_waitcnt 0
+    s_waitcnt vmcnt(1)
+    s_waitcnt expcnt(2) lgkmcnt(3)
+    s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3)
+    s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
+    s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
+

diff --git a/docs/AMDGPU/gfx9_addr_buf.rst b/docs/AMDGPU/gfx9_addr_buf.rst
new file mode 100644 (file)
index 0000000..c253640
--- /dev/null
+++ b/docs/AMDGPU/gfx9_addr_buf.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_addr_buf:
+
+vaddr
+===========================
+
+This is an optional operand which may specify offset and/or index.
+
+*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
+
+* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
+* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
+* If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords.
+* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`

diff --git a/docs/AMDGPU/gfx9_addr_ds.rst b/docs/AMDGPU/gfx9_addr_ds.rst
new file mode 100644 (file)
index 0000000..1174246
--- /dev/null
+++ b/docs/AMDGPU/gfx9_addr_ds.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_addr_ds:
+
+vaddr
+===========================
+
+An offset from the start of GDS/LDS memory.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_addr_flat.rst b/docs/AMDGPU/gfx9_addr_flat.rst
new file mode 100644 (file)
index 0000000..c748d07
--- /dev/null
+++ b/docs/AMDGPU/gfx9_addr_flat.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_addr_flat:
+
+vaddr
+===========================
+
+A 64-bit flat address.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_addr_mimg.rst b/docs/AMDGPU/gfx9_addr_mimg.rst
new file mode 100644 (file)
index 0000000..eb6ca88
--- /dev/null
+++ b/docs/AMDGPU/gfx9_addr_mimg.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_addr_mimg:
+
+vaddr
+===========================
+
+Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
+
+*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode, specific image being handled and :ref:`a16<amdgpu_synid_a16>`.
+
+  Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
+
+  Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_attr.rst b/docs/AMDGPU/gfx9_attr.rst
new file mode 100644 (file)
index 0000000..c69589f
--- /dev/null
+++ b/docs/AMDGPU/gfx9_attr.rst
@@ -0,0 +1,30 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_attr:
+
+attr
+===========================
+
+Interpolation attribute and channel:
+
+    ============== ===================================
+    Syntax         Description
+    ============== ===================================
+    attr{0..32}.x  Attribute 0..32 with *x* channel.
+    attr{0..32}.y  Attribute 0..32 with *y* channel.
+    attr{0..32}.z  Attribute 0..32 with *z* channel.
+    attr{0..32}.w  Attribute 0..32 with *w* channel.
+    ============== ===================================
+
+Examples:
+
+.. code-block:: nasm
+
+    v_interp_p1_f32 v1, v0, attr0.x
+    v_interp_p1_f32 v1, v0, attr32.w
+

diff --git a/docs/AMDGPU/gfx9_base_smem_addr.rst b/docs/AMDGPU/gfx9_base_smem_addr.rst
new file mode 100644 (file)
index 0000000..63c2cbd
--- /dev/null
+++ b/docs/AMDGPU/gfx9_base_smem_addr.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_base_smem_addr:
+
+sbase
+===========================
+
+A 64-bit base address for scalar memory operations.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_base_smem_buf.rst b/docs/AMDGPU/gfx9_base_smem_buf.rst
new file mode 100644 (file)
index 0000000..191ecba
--- /dev/null
+++ b/docs/AMDGPU/gfx9_base_smem_buf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_base_smem_buf:
+
+sbase
+===========================
+
+A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_base_smem_scratch.rst b/docs/AMDGPU/gfx9_base_smem_scratch.rst
new file mode 100644 (file)
index 0000000..83fd760
--- /dev/null
+++ b/docs/AMDGPU/gfx9_base_smem_scratch.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_base_smem_scratch:
+
+sbase
+===========================
+
+This operand is ignored by H/W and :ref:`flat_scratch<amdgpu_synid_flat_scratch>` is supplied instead.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_bimm16.rst b/docs/AMDGPU/gfx9_bimm16.rst
new file mode 100644 (file)
index 0000000..2c9dc5c
--- /dev/null
+++ b/docs/AMDGPU/gfx9_bimm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_bimm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits.
+

diff --git a/docs/AMDGPU/gfx9_bimm32.rst b/docs/AMDGPU/gfx9_bimm32.rst
new file mode 100644 (file)
index 0000000..e9b8967
--- /dev/null
+++ b/docs/AMDGPU/gfx9_bimm32.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_bimm32:
+
+imm32
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits.
+

diff --git a/docs/AMDGPU/gfx9_data_buf_atomic128.rst b/docs/AMDGPU/gfx9_data_buf_atomic128.rst
new file mode 100644 (file)
index 0000000..11c7c73
--- /dev/null
+++ b/docs/AMDGPU/gfx9_data_buf_atomic128.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_data_buf_atomic128:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_data_buf_atomic32.rst b/docs/AMDGPU/gfx9_data_buf_atomic32.rst
new file mode 100644 (file)
index 0000000..7b7d88b
--- /dev/null
+++ b/docs/AMDGPU/gfx9_data_buf_atomic32.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_data_buf_atomic32:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_data_buf_atomic64.rst b/docs/AMDGPU/gfx9_data_buf_atomic64.rst
new file mode 100644 (file)
index 0000000..71b2b4b
--- /dev/null
+++ b/docs/AMDGPU/gfx9_data_buf_atomic64.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_data_buf_atomic64:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst b/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst
new file mode 100644 (file)
index 0000000..08fe297
--- /dev/null
+++ b/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst
@@ -0,0 +1,27 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_data_mimg_atomic_cmp:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+  Note. The surface data format is indicated in the image resource constant but not in the instruction.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst b/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst
new file mode 100644 (file)
index 0000000..2037dfd
--- /dev/null
+++ b/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst
@@ -0,0 +1,26 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_data_mimg_atomic_reg:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+  Note. The surface data format is indicated in the image resource constant but not in the instruction.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_data_mimg_store.rst b/docs/AMDGPU/gfx9_data_mimg_store.rst
new file mode 100644 (file)
index 0000000..5e2b8b6
--- /dev/null
+++ b/docs/AMDGPU/gfx9_data_mimg_store.rst
@@ -0,0 +1,18 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_data_mimg_store:
+
+vdata
+===========================
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` which may specify from 1 to 4 data elements. Each data element occupies 1 dword.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_data_mimg_store_d16.rst b/docs/AMDGPU/gfx9_data_mimg_store_d16.rst
new file mode 100644 (file)
index 0000000..5c521f8
--- /dev/null
+++ b/docs/AMDGPU/gfx9_data_mimg_store_d16.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_data_mimg_store_d16:
+
+vdata
+===========================
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_data_smem_atomic128.rst b/docs/AMDGPU/gfx9_data_smem_atomic128.rst
new file mode 100644 (file)
index 0000000..6773618
--- /dev/null
+++ b/docs/AMDGPU/gfx9_data_smem_atomic128.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_data_smem_atomic128:
+
+sdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_data_smem_atomic32.rst b/docs/AMDGPU/gfx9_data_smem_atomic32.rst
new file mode 100644 (file)
index 0000000..9ad25f3
--- /dev/null
+++ b/docs/AMDGPU/gfx9_data_smem_atomic32.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_data_smem_atomic32:
+
+sdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_data_smem_atomic64.rst b/docs/AMDGPU/gfx9_data_smem_atomic64.rst
new file mode 100644 (file)
index 0000000..6f67bff
--- /dev/null
+++ b/docs/AMDGPU/gfx9_data_smem_atomic64.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_data_smem_atomic64:
+
+sdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_dst_buf_128.rst b/docs/AMDGPU/gfx9_dst_buf_128.rst
new file mode 100644 (file)
index 0000000..691be0f
--- /dev/null
+++ b/docs/AMDGPU/gfx9_dst_buf_128.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_dst_buf_128:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_dst_buf_32.rst b/docs/AMDGPU/gfx9_dst_buf_32.rst
new file mode 100644 (file)
index 0000000..5ee1aa2
--- /dev/null
+++ b/docs/AMDGPU/gfx9_dst_buf_32.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_dst_buf_32:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_dst_buf_64.rst b/docs/AMDGPU/gfx9_dst_buf_64.rst
new file mode 100644 (file)
index 0000000..6e27264
--- /dev/null
+++ b/docs/AMDGPU/gfx9_dst_buf_64.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_dst_buf_64:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_dst_buf_96.rst b/docs/AMDGPU/gfx9_dst_buf_96.rst
new file mode 100644 (file)
index 0000000..8011edc
--- /dev/null
+++ b/docs/AMDGPU/gfx9_dst_buf_96.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_dst_buf_96:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_dst_buf_lds.rst b/docs/AMDGPU/gfx9_dst_buf_lds.rst
new file mode 100644 (file)
index 0000000..0445619
--- /dev/null
+++ b/docs/AMDGPU/gfx9_dst_buf_lds.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_dst_buf_lds:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+If :ref:`lds<amdgpu_synid_lds>` is specified, this operand is ignored by H/W and data are stored directly into LDS.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+    Note that :ref:`tfe<amdgpu_synid_tfe>` and :ref:`lds<amdgpu_synid_lds>` cannot be used together.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_dst_flat_atomic32.rst b/docs/AMDGPU/gfx9_dst_flat_atomic32.rst
new file mode 100644 (file)
index 0000000..94a7fda
--- /dev/null
+++ b/docs/AMDGPU/gfx9_dst_flat_atomic32.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_dst_flat_atomic32:
+
+vdst
+===========================
+
+Data returned by a 32-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_dst_flat_atomic64.rst b/docs/AMDGPU/gfx9_dst_flat_atomic64.rst
new file mode 100644 (file)
index 0000000..7f684a7
--- /dev/null
+++ b/docs/AMDGPU/gfx9_dst_flat_atomic64.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_dst_flat_atomic64:
+
+vdst
+===========================
+
+Data returned by a 64-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_dst_mimg_gather4.rst b/docs/AMDGPU/gfx9_dst_mimg_gather4.rst
new file mode 100644 (file)
index 0000000..3bb6f30
--- /dev/null
+++ b/docs/AMDGPU/gfx9_dst_mimg_gather4.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_dst_mimg_gather4:
+
+vdst
+===========================
+
+Image data to load by an *image_gather4* instruction.
+
+*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+
+:ref:`d16<amdgpu_synid_d16>` and :ref:`tfe<amdgpu_synid_tfe>` affect operand size as follows:
+
+* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
+* :ref:`tfe<amdgpu_synid_tfe>` adds one dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_dst_mimg_regular.rst b/docs/AMDGPU/gfx9_dst_mimg_regular.rst
new file mode 100644 (file)
index 0000000..1a7b848
--- /dev/null
+++ b/docs/AMDGPU/gfx9_dst_mimg_regular.rst
@@ -0,0 +1,20 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_dst_mimg_regular:
+
+vdst
+===========================
+
+Image data to load by an image instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_dst_mimg_regular_d16.rst b/docs/AMDGPU/gfx9_dst_mimg_regular_d16.rst
new file mode 100644 (file)
index 0000000..a155639
--- /dev/null
+++ b/docs/AMDGPU/gfx9_dst_mimg_regular_d16.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_dst_mimg_regular_d16:
+
+vdst
+===========================
+
+Image data to load by an image instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`, :ref:`tfe<amdgpu_synid_tfe>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_fimm16.rst b/docs/AMDGPU/gfx9_fimm16.rst
new file mode 100644 (file)
index 0000000..a438b45
--- /dev/null
+++ b/docs/AMDGPU/gfx9_fimm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_fimm16:
+
+imm32
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The number is converted to *f16* as described :ref:`here<amdgpu_synid_lit_conv>`.
+

diff --git a/docs/AMDGPU/gfx9_fimm32.rst b/docs/AMDGPU/gfx9_fimm32.rst
new file mode 100644 (file)
index 0000000..11103e7
--- /dev/null
+++ b/docs/AMDGPU/gfx9_fimm32.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_fimm32:
+
+imm32
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The value is converted to *f32* as described :ref:`here<amdgpu_synid_lit_conv>`.
+

diff --git a/docs/AMDGPU/gfx9_hwreg.rst b/docs/AMDGPU/gfx9_hwreg.rst
new file mode 100644 (file)
index 0000000..cecba1e
--- /dev/null
+++ b/docs/AMDGPU/gfx9_hwreg.rst
@@ -0,0 +1,61 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_hwreg:
+
+hwreg
+===========================
+
+Bits of a hardware register being accessed.
+
+The bits of this operand have the following meaning:
+
+    ============ ===================================
+    Bits         Description
+    ============ ===================================
+    5:0          Register *id*.
+    10:6         First bit *offset* (0..31).
+    15:11        *Size* in bits (1..32).
+    ============ ===================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below.
+
+    ==================================== ============================================================================
+    Syntax                               Description
+    ==================================== ============================================================================
+    hwreg({0..63})                       All bits of a register indicated by its *id*.
+    hwreg(<*name*>)                      All bits of a register indicated by its *name*.
+    hwreg({0..63}, {0..31}, {1..32})     Register bits indicated by register *id*, first bit *offset* and *size*.
+    hwreg(<*name*>, {0..31}, {1..32})    Register bits indicated by register *name*, first bit *offset* and *size*.
+    ==================================== ============================================================================
+
+Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
+
+Defined register *names* include:
+
+    =================== ==========================================
+    Name                Description
+    =================== ==========================================
+    HW_REG_MODE         Shader writeable mode bits.
+    HW_REG_STATUS       Shader read-only status.
+    HW_REG_TRAPSTS      Trap status.
+    HW_REG_HW_ID        Id of wave, simd, compute unit, etc.
+    HW_REG_GPR_ALLOC    Per-wave SGPR and VGPR allocation.
+    HW_REG_LDS_ALLOC    Per-wave LDS allocation.
+    HW_REG_IB_STS       Counters of outstanding instructions.
+    HW_REG_SH_MEM_BASES Memory aperture.
+    =================== ==========================================
+
+Examples:
+
+.. code-block:: nasm
+
+    s_getreg_b32 s2, 0x6
+    s_getreg_b32 s2, hwreg(15)
+    s_getreg_b32 s2, hwreg(51, 1, 31)
+    s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
+

diff --git a/docs/AMDGPU/gfx9_imm4.rst b/docs/AMDGPU/gfx9_imm4.rst
new file mode 100644 (file)
index 0000000..b1c97fb
--- /dev/null
+++ b/docs/AMDGPU/gfx9_imm4.rst
@@ -0,0 +1,25 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_imm4:
+
+imm4
+===========================
+
+A positive :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 4 bits.
+
+This operand is a mask which controls indexing mode for operands of subsequent instructions. Value 1 enables indexing and value 0 disables it.
+
+    ============ ========================================
+    Bit          Meaning
+    ============ ========================================
+    0            Enables or disables *src0* indexing.
+    1            Enables or disables *src1* indexing.
+    2            Enables or disables *src2* indexing.
+    3            Enables or disables *dst* indexing.
+    ============ ========================================
+

diff --git a/docs/AMDGPU/gfx9_label.rst b/docs/AMDGPU/gfx9_label.rst
new file mode 100644 (file)
index 0000000..09fde5e
--- /dev/null
+++ b/docs/AMDGPU/gfx9_label.rst
@@ -0,0 +1,30 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_label:
+
+label
+===========================
+
+A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
+
+This operand may be specified as:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>`. The number is truncated to 16 bits.
+* An :ref:`absolute_expression<amdgpu_synid_absolute_expression>` which must start with an :ref:`integer_number<amdgpu_synid_integer_number>`. The value of the expression is truncated to 16 bits.
+* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
+
+Examples:
+
+.. code-block:: nasm
+
+  offset = 30
+  s_branch loop_end
+  s_branch 2 + offset
+  s_branch 32
+  loop_end:
+

diff --git a/docs/AMDGPU/gfx9_mad_type_dev.rst b/docs/AMDGPU/gfx9_mad_type_dev.rst
new file mode 100644 (file)
index 0000000..53c78e4
--- /dev/null
+++ b/docs/AMDGPU/gfx9_mad_type_dev.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_mad_type_dev:
+
+fx
+===========================
+
+This is an *f32* or *f16* operand depending on instruction modifiers:
+
+* Operand size is controlled by :ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
+* Location of 16-bit operand is controlled by :ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>`.
+

diff --git a/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst b/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst
new file mode 100644 (file)
index 0000000..ccbad8a
--- /dev/null
+++ b/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_mod_dpp_sdwa_abs_neg:
+
+m
+===========================
+
+This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
+

diff --git a/docs/AMDGPU/gfx9_mod_sdwa_sext.rst b/docs/AMDGPU/gfx9_mod_sdwa_sext.rst
new file mode 100644 (file)
index 0000000..e832097
--- /dev/null
+++ b/docs/AMDGPU/gfx9_mod_sdwa_sext.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_mod_sdwa_sext:
+
+m
+===========================
+
+This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
+

diff --git a/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst b/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst
new file mode 100644 (file)
index 0000000..2dac4b1
--- /dev/null
+++ b/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_mod_vop3_abs_neg:
+
+m
+===========================
+
+This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
+

diff --git a/docs/AMDGPU/gfx9_msg.rst b/docs/AMDGPU/gfx9_msg.rst
new file mode 100644 (file)
index 0000000..41cd7da
--- /dev/null
+++ b/docs/AMDGPU/gfx9_msg.rst
@@ -0,0 +1,72 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_msg:
+
+msg
+===========================
+
+A 16-bit message code. The bits of this operand have the following meaning:
+
+    ============ ======================================================
+    Bits         Description
+    ============ ======================================================
+    3:0          Message *type*.
+    6:4          Optional *operation*.
+    9:7          Optional *parameters*.
+    15:10        Unused.
+    ============ ======================================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below:
+
+    ======================================== ========================================================================
+    Syntax                                   Description
+    ======================================== ========================================================================
+    sendmsg(<*type*>)                        A message identified by its *type*.
+    sendmsg(<*type*>, <*op*>)                A message identified by its *type* and *operation*.
+    sendmsg(<*type*>, <*op*>, <*stream*>)    A message identified by its *type* and *operation* with a stream *id*.
+    ======================================== ========================================================================
+
+*Type* may be specified using message *name* or message *id*.
+
+*Op* may be specified using operation *name* or operation *id*.
+
+Stream *id* is an integer in the range 0..3.
+
+Message *id*, operation *id* and stream *id* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
+
+Each message type supports specific operations:
+
+    ================= ========== ============================== ============ ==========
+    Message name      Message Id Supported Operations           Operation Id Stream Id
+    ================= ========== ============================== ============ ==========
+    MSG_INTERRUPT     1          \-                             \-           \-
+    MSG_GS            2          GS_OP_CUT                      1            Optional
+    \                            GS_OP_EMIT                     2            Optional
+    \                            GS_OP_EMIT_CUT                 3            Optional
+    MSG_GS_DONE       3          GS_OP_NOP                      0            \-
+    \                            GS_OP_CUT                      1            Optional
+    \                            GS_OP_EMIT                     2            Optional
+    \                            GS_OP_EMIT_CUT                 3            Optional
+    MSG_SYSMSG        15         SYSMSG_OP_ECC_ERR_INTERRUPT    1            \-
+    \                            SYSMSG_OP_REG_RD               2            \-
+    \                            SYSMSG_OP_HOST_TRAP_ACK        3            \-
+    \                            SYSMSG_OP_TTRACE_PC            4            \-
+    ================= ========== ============================== ============ ==========
+
+Examples:
+
+.. code-block:: nasm
+
+    s_sendmsg 0x12
+    s_sendmsg sendmsg(MSG_INTERRUPT)
+    s_sendmsg sendmsg(2, GS_OP_CUT)
+    s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
+    s_sendmsg sendmsg(MSG_GS, 2)
+    s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
+    s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)
+

diff --git a/docs/AMDGPU/gfx9_offset_buf.rst b/docs/AMDGPU/gfx9_offset_buf.rst
new file mode 100644 (file)
index 0000000..ec6cc33
--- /dev/null
+++ b/docs/AMDGPU/gfx9_offset_buf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_offset_buf:
+
+soffset
+===========================
+
+An unsigned byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

diff --git a/docs/AMDGPU/gfx9_offset_smem_buf.rst b/docs/AMDGPU/gfx9_offset_smem_buf.rst
new file mode 100644 (file)
index 0000000..fdc4b09
--- /dev/null
+++ b/docs/AMDGPU/gfx9_offset_smem_buf.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_offset_smem_buf:
+
+soffset
+===========================
+
+An unsigned byte offset added to the base address to get memory address.
+
+.. WARNING:: Assembler currently supports 20-bit offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` instead of :ref:`uimm21<amdgpu_synid_uimm21>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm21<amdgpu_synid_uimm21>`

diff --git a/docs/AMDGPU/gfx9_offset_smem_plain.rst b/docs/AMDGPU/gfx9_offset_smem_plain.rst
new file mode 100644 (file)
index 0000000..a58df55
--- /dev/null
+++ b/docs/AMDGPU/gfx9_offset_smem_plain.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_offset_smem_plain:
+
+soffset
+===========================
+
+An offset added to the base address to get memory address.
+
+* If offset is specified as a register, it supplies an unsigned byte offset.
+* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
+
+.. WARNING:: Assembler currently supports 20-bit unsigned offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` instead of :ref:`simm21<amdgpu_synid_simm21>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`

diff --git a/docs/AMDGPU/gfx9_opt.rst b/docs/AMDGPU/gfx9_opt.rst
new file mode 100644 (file)
index 0000000..50d73f9
--- /dev/null
+++ b/docs/AMDGPU/gfx9_opt.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_opt:
+
+opt
+===========================
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+

diff --git a/docs/AMDGPU/gfx9_param.rst b/docs/AMDGPU/gfx9_param.rst
new file mode 100644 (file)
index 0000000..2831a65
--- /dev/null
+++ b/docs/AMDGPU/gfx9_param.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_param:
+
+param
+===========================
+
+Interpolation parameter to read:
+
+    ============ ===================================
+    Syntax       Description
+    ============ ===================================
+    p0           Parameter *P0*.
+    p10          Parameter *P10*.
+    p20          Parameter *P20*.
+    ============ ===================================
+

diff --git a/docs/AMDGPU/gfx9_perm_smem.rst b/docs/AMDGPU/gfx9_perm_smem.rst
new file mode 100644 (file)
index 0000000..370fb0d
--- /dev/null
+++ b/docs/AMDGPU/gfx9_perm_smem.rst
@@ -0,0 +1,24 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_perm_smem:
+
+imm3
+===========================
+
+A bit mask which indicates request permissions.
+
+This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 7 bits, but only 3 low bits are significant.
+
+    ============ ==============================
+    Bit Number   Description
+    ============ ==============================
+    0            Request *read* permission.
+    1            Request *write* permission.
+    2            Request *execute* permission.
+    ============ ==============================
+

diff --git a/docs/AMDGPU/gfx9_ret.rst b/docs/AMDGPU/gfx9_ret.rst
new file mode 100644 (file)
index 0000000..7015be6
--- /dev/null
+++ b/docs/AMDGPU/gfx9_ret.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_ret:
+
+dst
+===========================
+
+This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
+

diff --git a/docs/AMDGPU/gfx9_rsrc_buf.rst b/docs/AMDGPU/gfx9_rsrc_buf.rst
new file mode 100644 (file)
index 0000000..3dc1775
--- /dev/null
+++ b/docs/AMDGPU/gfx9_rsrc_buf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_rsrc_buf:
+
+srsrc
+===========================
+
+Buffer resource constant which defines the address and characteristics of the buffer in memory.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_rsrc_mimg.rst b/docs/AMDGPU/gfx9_rsrc_mimg.rst
new file mode 100644 (file)
index 0000000..29c90a1
--- /dev/null
+++ b/docs/AMDGPU/gfx9_rsrc_mimg.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_rsrc_mimg:
+
+srsrc
+===========================
+
+Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_saddr_flat_global.rst b/docs/AMDGPU/gfx9_saddr_flat_global.rst
new file mode 100644 (file)
index 0000000..7396df0
--- /dev/null
+++ b/docs/AMDGPU/gfx9_saddr_flat_global.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_saddr_flat_global:
+
+saddr
+===========================
+
+An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+See :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` for description of available addressing modes.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`off<amdgpu_synid_off>`

diff --git a/docs/AMDGPU/gfx9_saddr_flat_scratch.rst b/docs/AMDGPU/gfx9_saddr_flat_scratch.rst
new file mode 100644 (file)
index 0000000..5bdbf39
--- /dev/null
+++ b/docs/AMDGPU/gfx9_saddr_flat_scratch.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_saddr_flat_scratch:
+
+saddr
+===========================
+
+An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+Either this operand or :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>` must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`off<amdgpu_synid_off>`

diff --git a/docs/AMDGPU/gfx9_samp_mimg.rst b/docs/AMDGPU/gfx9_samp_mimg.rst
new file mode 100644 (file)
index 0000000..f901142
--- /dev/null
+++ b/docs/AMDGPU/gfx9_samp_mimg.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_samp_mimg:
+
+ssamp
+===========================
+
+Sampler constant used to specify filtering options applied to the image data after it is read.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_sdata128_0.rst b/docs/AMDGPU/gfx9_sdata128_0.rst
new file mode 100644 (file)
index 0000000..d3609d4
--- /dev/null
+++ b/docs/AMDGPU/gfx9_sdata128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_sdata128_0:
+
+sdata
+===========================
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_sdata32_0.rst b/docs/AMDGPU/gfx9_sdata32_0.rst
new file mode 100644 (file)
index 0000000..4de3635
--- /dev/null
+++ b/docs/AMDGPU/gfx9_sdata32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_sdata32_0:
+
+sdata
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_sdata64_0.rst b/docs/AMDGPU/gfx9_sdata64_0.rst
new file mode 100644 (file)
index 0000000..7cde210
--- /dev/null
+++ b/docs/AMDGPU/gfx9_sdata64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_sdata64_0:
+
+sdata
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_sdst128_0.rst b/docs/AMDGPU/gfx9_sdst128_0.rst
new file mode 100644 (file)
index 0000000..974df54
--- /dev/null
+++ b/docs/AMDGPU/gfx9_sdst128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_sdst128_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_sdst256_0.rst b/docs/AMDGPU/gfx9_sdst256_0.rst
new file mode 100644 (file)
index 0000000..b492921
--- /dev/null
+++ b/docs/AMDGPU/gfx9_sdst256_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_sdst256_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_sdst32_0.rst b/docs/AMDGPU/gfx9_sdst32_0.rst
new file mode 100644 (file)
index 0000000..911c843
--- /dev/null
+++ b/docs/AMDGPU/gfx9_sdst32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_sdst32_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_sdst32_1.rst b/docs/AMDGPU/gfx9_sdst32_1.rst
new file mode 100644 (file)
index 0000000..8f63024
--- /dev/null
+++ b/docs/AMDGPU/gfx9_sdst32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_sdst32_1:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`

diff --git a/docs/AMDGPU/gfx9_sdst32_2.rst b/docs/AMDGPU/gfx9_sdst32_2.rst
new file mode 100644 (file)
index 0000000..04f3cda
--- /dev/null
+++ b/docs/AMDGPU/gfx9_sdst32_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_sdst32_2:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_sdst512_0.rst b/docs/AMDGPU/gfx9_sdst512_0.rst
new file mode 100644 (file)
index 0000000..7f7dab6
--- /dev/null
+++ b/docs/AMDGPU/gfx9_sdst512_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_sdst512_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_sdst64_0.rst b/docs/AMDGPU/gfx9_sdst64_0.rst
new file mode 100644 (file)
index 0000000..dc5f4c7
--- /dev/null
+++ b/docs/AMDGPU/gfx9_sdst64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_sdst64_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_sdst64_1.rst b/docs/AMDGPU/gfx9_sdst64_1.rst
new file mode 100644 (file)
index 0000000..208d68b
--- /dev/null
+++ b/docs/AMDGPU/gfx9_sdst64_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_sdst64_1:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`

diff --git a/docs/AMDGPU/gfx9_simm16.rst b/docs/AMDGPU/gfx9_simm16.rst
new file mode 100644 (file)
index 0000000..47b200a
--- /dev/null
+++ b/docs/AMDGPU/gfx9_simm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_simm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then sign-extended to 32 bits.
+

diff --git a/docs/AMDGPU/gfx9_src32_0.rst b/docs/AMDGPU/gfx9_src32_0.rst
new file mode 100644 (file)
index 0000000..288ccbb
--- /dev/null
+++ b/docs/AMDGPU/gfx9_src32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_src32_0:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

diff --git a/docs/AMDGPU/gfx9_src32_1.rst b/docs/AMDGPU/gfx9_src32_1.rst
new file mode 100644 (file)
index 0000000..a06764d
--- /dev/null
+++ b/docs/AMDGPU/gfx9_src32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_src32_1:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

diff --git a/docs/AMDGPU/gfx9_src64_0.rst b/docs/AMDGPU/gfx9_src64_0.rst
new file mode 100644 (file)
index 0000000..f8ef842
--- /dev/null
+++ b/docs/AMDGPU/gfx9_src64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_src64_0:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

diff --git a/docs/AMDGPU/gfx9_src64_1.rst b/docs/AMDGPU/gfx9_src64_1.rst
new file mode 100644 (file)
index 0000000..fe7b7fd
--- /dev/null
+++ b/docs/AMDGPU/gfx9_src64_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_src64_1:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

diff --git a/docs/AMDGPU/gfx9_src_exp.rst b/docs/AMDGPU/gfx9_src_exp.rst
new file mode 100644 (file)
index 0000000..71eaac0
--- /dev/null
+++ b/docs/AMDGPU/gfx9_src_exp.rst
@@ -0,0 +1,28 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_src_exp:
+
+vsrc
+===========================
+
+Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+:ref:`compr<amdgpu_synid_compr>` modifier indicates use of compressed (16-bit) data. This limits number of source operands from 4 to 2:
+
+* src0 and src1 must specify the first register (or :ref:`off<amdgpu_synid_off>`).
+* src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
+
+An example:
+
+.. code-block:: nasm
+
+  exp mrtz v3, v3, off, off compr
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`

diff --git a/docs/AMDGPU/gfx9_ssrc32_0.rst b/docs/AMDGPU/gfx9_ssrc32_0.rst
new file mode 100644 (file)
index 0000000..25d6b37
--- /dev/null
+++ b/docs/AMDGPU/gfx9_ssrc32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_ssrc32_0:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

diff --git a/docs/AMDGPU/gfx9_ssrc32_1.rst b/docs/AMDGPU/gfx9_ssrc32_1.rst
new file mode 100644 (file)
index 0000000..caea764
--- /dev/null
+++ b/docs/AMDGPU/gfx9_ssrc32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_ssrc32_1:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_ssrc32_2.rst b/docs/AMDGPU/gfx9_ssrc32_2.rst
new file mode 100644 (file)
index 0000000..034f20e
--- /dev/null
+++ b/docs/AMDGPU/gfx9_ssrc32_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_ssrc32_2:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`

diff --git a/docs/AMDGPU/gfx9_ssrc32_3.rst b/docs/AMDGPU/gfx9_ssrc32_3.rst
new file mode 100644 (file)
index 0000000..1b08cad
--- /dev/null
+++ b/docs/AMDGPU/gfx9_ssrc32_3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_ssrc32_3:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`

diff --git a/docs/AMDGPU/gfx9_ssrc32_4.rst b/docs/AMDGPU/gfx9_ssrc32_4.rst
new file mode 100644 (file)
index 0000000..7e55427
--- /dev/null
+++ b/docs/AMDGPU/gfx9_ssrc32_4.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_ssrc32_4:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

diff --git a/docs/AMDGPU/gfx9_ssrc64_0.rst b/docs/AMDGPU/gfx9_ssrc64_0.rst
new file mode 100644 (file)
index 0000000..b2f86e1
--- /dev/null
+++ b/docs/AMDGPU/gfx9_ssrc64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_ssrc64_0:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

diff --git a/docs/AMDGPU/gfx9_ssrc64_1.rst b/docs/AMDGPU/gfx9_ssrc64_1.rst
new file mode 100644 (file)
index 0000000..02be6c5
--- /dev/null
+++ b/docs/AMDGPU/gfx9_ssrc64_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_ssrc64_1:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

diff --git a/docs/AMDGPU/gfx9_ssrc64_2.rst b/docs/AMDGPU/gfx9_ssrc64_2.rst
new file mode 100644 (file)
index 0000000..72d2c46
--- /dev/null
+++ b/docs/AMDGPU/gfx9_ssrc64_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_ssrc64_2:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

diff --git a/docs/AMDGPU/gfx9_ssrc64_3.rst b/docs/AMDGPU/gfx9_ssrc64_3.rst
new file mode 100644 (file)
index 0000000..3414802
--- /dev/null
+++ b/docs/AMDGPU/gfx9_ssrc64_3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_ssrc64_3:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`

diff --git a/docs/AMDGPU/gfx9_tgt.rst b/docs/AMDGPU/gfx9_tgt.rst
new file mode 100644 (file)
index 0000000..3ba8bae
--- /dev/null
+++ b/docs/AMDGPU/gfx9_tgt.rst
@@ -0,0 +1,24 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_tgt:
+
+tgt
+===========================
+
+An export target:
+
+    ============== ===================================
+    Syntax         Description
+    ============== ===================================
+    pos{0..3}      Copy vertex position 0..3.
+    param{0..31}   Copy vertex parameter 0..31.
+    mrt{0..7}      Copy pixel color to the MRTs 0..7.
+    mrtz           Copy pixel depth (Z) data.
+    null           Copy nothing.
+    ============== ===================================
+

diff --git a/docs/AMDGPU/gfx9_type_dev.rst b/docs/AMDGPU/gfx9_type_dev.rst
new file mode 100644 (file)
index 0000000..ae2b0bf
--- /dev/null
+++ b/docs/AMDGPU/gfx9_type_dev.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_type_dev:
+
+Type deviation
+===========================
+
+*Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.
+

diff --git a/docs/AMDGPU/gfx9_uimm16.rst b/docs/AMDGPU/gfx9_uimm16.rst
new file mode 100644 (file)
index 0000000..4d1fe1d
--- /dev/null
+++ b/docs/AMDGPU/gfx9_uimm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_uimm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then zero-extended to 32 bits.
+

diff --git a/docs/AMDGPU/gfx9_vaddr_flat_global.rst b/docs/AMDGPU/gfx9_vaddr_flat_global.rst
new file mode 100644 (file)
index 0000000..38beb6c
--- /dev/null
+++ b/docs/AMDGPU/gfx9_vaddr_flat_global.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vaddr_flat_global:
+
+vaddr
+===========================
+
+A 64-bit flat global address or a 32-bit offset depending on addressing mode:
+
+* Address = :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` + :ref:`flat_offset13<amdgpu_synid_flat_offset13>`. :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid9_saddr_flat_global>` set to :ref:`off<amdgpu_synid_off>`.
+* Address = :ref:`saddr<amdgpu_synid9_saddr_flat_global>` + :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` + :ref:`flat_offset13<amdgpu_synid_flat_offset13>`. :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid9_saddr_flat_global>` is not :ref:`off<amdgpu_synid_off>`.
+
+.. WARNING:: Assembler currently expects a 64-bit *vaddr* regardless of addressing mode. This have to be fixed.
+
+*Size:* 1 or 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_vaddr_flat_scratch.rst b/docs/AMDGPU/gfx9_vaddr_flat_scratch.rst
new file mode 100644 (file)
index 0000000..a72cf06
--- /dev/null
+++ b/docs/AMDGPU/gfx9_vaddr_flat_scratch.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vaddr_flat_scratch:
+
+vaddr
+===========================
+
+An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+Either this operand or :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`

diff --git a/docs/AMDGPU/gfx9_vcc_64.rst b/docs/AMDGPU/gfx9_vcc_64.rst
new file mode 100644 (file)
index 0000000..788306b
--- /dev/null
+++ b/docs/AMDGPU/gfx9_vcc_64.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vcc_64:
+
+vcc
+===========================
+
+Vector condition code.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`vcc<amdgpu_synid_vcc>`

diff --git a/docs/AMDGPU/gfx9_vdata128_0.rst b/docs/AMDGPU/gfx9_vdata128_0.rst
new file mode 100644 (file)
index 0000000..3d2b490
--- /dev/null
+++ b/docs/AMDGPU/gfx9_vdata128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vdata128_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_vdata32_0.rst b/docs/AMDGPU/gfx9_vdata32_0.rst
new file mode 100644 (file)
index 0000000..e285769
--- /dev/null
+++ b/docs/AMDGPU/gfx9_vdata32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vdata32_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_vdata64_0.rst b/docs/AMDGPU/gfx9_vdata64_0.rst
new file mode 100644 (file)
index 0000000..fcd1d0f
--- /dev/null
+++ b/docs/AMDGPU/gfx9_vdata64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vdata64_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_vdata96_0.rst b/docs/AMDGPU/gfx9_vdata96_0.rst
new file mode 100644 (file)
index 0000000..8a8cb76
--- /dev/null
+++ b/docs/AMDGPU/gfx9_vdata96_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vdata96_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_vdst128_0.rst b/docs/AMDGPU/gfx9_vdst128_0.rst
new file mode 100644 (file)
index 0000000..b8bbf89
--- /dev/null
+++ b/docs/AMDGPU/gfx9_vdst128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vdst128_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_vdst32_0.rst b/docs/AMDGPU/gfx9_vdst32_0.rst
new file mode 100644 (file)
index 0000000..ccee55f
--- /dev/null
+++ b/docs/AMDGPU/gfx9_vdst32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vdst32_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_vdst64_0.rst b/docs/AMDGPU/gfx9_vdst64_0.rst
new file mode 100644 (file)
index 0000000..60bf384
--- /dev/null
+++ b/docs/AMDGPU/gfx9_vdst64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vdst64_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_vdst96_0.rst b/docs/AMDGPU/gfx9_vdst96_0.rst
new file mode 100644 (file)
index 0000000..834d32a
--- /dev/null
+++ b/docs/AMDGPU/gfx9_vdst96_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vdst96_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_vsrc128_0.rst b/docs/AMDGPU/gfx9_vsrc128_0.rst
new file mode 100644 (file)
index 0000000..3e8c6de
--- /dev/null
+++ b/docs/AMDGPU/gfx9_vsrc128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vsrc128_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_vsrc32_0.rst b/docs/AMDGPU/gfx9_vsrc32_0.rst
new file mode 100644 (file)
index 0000000..a056f3a
--- /dev/null
+++ b/docs/AMDGPU/gfx9_vsrc32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vsrc32_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_vsrc64_0.rst b/docs/AMDGPU/gfx9_vsrc64_0.rst
new file mode 100644 (file)
index 0000000..b91b340
--- /dev/null
+++ b/docs/AMDGPU/gfx9_vsrc64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vsrc64_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

diff --git a/docs/AMDGPU/gfx9_waitcnt.rst b/docs/AMDGPU/gfx9_waitcnt.rst
new file mode 100644 (file)
index 0000000..5f755fc
--- /dev/null
+++ b/docs/AMDGPU/gfx9_waitcnt.rst
@@ -0,0 +1,56 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_waitcnt:
+
+waitcnt
+===========================
+
+Counts of outstanding instructions to wait for.
+
+The bits of this operand have the following meaning:
+
+    ============ ======================================================
+    Bits         Description
+    ============ ======================================================
+    3:0          VM_CNT: vector memory operations count, lower bits.
+    6:4          EXP_CNT: export count.
+    11:8         LGKM_CNT: LDS, GDS, Constant and Message count.
+    15:14        VM_CNT: vector memory operations count, upper bits.
+    ============ ======================================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>`
+or as a combination of the following symbolic helpers:
+
+    ====================== ======================================================================
+    Syntax                 Description
+    ====================== ======================================================================
+    vmcnt(<*N*>)           VM_CNT value. *N* must not exceed the largest VM_CNT value.
+    expcnt(<*N*>)          EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
+    lgkmcnt(<*N*>)         LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
+    vmcnt_sat(<*N*>)       VM_CNT value computed as min(*N*, the largest VM_CNT value).
+    expcnt_sat(<*N*>)      EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
+    lgkmcnt_sat(<*N*>)     LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
+    ====================== ======================================================================
+
+These helpers may be specified in any order. Ampersands and commas may be used as optional separators.
+
+*N* is either an
+:ref:`integer number<amdgpu_synid_integer_number>` or an
+:ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. code-block:: nasm
+
+    s_waitcnt 0
+    s_waitcnt vmcnt(1)
+    s_waitcnt expcnt(2) lgkmcnt(3)
+    s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3)
+    s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
+    s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
+

diff --git a/docs/AMDGPUAsmGFX7.rst b/docs/AMDGPUAsmGFX7.rst
deleted file mode 100644 (file)
index 8973c50..0000000
--- a/docs/AMDGPUAsmGFX7.rst
+++ /dev/null
@@ -1,1255 +0,0 @@
-..
-    **************************************************
-    *                                                *
-    *   Automatically generated file, do not edit!   *
-    *                                                *
-    **************************************************
-
-===========================
-Syntax of GFX7 Instructions
-===========================
-
-.. contents::
-  :local:
-
-
-DS
-===========================
-
-.. parsed-literal::
-
-    ds_add_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_b32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_b64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_rtn_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_rtn_b64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_src2_b32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_src2_b64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_append                      dst                            :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_b32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_b64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_f32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_f64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_rtn_b32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_rtn_b64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_rtn_f32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_rtn_f64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_condxchg32_rtn_b64          dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_consume                     dst                            :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_barrier                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_init                    src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_sema_br                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_sema_p                  src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_sema_release_all        src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_sema_v                  src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_f64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_i32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_i64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_f64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_i32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_i64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_f32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_f64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_i32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_i64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_f64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_i32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_i64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_f64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_i32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_i64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_f32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_f64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_i32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_i64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_mskor_b32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_mskor_b64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_mskor_rtn_b32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_mskor_rtn_b64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_nop                         src0
-    ds_or_b32                      src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_b64                      src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_rtn_b32                  dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_rtn_b64                  dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_src2_b32                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_src2_b64                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_ordered_count               dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read2_b32                   dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read2_b64                   dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read2st64_b32               dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read2st64_b64               dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_b128                   dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_b32                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_b64                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_b96                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_i16                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_i8                     dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_u16                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_u8                     dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_rtn_u32                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_rtn_u64                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_src2_u32               src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_src2_u64               src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_u32                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_u64                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_swizzle_b32                 dst, src0                      :ref:`sw_offset16<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrap_rtn_b32                dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write2_b32                  src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write2_b64                  src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write2st64_b32              src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write2st64_b64              src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b128                  src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b16                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b32                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b64                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b8                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b96                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_src2_b32              src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_src2_b64              src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg2_rtn_b32             dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg2_rtn_b64             dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg2st64_rtn_b32         dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg2st64_rtn_b64         dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg_rtn_b32              dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg_rtn_b64              dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_b32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_b64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_rtn_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_rtn_b64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_src2_b32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_src2_b64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-
-EXP
-===========================
-
-.. parsed-literal::
-
-    exp                            dst, src0, src1, src2, src3    :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
-
-FLAT
-===========================
-
-.. parsed-literal::
-
-    flat_atomic_add                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_add_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_and                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_and_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_cmpswap            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_cmpswap_x2         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_dec                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_dec_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_fcmpswap           dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_fcmpswap_x2        dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_fmax               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_fmax_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_fmin               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_fmin_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_inc                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_inc_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_or                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_or_x2              dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_smax               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_smax_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_smin               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_smin_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_sub                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_sub_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_swap               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_swap_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_umax               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_umax_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_umin               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_umin_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_xor                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_xor_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_dword                dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_dwordx2              dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_dwordx3              dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_dwordx4              dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_sbyte                dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_sshort               dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_ubyte                dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_ushort               dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_byte                src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_dword               src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_dwordx2             src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_dwordx3             src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_dwordx4             src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_short               src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-
-MIMG
-===========================
-
-.. parsed-literal::
-
-    image_atomic_add               src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_and               src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_cmpswap           src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_dec               src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_inc               src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_or                src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_smax              src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_smin              src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_sub               src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_swap              src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_umax              src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_umin              src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_xor               src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4                  dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_b                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_b_cl             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_b_cl_o           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_b_o              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_b              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_b_cl           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_b_cl_o         dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_b_o            dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_cl             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_cl_o           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_l              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_l_o            dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_lz             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_lz_o           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_o              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_cl               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_cl_o             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_l                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_l_o              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_lz               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_lz_o             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_o                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_get_lod                  dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_get_resinfo              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load                     dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_mip                 dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_mip_pck             dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_mip_pck_sgn         dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_pck                 dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_pck_sgn             dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample                   dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_b                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_b_cl              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_b               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_b_cl            dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_cd              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_cl              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_d               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_l               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_lz              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_cl                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_l                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_lz                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_store                    src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_store_mip                src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_store_mip_pck            src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_store_pck                src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-
-MUBUF
-===========================
-
-.. parsed-literal::
-
-    buffer_atomic_add              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_add_x2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_and              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_and_x2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_cmpswap          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_cmpswap_x2       src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_dec              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_dec_x2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_inc              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_inc_x2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_or               src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_or_x2            src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smax             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smax_x2          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smin             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smin_x2          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_sub              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_sub_x2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_swap             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_swap_x2          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umax             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umax_x2          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umin             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umin_x2          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_xor              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_xor_x2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_dword              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_dwordx2            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_dwordx3            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_dwordx4            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_x           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_format_xy          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_xyz         dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_xyzw        dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_sbyte              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_sshort             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_ubyte              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_ushort             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_store_byte              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dword             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dwordx2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dwordx3           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dwordx4           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_x          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_xy         src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_xyz        src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_xyzw       src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_short             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_wbinvl1
-    buffer_wbinvl1_vol
-
-SMRD
-===========================
-
-.. parsed-literal::
-
-    s_buffer_load_dword            dst, src0, src1
-    s_buffer_load_dwordx16         dst, src0, src1
-    s_buffer_load_dwordx2          dst, src0, src1
-    s_buffer_load_dwordx4          dst, src0, src1
-    s_buffer_load_dwordx8          dst, src0, src1
-    s_dcache_inv
-    s_dcache_inv_vol
-    s_load_dword                   dst, src0, src1
-    s_load_dwordx16                dst, src0, src1
-    s_load_dwordx2                 dst, src0, src1
-    s_load_dwordx4                 dst, src0, src1
-    s_load_dwordx8                 dst, src0, src1
-    s_memtime                      dst
-
-SOP1
-===========================
-
-.. parsed-literal::
-
-    s_abs_i32                      dst, src0
-    s_and_saveexec_b64             dst, src0
-    s_andn2_saveexec_b64           dst, src0
-    s_bcnt0_i32_b32                dst, src0
-    s_bcnt0_i32_b64                dst, src0
-    s_bcnt1_i32_b32                dst, src0
-    s_bcnt1_i32_b64                dst, src0
-    s_bitset0_b32                  dst, src0
-    s_bitset0_b64                  dst, src0
-    s_bitset1_b32                  dst, src0
-    s_bitset1_b64                  dst, src0
-    s_brev_b32                     dst, src0
-    s_brev_b64                     dst, src0
-    s_cbranch_join                 src0
-    s_cmov_b32                     dst, src0
-    s_cmov_b64                     dst, src0
-    s_ff0_i32_b32                  dst, src0
-    s_ff0_i32_b64                  dst, src0
-    s_ff1_i32_b32                  dst, src0
-    s_ff1_i32_b64                  dst, src0
-    s_flbit_i32                    dst, src0
-    s_flbit_i32_b32                dst, src0
-    s_flbit_i32_b64                dst, src0
-    s_flbit_i32_i64                dst, src0
-    s_getpc_b64                    dst
-    s_mov_b32                      dst, src0
-    s_mov_b64                      dst, src0
-    s_mov_fed_b32                  dst, src0
-    s_movreld_b32                  dst, src0
-    s_movreld_b64                  dst, src0
-    s_movrels_b32                  dst, src0
-    s_movrels_b64                  dst, src0
-    s_nand_saveexec_b64            dst, src0
-    s_nor_saveexec_b64             dst, src0
-    s_not_b32                      dst, src0
-    s_not_b64                      dst, src0
-    s_or_saveexec_b64              dst, src0
-    s_orn2_saveexec_b64            dst, src0
-    s_quadmask_b32                 dst, src0
-    s_quadmask_b64                 dst, src0
-    s_rfe_b64                      src0
-    s_setpc_b64                    src0
-    s_sext_i32_i16                 dst, src0
-    s_sext_i32_i8                  dst, src0
-    s_swappc_b64                   dst, src0
-    s_wqm_b32                      dst, src0
-    s_wqm_b64                      dst, src0
-    s_xnor_saveexec_b64            dst, src0
-    s_xor_saveexec_b64             dst, src0
-
-SOP2
-===========================
-
-.. parsed-literal::
-
-    s_absdiff_i32                  dst, src0, src1
-    s_add_i32                      dst, src0, src1
-    s_add_u32                      dst, src0, src1
-    s_addc_u32                     dst, src0, src1
-    s_and_b32                      dst, src0, src1
-    s_and_b64                      dst, src0, src1
-    s_andn2_b32                    dst, src0, src1
-    s_andn2_b64                    dst, src0, src1
-    s_ashr_i32                     dst, src0, src1
-    s_ashr_i64                     dst, src0, src1
-    s_bfe_i32                      dst, src0, src1
-    s_bfe_i64                      dst, src0, src1
-    s_bfe_u32                      dst, src0, src1
-    s_bfe_u64                      dst, src0, src1
-    s_bfm_b32                      dst, src0, src1
-    s_bfm_b64                      dst, src0, src1
-    s_cbranch_g_fork               src0, src1
-    s_cselect_b32                  dst, src0, src1
-    s_cselect_b64                  dst, src0, src1
-    s_lshl_b32                     dst, src0, src1
-    s_lshl_b64                     dst, src0, src1
-    s_lshr_b32                     dst, src0, src1
-    s_lshr_b64                     dst, src0, src1
-    s_max_i32                      dst, src0, src1
-    s_max_u32                      dst, src0, src1
-    s_min_i32                      dst, src0, src1
-    s_min_u32                      dst, src0, src1
-    s_mul_i32                      dst, src0, src1
-    s_nand_b32                     dst, src0, src1
-    s_nand_b64                     dst, src0, src1
-    s_nor_b32                      dst, src0, src1
-    s_nor_b64                      dst, src0, src1
-    s_or_b32                       dst, src0, src1
-    s_or_b64                       dst, src0, src1
-    s_orn2_b32                     dst, src0, src1
-    s_orn2_b64                     dst, src0, src1
-    s_sub_i32                      dst, src0, src1
-    s_sub_u32                      dst, src0, src1
-    s_subb_u32                     dst, src0, src1
-    s_xnor_b32                     dst, src0, src1
-    s_xnor_b64                     dst, src0, src1
-    s_xor_b32                      dst, src0, src1
-    s_xor_b64                      dst, src0, src1
-
-SOPC
-===========================
-
-.. parsed-literal::
-
-    s_bitcmp0_b32                  src0, src1
-    s_bitcmp0_b64                  src0, src1
-    s_bitcmp1_b32                  src0, src1
-    s_bitcmp1_b64                  src0, src1
-    s_cmp_eq_i32                   src0, src1
-    s_cmp_eq_u32                   src0, src1
-    s_cmp_ge_i32                   src0, src1
-    s_cmp_ge_u32                   src0, src1
-    s_cmp_gt_i32                   src0, src1
-    s_cmp_gt_u32                   src0, src1
-    s_cmp_le_i32                   src0, src1
-    s_cmp_le_u32                   src0, src1
-    s_cmp_lg_i32                   src0, src1
-    s_cmp_lg_u32                   src0, src1
-    s_cmp_lt_i32                   src0, src1
-    s_cmp_lt_u32                   src0, src1
-    s_setvskip                     src0, src1
-
-SOPK
-===========================
-
-.. parsed-literal::
-
-    s_addk_i32                     dst, src0
-    s_cbranch_i_fork               src0, src1
-    s_cmovk_i32                    dst, src0
-    s_cmpk_eq_i32                  src0, src1
-    s_cmpk_eq_u32                  src0, src1
-    s_cmpk_ge_i32                  src0, src1
-    s_cmpk_ge_u32                  src0, src1
-    s_cmpk_gt_i32                  src0, src1
-    s_cmpk_gt_u32                  src0, src1
-    s_cmpk_le_i32                  src0, src1
-    s_cmpk_le_u32                  src0, src1
-    s_cmpk_lg_i32                  src0, src1
-    s_cmpk_lg_u32                  src0, src1
-    s_cmpk_lt_i32                  src0, src1
-    s_cmpk_lt_u32                  src0, src1
-    s_getreg_b32                   dst, src0
-    s_movk_i32                     dst, src0
-    s_mulk_i32                     dst, src0
-    s_setreg_b32                   dst, src0
-    s_setreg_imm32_b32             dst, src0
-
-SOPP
-===========================
-
-.. parsed-literal::
-
-    s_barrier
-    s_branch                       src0
-    s_cbranch_cdbgsys              src0
-    s_cbranch_cdbgsys_and_user     src0
-    s_cbranch_cdbgsys_or_user      src0
-    s_cbranch_cdbguser             src0
-    s_cbranch_execnz               src0
-    s_cbranch_execz                src0
-    s_cbranch_scc0                 src0
-    s_cbranch_scc1                 src0
-    s_cbranch_vccnz                src0
-    s_cbranch_vccz                 src0
-    s_decperflevel                 src0
-    s_endpgm
-    s_icache_inv
-    s_incperflevel                 src0
-    s_nop                          src0
-    s_sendmsg                      src0
-    s_sendmsghalt                  src0
-    s_sethalt                      src0
-    s_setkill                      src0
-    s_setprio                      src0
-    s_sleep                        src0
-    s_trap                         src0
-    s_ttracedata
-    s_waitcnt                      src0
-
-VINTRP
-===========================
-
-.. parsed-literal::
-
-    v_interp_mov_f32               dst, src0, src1
-    v_interp_p1_f32                dst, src0, src1
-    v_interp_p2_f32                dst, src0, src1
-
-VOP1
-===========================
-
-.. parsed-literal::
-
-    v_bfrev_b32                    dst, src0
-    v_ceil_f32                     dst, src0
-    v_ceil_f64                     dst, src0
-    v_clrexcp
-    v_cos_f32                      dst, src0
-    v_cvt_f16_f32                  dst, src0
-    v_cvt_f32_f16                  dst, src0
-    v_cvt_f32_f64                  dst, src0
-    v_cvt_f32_i32                  dst, src0
-    v_cvt_f32_u32                  dst, src0
-    v_cvt_f32_ubyte0               dst, src0
-    v_cvt_f32_ubyte1               dst, src0
-    v_cvt_f32_ubyte2               dst, src0
-    v_cvt_f32_ubyte3               dst, src0
-    v_cvt_f64_f32                  dst, src0
-    v_cvt_f64_i32                  dst, src0
-    v_cvt_f64_u32                  dst, src0
-    v_cvt_flr_i32_f32              dst, src0
-    v_cvt_i32_f32                  dst, src0
-    v_cvt_i32_f64                  dst, src0
-    v_cvt_off_f32_i4               dst, src0
-    v_cvt_rpi_i32_f32              dst, src0
-    v_cvt_u32_f32                  dst, src0
-    v_cvt_u32_f64                  dst, src0
-    v_exp_f32                      dst, src0
-    v_exp_legacy_f32               dst, src0
-    v_ffbh_i32                     dst, src0
-    v_ffbh_u32                     dst, src0
-    v_ffbl_b32                     dst, src0
-    v_floor_f32                    dst, src0
-    v_floor_f64                    dst, src0
-    v_fract_f32                    dst, src0
-    v_fract_f64                    dst, src0
-    v_frexp_exp_i32_f32            dst, src0
-    v_frexp_exp_i32_f64            dst, src0
-    v_frexp_mant_f32               dst, src0
-    v_frexp_mant_f64               dst, src0
-    v_log_clamp_f32                dst, src0
-    v_log_f32                      dst, src0
-    v_log_legacy_f32               dst, src0
-    v_mov_b32                      dst, src0
-    v_mov_fed_b32                  dst, src0
-    v_movreld_b32                  dst, src0
-    v_movrels_b32                  dst, src0
-    v_movrelsd_b32                 dst, src0
-    v_nop
-    v_not_b32                      dst, src0
-    v_rcp_clamp_f32                dst, src0
-    v_rcp_clamp_f64                dst, src0
-    v_rcp_f32                      dst, src0
-    v_rcp_f64                      dst, src0
-    v_rcp_iflag_f32                dst, src0
-    v_rcp_legacy_f32               dst, src0
-    v_readfirstlane_b32            dst, src0
-    v_rndne_f32                    dst, src0
-    v_rndne_f64                    dst, src0
-    v_rsq_clamp_f32                dst, src0
-    v_rsq_clamp_f64                dst, src0
-    v_rsq_f32                      dst, src0
-    v_rsq_f64                      dst, src0
-    v_rsq_legacy_f32               dst, src0
-    v_sin_f32                      dst, src0
-    v_sqrt_f32                     dst, src0
-    v_sqrt_f64                     dst, src0
-    v_trunc_f32                    dst, src0
-    v_trunc_f64                    dst, src0
-
-VOP2
-===========================
-
-.. parsed-literal::
-
-    v_add_f32                      dst, src0, src1
-    v_add_i32                      dst0, dst1, src0, src1
-    v_addc_u32                     dst0, dst1, src0, src1, src2
-    v_and_b32                      dst, src0, src1
-    v_ashr_i32                     dst, src0, src1
-    v_ashrrev_i32                  dst, src0, src1
-    v_bcnt_u32_b32                 dst, src0, src1
-    v_bfm_b32                      dst, src0, src1
-    v_cndmask_b32                  dst, src0, src1, src2
-    v_cvt_pk_i16_i32               dst, src0, src1
-    v_cvt_pk_u16_u32               dst, src0, src1
-    v_cvt_pkaccum_u8_f32           dst, src0, src1
-    v_cvt_pknorm_i16_f32           dst, src0, src1
-    v_cvt_pknorm_u16_f32           dst, src0, src1
-    v_cvt_pkrtz_f16_f32            dst, src0, src1
-    v_ldexp_f32                    dst, src0, src1
-    v_lshl_b32                     dst, src0, src1
-    v_lshlrev_b32                  dst, src0, src1
-    v_lshr_b32                     dst, src0, src1
-    v_lshrrev_b32                  dst, src0, src1
-    v_mac_f32                      dst, src0, src1
-    v_mac_legacy_f32               dst, src0, src1
-    v_madak_f32                    dst, src0, src1, src2
-    v_madmk_f32                    dst, src0, src1, src2
-    v_max_f32                      dst, src0, src1
-    v_max_i32                      dst, src0, src1
-    v_max_legacy_f32               dst, src0, src1
-    v_max_u32                      dst, src0, src1
-    v_mbcnt_hi_u32_b32             dst, src0, src1
-    v_mbcnt_lo_u32_b32             dst, src0, src1
-    v_min_f32                      dst, src0, src1
-    v_min_i32                      dst, src0, src1
-    v_min_legacy_f32               dst, src0, src1
-    v_min_u32                      dst, src0, src1
-    v_mul_f32                      dst, src0, src1
-    v_mul_hi_i32_i24               dst, src0, src1
-    v_mul_hi_u32_u24               dst, src0, src1
-    v_mul_i32_i24                  dst, src0, src1
-    v_mul_legacy_f32               dst, src0, src1
-    v_mul_u32_u24                  dst, src0, src1
-    v_or_b32                       dst, src0, src1
-    v_readlane_b32                 dst, src0, src1
-    v_sub_f32                      dst, src0, src1
-    v_sub_i32                      dst0, dst1, src0, src1
-    v_subb_u32                     dst0, dst1, src0, src1, src2
-    v_subbrev_u32                  dst0, dst1, src0, src1, src2
-    v_subrev_f32                   dst, src0, src1
-    v_subrev_i32                   dst0, dst1, src0, src1
-    v_writelane_b32                dst, src0, src1
-    v_xor_b32                      dst, src0, src1
-
-VOP3
-===========================
-
-.. parsed-literal::
-
-    v_add_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_i32_e64                  dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
-    v_addc_u32_e64                 dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_alignbit_b32                 dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_alignbyte_b32                dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_and_b32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_ashr_i32_e64                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_ashr_i64                     dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_ashrrev_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_bcnt_u32_b32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_bfe_i32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_bfe_u32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_bfi_b32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_bfm_b32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_bfrev_b32_e64                dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_ceil_f32_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ceil_f64_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_clrexcp_e64                                                 :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_class_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_class_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_f32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_f64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_i32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_i64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_u32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_u64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lg_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lg_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_neq_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_neq_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nge_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nge_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ngt_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ngt_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nle_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nle_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlg_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlg_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlt_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlt_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_o_f32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_o_f64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_i32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_i64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_u32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_u64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_tru_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_tru_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_u_f32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_u_f64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_eq_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_eq_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_f_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_f_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_ge_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_ge_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_gt_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_gt_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_le_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_le_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_lg_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_lg_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_lt_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_lt_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_neq_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_neq_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_nge_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_nge_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_ngt_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_ngt_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_nle_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_nle_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_nlg_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_nlg_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_nlt_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_nlt_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_o_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_o_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_tru_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_tru_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_u_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmps_u_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_eq_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_eq_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_f_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_f_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_ge_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_ge_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_gt_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_gt_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_le_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_le_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_lg_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_lg_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_lt_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_lt_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_neq_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_neq_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_nge_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_nge_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_ngt_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_ngt_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_nle_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_nle_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_nlg_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_nlg_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_nlt_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_nlt_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_o_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_o_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_tru_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_tru_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_u_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpsx_u_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_class_f32_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_class_f64_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lg_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lg_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_neq_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_neq_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nge_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nge_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ngt_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ngt_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nle_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nle_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlg_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlg_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlt_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlt_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_o_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_o_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_tru_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_tru_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_u_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_u_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cndmask_b32_e64              dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_cos_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubeid_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubema_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubesc_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubetc_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_f32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_f16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_f64_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_i32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_u32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte0_e64           dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte1_e64           dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte2_e64           dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte3_e64           dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_f32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_i32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_u32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_flr_i32_f32_e64          dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_i32_f32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_i32_f64_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_off_f32_i4_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_i16_i32_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_u16_u32_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_u8_f32                dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pkaccum_u8_f32_e64       dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pknorm_i16_f32_e64       dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pknorm_u16_f32_e64       dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pkrtz_f16_f32_e64        dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_rpi_i32_f32_e64          dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_u32_f32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_u32_f64_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_div_fixup_f32                dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fixup_f64                dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fmas_f32                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fmas_f64                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_scale_f32                dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_div_scale_f64                dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_exp_f32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_exp_legacy_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ffbh_i32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_ffbh_u32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_ffbl_b32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_floor_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_floor_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_f32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_f64                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fract_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fract_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_exp_i32_f32_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_exp_i32_f64_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_mant_f32_e64           dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_mant_f64_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f64                    dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lerp_u8                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_log_clamp_f32_e64            dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_log_f32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_log_legacy_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lshl_b32_e64                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshl_b64                     dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshlrev_b32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshr_b32_e64                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshr_b64                     dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshrrev_b32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mac_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mac_legacy_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_f32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i32_i24                  dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i64_i32                  dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_mad_legacy_f32               dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_u32_u24                  dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_mad_u64_u32                  dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_max3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_max3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_max_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_i32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_max_legacy_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mbcnt_hi_u32_b32_e64         dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mbcnt_lo_u32_b32_e64         dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_med3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_med3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_med3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_min3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_min3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_min_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_i32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_min_legacy_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mov_b32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_mov_fed_b32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_movreld_b32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_movrels_b32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_movrelsd_b32_e64             dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_mqsad_pk_u16_u8              dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_mqsad_u32_u8                 dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_msad_u8                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_mul_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_i32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_i32_i24_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_u32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_u32_u24_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_i32_i24_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_legacy_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_lo_i32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_lo_u32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_u32_u24_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mullit_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_nop_e64                                                     :ref:`omod<amdgpu_synid_omod>`
-    v_not_b32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_or_b32_e64                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_qsad_pk_u16_u8               dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_clamp_f32_e64            dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_clamp_f64_e64            dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_f32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_f64_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_iflag_f32_e64            dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_legacy_f32_e64           dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_rndne_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rndne_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_clamp_f32_e64            dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_clamp_f64_e64            dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_f64_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_legacy_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_hi_u8                    dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_sad_u16                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_sad_u32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_sad_u8                       dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_sin_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sqrt_f32_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sqrt_f64_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_i32_e64                  dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
-    v_subb_u32_e64                 dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_subbrev_u32_e64              dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_i32_e64               dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
-    v_trig_preop_f64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_trunc_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_trunc_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_xor_b32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-
-VOPC
-===========================
-
-.. parsed-literal::
-
-    v_cmp_class_f32                dst, src0, src1
-    v_cmp_class_f64                dst, src0, src1
-    v_cmp_eq_f32                   dst, src0, src1
-    v_cmp_eq_f64                   dst, src0, src1
-    v_cmp_eq_i32                   dst, src0, src1
-    v_cmp_eq_i64                   dst, src0, src1
-    v_cmp_eq_u32                   dst, src0, src1
-    v_cmp_eq_u64                   dst, src0, src1
-    v_cmp_f_f32                    dst, src0, src1
-    v_cmp_f_f64                    dst, src0, src1
-    v_cmp_f_i32                    dst, src0, src1
-    v_cmp_f_i64                    dst, src0, src1
-    v_cmp_f_u32                    dst, src0, src1
-    v_cmp_f_u64                    dst, src0, src1
-    v_cmp_ge_f32                   dst, src0, src1
-    v_cmp_ge_f64                   dst, src0, src1
-    v_cmp_ge_i32                   dst, src0, src1
-    v_cmp_ge_i64                   dst, src0, src1
-    v_cmp_ge_u32                   dst, src0, src1
-    v_cmp_ge_u64                   dst, src0, src1
-    v_cmp_gt_f32                   dst, src0, src1
-    v_cmp_gt_f64                   dst, src0, src1
-    v_cmp_gt_i32                   dst, src0, src1
-    v_cmp_gt_i64                   dst, src0, src1
-    v_cmp_gt_u32                   dst, src0, src1
-    v_cmp_gt_u64                   dst, src0, src1
-    v_cmp_le_f32                   dst, src0, src1
-    v_cmp_le_f64                   dst, src0, src1
-    v_cmp_le_i32                   dst, src0, src1
-    v_cmp_le_i64                   dst, src0, src1
-    v_cmp_le_u32                   dst, src0, src1
-    v_cmp_le_u64                   dst, src0, src1
-    v_cmp_lg_f32                   dst, src0, src1
-    v_cmp_lg_f64                   dst, src0, src1
-    v_cmp_lt_f32                   dst, src0, src1
-    v_cmp_lt_f64                   dst, src0, src1
-    v_cmp_lt_i32                   dst, src0, src1
-    v_cmp_lt_i64                   dst, src0, src1
-    v_cmp_lt_u32                   dst, src0, src1
-    v_cmp_lt_u64                   dst, src0, src1
-    v_cmp_ne_i32                   dst, src0, src1
-    v_cmp_ne_i64                   dst, src0, src1
-    v_cmp_ne_u32                   dst, src0, src1
-    v_cmp_ne_u64                   dst, src0, src1
-    v_cmp_neq_f32                  dst, src0, src1
-    v_cmp_neq_f64                  dst, src0, src1
-    v_cmp_nge_f32                  dst, src0, src1
-    v_cmp_nge_f64                  dst, src0, src1
-    v_cmp_ngt_f32                  dst, src0, src1
-    v_cmp_ngt_f64                  dst, src0, src1
-    v_cmp_nle_f32                  dst, src0, src1
-    v_cmp_nle_f64                  dst, src0, src1
-    v_cmp_nlg_f32                  dst, src0, src1
-    v_cmp_nlg_f64                  dst, src0, src1
-    v_cmp_nlt_f32                  dst, src0, src1
-    v_cmp_nlt_f64                  dst, src0, src1
-    v_cmp_o_f32                    dst, src0, src1
-    v_cmp_o_f64                    dst, src0, src1
-    v_cmp_t_i32                    dst, src0, src1
-    v_cmp_t_i64                    dst, src0, src1
-    v_cmp_t_u32                    dst, src0, src1
-    v_cmp_t_u64                    dst, src0, src1
-    v_cmp_tru_f32                  dst, src0, src1
-    v_cmp_tru_f64                  dst, src0, src1
-    v_cmp_u_f32                    dst, src0, src1
-    v_cmp_u_f64                    dst, src0, src1
-    v_cmps_eq_f32                  dst, src0, src1
-    v_cmps_eq_f64                  dst, src0, src1
-    v_cmps_f_f32                   dst, src0, src1
-    v_cmps_f_f64                   dst, src0, src1
-    v_cmps_ge_f32                  dst, src0, src1
-    v_cmps_ge_f64                  dst, src0, src1
-    v_cmps_gt_f32                  dst, src0, src1
-    v_cmps_gt_f64                  dst, src0, src1
-    v_cmps_le_f32                  dst, src0, src1
-    v_cmps_le_f64                  dst, src0, src1
-    v_cmps_lg_f32                  dst, src0, src1
-    v_cmps_lg_f64                  dst, src0, src1
-    v_cmps_lt_f32                  dst, src0, src1
-    v_cmps_lt_f64                  dst, src0, src1
-    v_cmps_neq_f32                 dst, src0, src1
-    v_cmps_neq_f64                 dst, src0, src1
-    v_cmps_nge_f32                 dst, src0, src1
-    v_cmps_nge_f64                 dst, src0, src1
-    v_cmps_ngt_f32                 dst, src0, src1
-    v_cmps_ngt_f64                 dst, src0, src1
-    v_cmps_nle_f32                 dst, src0, src1
-    v_cmps_nle_f64                 dst, src0, src1
-    v_cmps_nlg_f32                 dst, src0, src1
-    v_cmps_nlg_f64                 dst, src0, src1
-    v_cmps_nlt_f32                 dst, src0, src1
-    v_cmps_nlt_f64                 dst, src0, src1
-    v_cmps_o_f32                   dst, src0, src1
-    v_cmps_o_f64                   dst, src0, src1
-    v_cmps_tru_f32                 dst, src0, src1
-    v_cmps_tru_f64                 dst, src0, src1
-    v_cmps_u_f32                   dst, src0, src1
-    v_cmps_u_f64                   dst, src0, src1
-    v_cmpsx_eq_f32                 dst, src0, src1
-    v_cmpsx_eq_f64                 dst, src0, src1
-    v_cmpsx_f_f32                  dst, src0, src1
-    v_cmpsx_f_f64                  dst, src0, src1
-    v_cmpsx_ge_f32                 dst, src0, src1
-    v_cmpsx_ge_f64                 dst, src0, src1
-    v_cmpsx_gt_f32                 dst, src0, src1
-    v_cmpsx_gt_f64                 dst, src0, src1
-    v_cmpsx_le_f32                 dst, src0, src1
-    v_cmpsx_le_f64                 dst, src0, src1
-    v_cmpsx_lg_f32                 dst, src0, src1
-    v_cmpsx_lg_f64                 dst, src0, src1
-    v_cmpsx_lt_f32                 dst, src0, src1
-    v_cmpsx_lt_f64                 dst, src0, src1
-    v_cmpsx_neq_f32                dst, src0, src1
-    v_cmpsx_neq_f64                dst, src0, src1
-    v_cmpsx_nge_f32                dst, src0, src1
-    v_cmpsx_nge_f64                dst, src0, src1
-    v_cmpsx_ngt_f32                dst, src0, src1
-    v_cmpsx_ngt_f64                dst, src0, src1
-    v_cmpsx_nle_f32                dst, src0, src1
-    v_cmpsx_nle_f64                dst, src0, src1
-    v_cmpsx_nlg_f32                dst, src0, src1
-    v_cmpsx_nlg_f64                dst, src0, src1
-    v_cmpsx_nlt_f32                dst, src0, src1
-    v_cmpsx_nlt_f64                dst, src0, src1
-    v_cmpsx_o_f32                  dst, src0, src1
-    v_cmpsx_o_f64                  dst, src0, src1
-    v_cmpsx_tru_f32                dst, src0, src1
-    v_cmpsx_tru_f64                dst, src0, src1
-    v_cmpsx_u_f32                  dst, src0, src1
-    v_cmpsx_u_f64                  dst, src0, src1
-    v_cmpx_class_f32               dst, src0, src1
-    v_cmpx_class_f64               dst, src0, src1
-    v_cmpx_eq_f32                  dst, src0, src1
-    v_cmpx_eq_f64                  dst, src0, src1
-    v_cmpx_eq_i32                  dst, src0, src1
-    v_cmpx_eq_i64                  dst, src0, src1
-    v_cmpx_eq_u32                  dst, src0, src1
-    v_cmpx_eq_u64                  dst, src0, src1
-    v_cmpx_f_f32                   dst, src0, src1
-    v_cmpx_f_f64                   dst, src0, src1
-    v_cmpx_f_i32                   dst, src0, src1
-    v_cmpx_f_i64                   dst, src0, src1
-    v_cmpx_f_u32                   dst, src0, src1
-    v_cmpx_f_u64                   dst, src0, src1
-    v_cmpx_ge_f32                  dst, src0, src1
-    v_cmpx_ge_f64                  dst, src0, src1
-    v_cmpx_ge_i32                  dst, src0, src1
-    v_cmpx_ge_i64                  dst, src0, src1
-    v_cmpx_ge_u32                  dst, src0, src1
-    v_cmpx_ge_u64                  dst, src0, src1
-    v_cmpx_gt_f32                  dst, src0, src1
-    v_cmpx_gt_f64                  dst, src0, src1
-    v_cmpx_gt_i32                  dst, src0, src1
-    v_cmpx_gt_i64                  dst, src0, src1
-    v_cmpx_gt_u32                  dst, src0, src1
-    v_cmpx_gt_u64                  dst, src0, src1
-    v_cmpx_le_f32                  dst, src0, src1
-    v_cmpx_le_f64                  dst, src0, src1
-    v_cmpx_le_i32                  dst, src0, src1
-    v_cmpx_le_i64                  dst, src0, src1
-    v_cmpx_le_u32                  dst, src0, src1
-    v_cmpx_le_u64                  dst, src0, src1
-    v_cmpx_lg_f32                  dst, src0, src1
-    v_cmpx_lg_f64                  dst, src0, src1
-    v_cmpx_lt_f32                  dst, src0, src1
-    v_cmpx_lt_f64                  dst, src0, src1
-    v_cmpx_lt_i32                  dst, src0, src1
-    v_cmpx_lt_i64                  dst, src0, src1
-    v_cmpx_lt_u32                  dst, src0, src1
-    v_cmpx_lt_u64                  dst, src0, src1
-    v_cmpx_ne_i32                  dst, src0, src1
-    v_cmpx_ne_i64                  dst, src0, src1
-    v_cmpx_ne_u32                  dst, src0, src1
-    v_cmpx_ne_u64                  dst, src0, src1
-    v_cmpx_neq_f32                 dst, src0, src1
-    v_cmpx_neq_f64                 dst, src0, src1
-    v_cmpx_nge_f32                 dst, src0, src1
-    v_cmpx_nge_f64                 dst, src0, src1
-    v_cmpx_ngt_f32                 dst, src0, src1
-    v_cmpx_ngt_f64                 dst, src0, src1
-    v_cmpx_nle_f32                 dst, src0, src1
-    v_cmpx_nle_f64                 dst, src0, src1
-    v_cmpx_nlg_f32                 dst, src0, src1
-    v_cmpx_nlg_f64                 dst, src0, src1
-    v_cmpx_nlt_f32                 dst, src0, src1
-    v_cmpx_nlt_f64                 dst, src0, src1
-    v_cmpx_o_f32                   dst, src0, src1
-    v_cmpx_o_f64                   dst, src0, src1
-    v_cmpx_t_i32                   dst, src0, src1
-    v_cmpx_t_i64                   dst, src0, src1
-    v_cmpx_t_u32                   dst, src0, src1
-    v_cmpx_t_u64                   dst, src0, src1
-    v_cmpx_tru_f32                 dst, src0, src1
-    v_cmpx_tru_f64                 dst, src0, src1
-    v_cmpx_u_f32                   dst, src0, src1
-    v_cmpx_u_f64                   dst, src0, src1

diff --git a/docs/AMDGPUAsmGFX8.rst b/docs/AMDGPUAsmGFX8.rst
deleted file mode 100644 (file)
index 44c4843..0000000
--- a/docs/AMDGPUAsmGFX8.rst
+++ /dev/null
@@ -1,1672 +0,0 @@
-..
-    **************************************************
-    *                                                *
-    *   Automatically generated file, do not edit!   *
-    *                                                *
-    **************************************************
-
-===========================
-Syntax of GFX8 Instructions
-===========================
-
-.. contents::
-  :local:
-
-
-DS
-===========================
-
-.. parsed-literal::
-
-    ds_add_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_src2_f32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_b32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_b64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_rtn_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_rtn_b64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_src2_b32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_src2_b64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_append                      dst                            :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_bpermute_b32                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
-    ds_cmpst_b32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_b64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_f32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_f64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_rtn_b32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_rtn_b64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_rtn_f32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_rtn_f64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_condxchg32_rtn_b64          dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_consume                     dst                            :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_barrier                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_init                    src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_sema_br                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_sema_p                                                 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_sema_release_all                                       :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_sema_v                                                 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_f64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_i32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_i64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_f64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_i32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_i64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_f32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_f64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_i32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_i64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_f64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_i32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_i64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_f64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_i32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_i64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_f32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_f64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_i32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_i64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_mskor_b32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_mskor_b64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_mskor_rtn_b32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_mskor_rtn_b64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_nop
-    ds_or_b32                      src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_b64                      src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_rtn_b32                  dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_rtn_b64                  dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_src2_b32                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_src2_b64                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_ordered_count               dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_permute_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
-    ds_read2_b32                   dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read2_b64                   dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read2st64_b32               dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read2st64_b64               dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_b128                   dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_b32                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_b64                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_b96                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_i16                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_i8                     dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_u16                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_u8                     dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_rtn_u32                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_rtn_u64                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_src2_u32               src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_src2_u64               src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_u32                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_u64                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_swizzle_b32                 dst, src0                      :ref:`sw_offset16<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrap_rtn_b32                dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write2_b32                  src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write2_b64                  src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write2st64_b32              src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write2st64_b64              src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b128                  src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b16                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b32                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b64                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b8                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b96                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_src2_b32              src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_src2_b64              src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg2_rtn_b32             dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg2_rtn_b64             dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg2st64_rtn_b32         dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg2st64_rtn_b64         dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg_rtn_b32              dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg_rtn_b64              dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_b32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_b64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_rtn_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_rtn_b64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_src2_b32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_src2_b64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-
-EXP
-===========================
-
-.. parsed-literal::
-
-    exp                            dst, src0, src1, src2, src3    :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
-
-FLAT
-===========================
-
-.. parsed-literal::
-
-    flat_atomic_add                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_add_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_and                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_and_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_cmpswap            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_cmpswap_x2         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_dec                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_dec_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_inc                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_inc_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_or                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_or_x2              dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_smax               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_smax_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_smin               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_smin_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_sub                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_sub_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_swap               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_swap_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_umax               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_umax_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_umin               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_umin_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_xor                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_xor_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_dword                dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_dwordx2              dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_dwordx3              dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_dwordx4              dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_sbyte                dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_sshort               dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_ubyte                dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_ushort               dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_byte                src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_dword               src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_dwordx2             src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_dwordx3             src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_dwordx4             src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_short               src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-
-MIMG
-===========================
-
-.. parsed-literal::
-
-    image_atomic_add               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_and               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_cmpswap           dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_dec               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_inc               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_or                dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_smax              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_smin              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_sub               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_swap              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_umax              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_umin              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_xor               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4                  dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_b                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_b_cl             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_b_cl_o           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_b_o              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_b              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_b_cl           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_b_cl_o         dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_b_o            dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_cl             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_cl_o           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_l              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_l_o            dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_lz             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_lz_o           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_o              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_cl               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_cl_o             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_l                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_l_o              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_lz               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_lz_o             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_o                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_get_lod                  dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_get_resinfo              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load                     dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_load_mip                 dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_load_mip_pck             dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_mip_pck_sgn         dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_pck                 dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_pck_sgn             dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample                   dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b_cl              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_b               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_b_cl            dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cl              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_l               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_lz              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cl                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_l                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_lz                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_store                    src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_store_mip                src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_store_mip_pck            src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_store_pck                src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-
-MUBUF
-===========================
-
-.. parsed-literal::
-
-    buffer_atomic_add              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_add_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_and              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_and_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_cmpswap          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_cmpswap_x2       dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_dec              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_dec_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_inc              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_inc_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_or               dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_or_x2            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smax             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smax_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smin             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smin_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_sub              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_sub_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_swap             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_swap_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umax             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umax_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umin             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umin_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_xor              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_xor_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_dword              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_dwordx2            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_dwordx3            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_dwordx4            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_d16_x       dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_d16_xy      dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_d16_xyz     dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_d16_xyzw    dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_x           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_format_xy          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_xyz         dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_xyzw        dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_sbyte              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_sshort             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_ubyte              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_ushort             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_store_byte              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dword             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dwordx2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dwordx3           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dwordx4           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_d16_x      src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_d16_xy     src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_d16_xyz    src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_d16_xyzw   src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_x          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_xy         src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_xyz        src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_xyzw       src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_lds_dword         src0, src1                     :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`lds<amdgpu_synid_lds>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_short             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_wbinvl1
-    buffer_wbinvl1_vol
-
-SMEM
-===========================
-
-.. parsed-literal::
-
-    s_atc_probe                    src0, src1, src2
-    s_atc_probe_buffer             src0, src1, src2
-    s_buffer_load_dword            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_load_dwordx16         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_load_dwordx2          dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_load_dwordx4          dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_load_dwordx8          dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_store_dword           src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_store_dwordx2         src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_store_dwordx4         src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-    s_dcache_inv
-    s_dcache_inv_vol
-    s_dcache_wb
-    s_dcache_wb_vol
-    s_load_dword                   dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_load_dwordx16                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_load_dwordx2                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_load_dwordx4                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_load_dwordx8                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_memrealtime                  dst
-    s_memtime                      dst
-    s_store_dword                  src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-    s_store_dwordx2                src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-    s_store_dwordx4                src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-
-SOP1
-===========================
-
-.. parsed-literal::
-
-    s_abs_i32                      dst, src0
-    s_and_saveexec_b64             dst, src0
-    s_andn2_saveexec_b64           dst, src0
-    s_bcnt0_i32_b32                dst, src0
-    s_bcnt0_i32_b64                dst, src0
-    s_bcnt1_i32_b32                dst, src0
-    s_bcnt1_i32_b64                dst, src0
-    s_bitset0_b32                  dst, src0
-    s_bitset0_b64                  dst, src0
-    s_bitset1_b32                  dst, src0
-    s_bitset1_b64                  dst, src0
-    s_brev_b32                     dst, src0
-    s_brev_b64                     dst, src0
-    s_cbranch_join                 src0
-    s_cmov_b32                     dst, src0
-    s_cmov_b64                     dst, src0
-    s_ff0_i32_b32                  dst, src0
-    s_ff0_i32_b64                  dst, src0
-    s_ff1_i32_b32                  dst, src0
-    s_ff1_i32_b64                  dst, src0
-    s_flbit_i32                    dst, src0
-    s_flbit_i32_b32                dst, src0
-    s_flbit_i32_b64                dst, src0
-    s_flbit_i32_i64                dst, src0
-    s_getpc_b64                    dst
-    s_mov_b32                      dst, src0
-    s_mov_b64                      dst, src0
-    s_mov_fed_b32                  dst, src0
-    s_movreld_b32                  dst, src0
-    s_movreld_b64                  dst, src0
-    s_movrels_b32                  dst, src0
-    s_movrels_b64                  dst, src0
-    s_nand_saveexec_b64            dst, src0
-    s_nor_saveexec_b64             dst, src0
-    s_not_b32                      dst, src0
-    s_not_b64                      dst, src0
-    s_or_saveexec_b64              dst, src0
-    s_orn2_saveexec_b64            dst, src0
-    s_quadmask_b32                 dst, src0
-    s_quadmask_b64                 dst, src0
-    s_rfe_b64                      src0
-    s_set_gpr_idx_idx              src0
-    s_setpc_b64                    src0
-    s_sext_i32_i16                 dst, src0
-    s_sext_i32_i8                  dst, src0
-    s_swappc_b64                   dst, src0
-    s_wqm_b32                      dst, src0
-    s_wqm_b64                      dst, src0
-    s_xnor_saveexec_b64            dst, src0
-    s_xor_saveexec_b64             dst, src0
-
-SOP2
-===========================
-
-.. parsed-literal::
-
-    s_absdiff_i32                  dst, src0, src1
-    s_add_i32                      dst, src0, src1
-    s_add_u32                      dst, src0, src1
-    s_addc_u32                     dst, src0, src1
-    s_and_b32                      dst, src0, src1
-    s_and_b64                      dst, src0, src1
-    s_andn2_b32                    dst, src0, src1
-    s_andn2_b64                    dst, src0, src1
-    s_ashr_i32                     dst, src0, src1
-    s_ashr_i64                     dst, src0, src1
-    s_bfe_i32                      dst, src0, src1
-    s_bfe_i64                      dst, src0, src1
-    s_bfe_u32                      dst, src0, src1
-    s_bfe_u64                      dst, src0, src1
-    s_bfm_b32                      dst, src0, src1
-    s_bfm_b64                      dst, src0, src1
-    s_cbranch_g_fork               src0, src1
-    s_cselect_b32                  dst, src0, src1
-    s_cselect_b64                  dst, src0, src1
-    s_lshl_b32                     dst, src0, src1
-    s_lshl_b64                     dst, src0, src1
-    s_lshr_b32                     dst, src0, src1
-    s_lshr_b64                     dst, src0, src1
-    s_max_i32                      dst, src0, src1
-    s_max_u32                      dst, src0, src1
-    s_min_i32                      dst, src0, src1
-    s_min_u32                      dst, src0, src1
-    s_mul_i32                      dst, src0, src1
-    s_nand_b32                     dst, src0, src1
-    s_nand_b64                     dst, src0, src1
-    s_nor_b32                      dst, src0, src1
-    s_nor_b64                      dst, src0, src1
-    s_or_b32                       dst, src0, src1
-    s_or_b64                       dst, src0, src1
-    s_orn2_b32                     dst, src0, src1
-    s_orn2_b64                     dst, src0, src1
-    s_rfe_restore_b64              src0, src1
-    s_sub_i32                      dst, src0, src1
-    s_sub_u32                      dst, src0, src1
-    s_subb_u32                     dst, src0, src1
-    s_xnor_b32                     dst, src0, src1
-    s_xnor_b64                     dst, src0, src1
-    s_xor_b32                      dst, src0, src1
-    s_xor_b64                      dst, src0, src1
-
-SOPC
-===========================
-
-.. parsed-literal::
-
-    s_bitcmp0_b32                  src0, src1
-    s_bitcmp0_b64                  src0, src1
-    s_bitcmp1_b32                  src0, src1
-    s_bitcmp1_b64                  src0, src1
-    s_cmp_eq_i32                   src0, src1
-    s_cmp_eq_u32                   src0, src1
-    s_cmp_eq_u64                   src0, src1
-    s_cmp_ge_i32                   src0, src1
-    s_cmp_ge_u32                   src0, src1
-    s_cmp_gt_i32                   src0, src1
-    s_cmp_gt_u32                   src0, src1
-    s_cmp_le_i32                   src0, src1
-    s_cmp_le_u32                   src0, src1
-    s_cmp_lg_i32                   src0, src1
-    s_cmp_lg_u32                   src0, src1
-    s_cmp_lg_u64                   src0, src1
-    s_cmp_lt_i32                   src0, src1
-    s_cmp_lt_u32                   src0, src1
-    s_set_gpr_idx_on               src0, src1
-    s_setvskip                     src0, src1
-
-SOPK
-===========================
-
-.. parsed-literal::
-
-    s_addk_i32                     dst, src0
-    s_cbranch_i_fork               src0, src1
-    s_cmovk_i32                    dst, src0
-    s_cmpk_eq_i32                  src0, src1
-    s_cmpk_eq_u32                  src0, src1
-    s_cmpk_ge_i32                  src0, src1
-    s_cmpk_ge_u32                  src0, src1
-    s_cmpk_gt_i32                  src0, src1
-    s_cmpk_gt_u32                  src0, src1
-    s_cmpk_le_i32                  src0, src1
-    s_cmpk_le_u32                  src0, src1
-    s_cmpk_lg_i32                  src0, src1
-    s_cmpk_lg_u32                  src0, src1
-    s_cmpk_lt_i32                  src0, src1
-    s_cmpk_lt_u32                  src0, src1
-    s_getreg_b32                   dst, src0
-    s_movk_i32                     dst, src0
-    s_mulk_i32                     dst, src0
-    s_setreg_b32                   dst, src0
-    s_setreg_imm32_b32             dst, src0
-
-SOPP
-===========================
-
-.. parsed-literal::
-
-    s_barrier
-    s_branch                       src0
-    s_cbranch_cdbgsys              src0
-    s_cbranch_cdbgsys_and_user     src0
-    s_cbranch_cdbgsys_or_user      src0
-    s_cbranch_cdbguser             src0
-    s_cbranch_execnz               src0
-    s_cbranch_execz                src0
-    s_cbranch_scc0                 src0
-    s_cbranch_scc1                 src0
-    s_cbranch_vccnz                src0
-    s_cbranch_vccz                 src0
-    s_decperflevel                 src0
-    s_endpgm
-    s_endpgm_saved
-    s_icache_inv
-    s_incperflevel                 src0
-    s_nop                          src0
-    s_sendmsg                      src0
-    s_sendmsghalt                  src0
-    s_set_gpr_idx_mode             src0
-    s_set_gpr_idx_off
-    s_sethalt                      src0
-    s_setkill                      src0
-    s_setprio                      src0
-    s_sleep                        src0
-    s_trap                         src0
-    s_ttracedata
-    s_waitcnt                      src0
-    s_wakeup
-
-VINTRP
-===========================
-
-.. parsed-literal::
-
-    v_interp_mov_f32               dst, src0, src1
-    v_interp_p1_f32                dst, src0, src1
-    v_interp_p2_f32                dst, src0, src1
-
-VOP1
-===========================
-
-.. parsed-literal::
-
-    v_bfrev_b32                    dst, src0
-    v_bfrev_b32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_bfrev_b32_sdwa               dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_ceil_f16                     dst, src0
-    v_ceil_f16_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ceil_f16_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_ceil_f32                     dst, src0
-    v_ceil_f32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ceil_f32_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_ceil_f64                     dst, src0
-    v_clrexcp
-    v_cos_f16                      dst, src0
-    v_cos_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cos_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cos_f32                      dst, src0
-    v_cos_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cos_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f16_f32                  dst, src0
-    v_cvt_f16_f32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f16_f32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f16_i16                  dst, src0
-    v_cvt_f16_i16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f16_i16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f16_u16                  dst, src0
-    v_cvt_f16_u16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f16_u16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f32_f16                  dst, src0
-    v_cvt_f32_f16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f32_f16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f32_f64                  dst, src0
-    v_cvt_f32_i32                  dst, src0
-    v_cvt_f32_i32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f32_i32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f32_u32                  dst, src0
-    v_cvt_f32_u32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f32_u32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f32_ubyte0               dst, src0
-    v_cvt_f32_ubyte0_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f32_ubyte0_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f32_ubyte1               dst, src0
-    v_cvt_f32_ubyte1_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f32_ubyte1_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f32_ubyte2               dst, src0
-    v_cvt_f32_ubyte2_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f32_ubyte2_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f32_ubyte3               dst, src0
-    v_cvt_f32_ubyte3_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f32_ubyte3_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f64_f32                  dst, src0
-    v_cvt_f64_i32                  dst, src0
-    v_cvt_f64_u32                  dst, src0
-    v_cvt_flr_i32_f32              dst, src0
-    v_cvt_flr_i32_f32_dpp          dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_flr_i32_f32_sdwa         dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_i16_f16                  dst, src0
-    v_cvt_i16_f16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_i16_f16_sdwa             dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_i32_f32                  dst, src0
-    v_cvt_i32_f32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_i32_f32_sdwa             dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_i32_f64                  dst, src0
-    v_cvt_off_f32_i4               dst, src0
-    v_cvt_off_f32_i4_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_off_f32_i4_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_rpi_i32_f32              dst, src0
-    v_cvt_rpi_i32_f32_dpp          dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_rpi_i32_f32_sdwa         dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_u16_f16                  dst, src0
-    v_cvt_u16_f16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_u16_f16_sdwa             dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_u32_f32                  dst, src0
-    v_cvt_u32_f32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_u32_f32_sdwa             dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_u32_f64                  dst, src0
-    v_exp_f16                      dst, src0
-    v_exp_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_exp_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_exp_f32                      dst, src0
-    v_exp_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_exp_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_exp_legacy_f32               dst, src0
-    v_exp_legacy_f32_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_exp_legacy_f32_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_ffbh_i32                     dst, src0
-    v_ffbh_i32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ffbh_i32_sdwa                dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_ffbh_u32                     dst, src0
-    v_ffbh_u32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ffbh_u32_sdwa                dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_ffbl_b32                     dst, src0
-    v_ffbl_b32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ffbl_b32_sdwa                dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_floor_f16                    dst, src0
-    v_floor_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_floor_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_floor_f32                    dst, src0
-    v_floor_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_floor_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_floor_f64                    dst, src0
-    v_fract_f16                    dst, src0
-    v_fract_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_fract_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_fract_f32                    dst, src0
-    v_fract_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_fract_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_fract_f64                    dst, src0
-    v_frexp_exp_i16_f16            dst, src0
-    v_frexp_exp_i16_f16_dpp        dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_frexp_exp_i16_f16_sdwa       dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_frexp_exp_i32_f32            dst, src0
-    v_frexp_exp_i32_f32_dpp        dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_frexp_exp_i32_f32_sdwa       dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_frexp_exp_i32_f64            dst, src0
-    v_frexp_mant_f16               dst, src0
-    v_frexp_mant_f16_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_frexp_mant_f16_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_frexp_mant_f32               dst, src0
-    v_frexp_mant_f32_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_frexp_mant_f32_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_frexp_mant_f64               dst, src0
-    v_log_f16                      dst, src0
-    v_log_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_log_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_log_f32                      dst, src0
-    v_log_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_log_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_log_legacy_f32               dst, src0
-    v_log_legacy_f32_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_log_legacy_f32_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_mov_b32                      dst, src0
-    v_mov_b32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mov_b32_sdwa                 dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_mov_fed_b32                  dst, src0
-    v_mov_fed_b32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mov_fed_b32_sdwa             dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_movreld_b32                  dst, src0
-    v_movrels_b32                  dst, src0
-    v_movrelsd_b32                 dst, src0
-    v_nop
-    v_not_b32                      dst, src0
-    v_not_b32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_not_b32_sdwa                 dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_rcp_f16                      dst, src0
-    v_rcp_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_rcp_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_rcp_f32                      dst, src0
-    v_rcp_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_rcp_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_rcp_f64                      dst, src0
-    v_rcp_iflag_f32                dst, src0
-    v_rcp_iflag_f32_dpp            dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_rcp_iflag_f32_sdwa           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_readfirstlane_b32            dst, src0
-    v_rndne_f16                    dst, src0
-    v_rndne_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_rndne_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_rndne_f32                    dst, src0
-    v_rndne_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_rndne_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_rndne_f64                    dst, src0
-    v_rsq_f16                      dst, src0
-    v_rsq_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_rsq_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_rsq_f32                      dst, src0
-    v_rsq_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_rsq_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_rsq_f64                      dst, src0
-    v_sin_f16                      dst, src0
-    v_sin_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sin_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_sin_f32                      dst, src0
-    v_sin_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sin_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_sqrt_f16                     dst, src0
-    v_sqrt_f16_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sqrt_f16_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_sqrt_f32                     dst, src0
-    v_sqrt_f32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sqrt_f32_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_sqrt_f64                     dst, src0
-    v_trunc_f16                    dst, src0
-    v_trunc_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_trunc_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_trunc_f32                    dst, src0
-    v_trunc_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_trunc_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_trunc_f64                    dst, src0
-
-VOP2
-===========================
-
-.. parsed-literal::
-
-    v_add_f16                      dst, src0, src1
-    v_add_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_add_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_add_f32                      dst, src0, src1
-    v_add_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_add_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_add_u16                      dst, src0, src1
-    v_add_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_add_u16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_add_u32                      dst0, dst1, src0, src1
-    v_add_u32_dpp                  dst0, dst1, src0, src1         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_add_u32_sdwa                 dst0, dst1, src0, src1         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_addc_u32                     dst0, dst1, src0, src1, src2
-    v_addc_u32_dpp                 dst0, dst1, src0, src1, src2   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_addc_u32_sdwa                dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_and_b32                      dst, src0, src1
-    v_and_b32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_and_b32_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_ashrrev_i16                  dst, src0, src1
-    v_ashrrev_i16_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ashrrev_i16_sdwa             dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_ashrrev_i32                  dst, src0, src1
-    v_ashrrev_i32_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ashrrev_i32_sdwa             dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cndmask_b32                  dst, src0, src1, src2
-    v_cndmask_b32_dpp              dst, src0, src1, src2          :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cndmask_b32_sdwa             dst, src0, src1, src2          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_ldexp_f16                    dst, src0, src1
-    v_ldexp_f16_dpp                dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ldexp_f16_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshlrev_b16                  dst, src0, src1
-    v_lshlrev_b16_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshlrev_b16_sdwa             dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshlrev_b32                  dst, src0, src1
-    v_lshlrev_b32_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshlrev_b32_sdwa             dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshrrev_b16                  dst, src0, src1
-    v_lshrrev_b16_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshrrev_b16_sdwa             dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshrrev_b32                  dst, src0, src1
-    v_lshrrev_b32_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshrrev_b32_sdwa             dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mac_f16                      dst, src0, src1
-    v_mac_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mac_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mac_f32                      dst, src0, src1
-    v_mac_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mac_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_madak_f16                    dst, src0, src1, src2
-    v_madak_f32                    dst, src0, src1, src2
-    v_madmk_f16                    dst, src0, src1, src2
-    v_madmk_f32                    dst, src0, src1, src2
-    v_max_f16                      dst, src0, src1
-    v_max_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_max_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_max_f32                      dst, src0, src1
-    v_max_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_max_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_max_i16                      dst, src0, src1
-    v_max_i16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_max_i16_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_max_i32                      dst, src0, src1
-    v_max_i32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_max_i32_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_max_u16                      dst, src0, src1
-    v_max_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_max_u16_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_max_u32                      dst, src0, src1
-    v_max_u32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_max_u32_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_f16                      dst, src0, src1
-    v_min_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_min_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_f32                      dst, src0, src1
-    v_min_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_min_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_i16                      dst, src0, src1
-    v_min_i16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_min_i16_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_i32                      dst, src0, src1
-    v_min_i32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_min_i32_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_u16                      dst, src0, src1
-    v_min_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_min_u16_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_u32                      dst, src0, src1
-    v_min_u32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_min_u32_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_f16                      dst, src0, src1
-    v_mul_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_f32                      dst, src0, src1
-    v_mul_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_hi_i32_i24               dst, src0, src1
-    v_mul_hi_i32_i24_dpp           dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_hi_i32_i24_sdwa          dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_hi_u32_u24               dst, src0, src1
-    v_mul_hi_u32_u24_dpp           dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_hi_u32_u24_sdwa          dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_i32_i24                  dst, src0, src1
-    v_mul_i32_i24_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_i32_i24_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_legacy_f32               dst, src0, src1
-    v_mul_legacy_f32_dpp           dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_legacy_f32_sdwa          dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_lo_u16                   dst, src0, src1
-    v_mul_lo_u16_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_lo_u16_sdwa              dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_u32_u24                  dst, src0, src1
-    v_mul_u32_u24_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_u32_u24_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_or_b32                       dst, src0, src1
-    v_or_b32_dpp                   dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_or_b32_sdwa                  dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_sub_f16                      dst, src0, src1
-    v_sub_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sub_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_sub_f32                      dst, src0, src1
-    v_sub_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sub_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_sub_u16                      dst, src0, src1
-    v_sub_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sub_u16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_sub_u32                      dst0, dst1, src0, src1
-    v_sub_u32_dpp                  dst0, dst1, src0, src1         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sub_u32_sdwa                 dst0, dst1, src0, src1         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subb_u32                     dst0, dst1, src0, src1, src2
-    v_subb_u32_dpp                 dst0, dst1, src0, src1, src2   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subb_u32_sdwa                dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subbrev_u32                  dst0, dst1, src0, src1, src2
-    v_subbrev_u32_dpp              dst0, dst1, src0, src1, src2   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subbrev_u32_sdwa             dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_f16                   dst, src0, src1
-    v_subrev_f16_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_f32                   dst, src0, src1
-    v_subrev_f32_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_u16                   dst, src0, src1
-    v_subrev_u16_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_u16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_u32                   dst0, dst1, src0, src1
-    v_subrev_u32_dpp               dst0, dst1, src0, src1         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_u32_sdwa              dst0, dst1, src0, src1         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_xor_b32                      dst, src0, src1
-    v_xor_b32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_xor_b32_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-
-VOP3
-===========================
-
-.. parsed-literal::
-
-    v_add_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_add_u32_e64                  dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
-    v_addc_u32_e64                 dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_alignbit_b32                 dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_alignbyte_b32                dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_and_b32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_ashrrev_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_ashrrev_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_ashrrev_i64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_bcnt_u32_b32                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_bfe_i32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_bfe_u32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_bfi_b32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_bfm_b32                      dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_bfrev_b32_e64                dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_ceil_f16_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ceil_f32_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ceil_f64_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_clrexcp_e64                                                 :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_class_f16_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_class_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_class_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_f32_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_f64_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_i16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_i32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_i64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_u16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_u32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_u64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lg_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lg_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lg_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_neq_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_neq_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_neq_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nge_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nge_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nge_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ngt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ngt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ngt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nle_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nle_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nle_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlg_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlg_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlg_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_o_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_o_f32_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_o_f64_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_i16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_i32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_i64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_u16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_u32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_u64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_tru_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_tru_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_tru_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_u_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_u_f32_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_u_f64_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_class_f16_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_class_f32_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_class_f64_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lg_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lg_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lg_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_neq_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_neq_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_neq_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nge_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nge_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nge_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ngt_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ngt_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ngt_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nle_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nle_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nle_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlg_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlg_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlg_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlt_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlt_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlt_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_o_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_o_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_o_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_tru_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_tru_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_tru_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_u_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_u_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_u_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cndmask_b32_e64              dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_cos_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cos_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubeid_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubema_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubesc_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubetc_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_f32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_i16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_u16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_f16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_f64_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_i32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_u32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte0_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte1_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte2_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte3_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_f32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_i32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_u32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_flr_i32_f32_e64          dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_i16_f16_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_i32_f32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_i32_f64_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_off_f32_i4_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_i16_i32               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_u16_u32               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_u8_f32                dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pkaccum_u8_f32           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pknorm_i16_f32           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pknorm_u16_f32           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pkrtz_f16_f32            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_rpi_i32_f32_e64          dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_u16_f16_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_u32_f32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_u32_f64_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_div_fixup_f16                dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fixup_f32                dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fixup_f64                dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fmas_f32                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fmas_f64                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_scale_f32                dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_div_scale_f64                dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_exp_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_exp_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_exp_legacy_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ffbh_i32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_ffbh_u32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_ffbl_b32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_floor_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_floor_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_floor_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_f16                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_f32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_f64                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fract_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fract_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fract_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_exp_i16_f16_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_exp_i32_f32_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_exp_i32_f64_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_mant_f16_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_mant_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_mant_f64_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_interp_mov_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_interp_p1_f32_e64            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_interp_p1ll_f16              dst, src0, src1                :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_interp_p1lv_f16              dst, src0, src1, src2          :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_interp_p2_f16                dst, src0, src1, src2          :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_interp_p2_f32_e64            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f32                    dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f64                    dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lerp_u8                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_log_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_log_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_log_legacy_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lshlrev_b16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshlrev_b32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshlrev_b64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshrrev_b16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshrrev_b32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshrrev_b64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mac_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mac_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_f16                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_f32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i16                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i32_i24                  dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i64_i32                  dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_legacy_f32               dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_u16                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_u32_u24                  dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_u64_u32                  dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_max3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_max_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_i16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_max_i32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_max_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_max_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mbcnt_hi_u32_b32             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mbcnt_lo_u32_b32             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_med3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_med3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_med3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_min3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_min3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_min_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_i16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_min_i32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_min_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_min_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mov_b32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_mov_fed_b32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_movreld_b32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_movrels_b32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_movrelsd_b32_e64             dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_mqsad_pk_u16_u8              dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mqsad_u32_u8                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_msad_u8                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_i32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_i32_i24_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_u32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_u32_u24_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_i32_i24_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_legacy_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_lo_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_lo_u32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_u32_u24_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_nop_e64                                                     :ref:`omod<amdgpu_synid_omod>`
-    v_not_b32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_or_b32_e64                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_perm_b32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_qsad_pk_u16_u8               dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_f64_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_iflag_f32_e64            dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_readlane_b32                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_rndne_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rndne_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rndne_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_f64_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_hi_u8                    dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_u16                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_u32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_u8                       dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sin_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sin_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sqrt_f16_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sqrt_f32_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sqrt_f64_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_sub_u32_e64                  dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
-    v_subb_u32_e64                 dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_subbrev_u32_e64              dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_u32_e64               dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
-    v_trig_preop_f64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_trunc_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_trunc_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_trunc_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_writelane_b32                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_xor_b32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-
-VOPC
-===========================
-
-.. parsed-literal::
-
-    v_cmp_class_f16                dst, src0, src1
-    v_cmp_class_f16_sdwa           dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_class_f32                dst, src0, src1
-    v_cmp_class_f32_sdwa           dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_class_f64                dst, src0, src1
-    v_cmp_eq_f16                   dst, src0, src1
-    v_cmp_eq_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_eq_f32                   dst, src0, src1
-    v_cmp_eq_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_eq_f64                   dst, src0, src1
-    v_cmp_eq_i16                   dst, src0, src1
-    v_cmp_eq_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_eq_i32                   dst, src0, src1
-    v_cmp_eq_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_eq_i64                   dst, src0, src1
-    v_cmp_eq_u16                   dst, src0, src1
-    v_cmp_eq_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_eq_u32                   dst, src0, src1
-    v_cmp_eq_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_eq_u64                   dst, src0, src1
-    v_cmp_f_f16                    dst, src0, src1
-    v_cmp_f_f16_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_f_f32                    dst, src0, src1
-    v_cmp_f_f32_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_f_f64                    dst, src0, src1
-    v_cmp_f_i16                    dst, src0, src1
-    v_cmp_f_i16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_f_i32                    dst, src0, src1
-    v_cmp_f_i32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_f_i64                    dst, src0, src1
-    v_cmp_f_u16                    dst, src0, src1
-    v_cmp_f_u16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_f_u32                    dst, src0, src1
-    v_cmp_f_u32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_f_u64                    dst, src0, src1
-    v_cmp_ge_f16                   dst, src0, src1
-    v_cmp_ge_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ge_f32                   dst, src0, src1
-    v_cmp_ge_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ge_f64                   dst, src0, src1
-    v_cmp_ge_i16                   dst, src0, src1
-    v_cmp_ge_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ge_i32                   dst, src0, src1
-    v_cmp_ge_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ge_i64                   dst, src0, src1
-    v_cmp_ge_u16                   dst, src0, src1
-    v_cmp_ge_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ge_u32                   dst, src0, src1
-    v_cmp_ge_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ge_u64                   dst, src0, src1
-    v_cmp_gt_f16                   dst, src0, src1
-    v_cmp_gt_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_gt_f32                   dst, src0, src1
-    v_cmp_gt_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_gt_f64                   dst, src0, src1
-    v_cmp_gt_i16                   dst, src0, src1
-    v_cmp_gt_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_gt_i32                   dst, src0, src1
-    v_cmp_gt_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_gt_i64                   dst, src0, src1
-    v_cmp_gt_u16                   dst, src0, src1
-    v_cmp_gt_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_gt_u32                   dst, src0, src1
-    v_cmp_gt_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_gt_u64                   dst, src0, src1
-    v_cmp_le_f16                   dst, src0, src1
-    v_cmp_le_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_le_f32                   dst, src0, src1
-    v_cmp_le_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_le_f64                   dst, src0, src1
-    v_cmp_le_i16                   dst, src0, src1
-    v_cmp_le_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_le_i32                   dst, src0, src1
-    v_cmp_le_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_le_i64                   dst, src0, src1
-    v_cmp_le_u16                   dst, src0, src1
-    v_cmp_le_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_le_u32                   dst, src0, src1
-    v_cmp_le_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_le_u64                   dst, src0, src1
-    v_cmp_lg_f16                   dst, src0, src1
-    v_cmp_lg_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lg_f32                   dst, src0, src1
-    v_cmp_lg_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lg_f64                   dst, src0, src1
-    v_cmp_lt_f16                   dst, src0, src1
-    v_cmp_lt_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lt_f32                   dst, src0, src1
-    v_cmp_lt_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lt_f64                   dst, src0, src1
-    v_cmp_lt_i16                   dst, src0, src1
-    v_cmp_lt_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lt_i32                   dst, src0, src1
-    v_cmp_lt_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lt_i64                   dst, src0, src1
-    v_cmp_lt_u16                   dst, src0, src1
-    v_cmp_lt_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lt_u32                   dst, src0, src1
-    v_cmp_lt_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lt_u64                   dst, src0, src1
-    v_cmp_ne_i16                   dst, src0, src1
-    v_cmp_ne_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ne_i32                   dst, src0, src1
-    v_cmp_ne_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ne_i64                   dst, src0, src1
-    v_cmp_ne_u16                   dst, src0, src1
-    v_cmp_ne_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ne_u32                   dst, src0, src1
-    v_cmp_ne_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ne_u64                   dst, src0, src1
-    v_cmp_neq_f16                  dst, src0, src1
-    v_cmp_neq_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_neq_f32                  dst, src0, src1
-    v_cmp_neq_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_neq_f64                  dst, src0, src1
-    v_cmp_nge_f16                  dst, src0, src1
-    v_cmp_nge_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nge_f32                  dst, src0, src1
-    v_cmp_nge_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nge_f64                  dst, src0, src1
-    v_cmp_ngt_f16                  dst, src0, src1
-    v_cmp_ngt_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ngt_f32                  dst, src0, src1
-    v_cmp_ngt_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ngt_f64                  dst, src0, src1
-    v_cmp_nle_f16                  dst, src0, src1
-    v_cmp_nle_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nle_f32                  dst, src0, src1
-    v_cmp_nle_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nle_f64                  dst, src0, src1
-    v_cmp_nlg_f16                  dst, src0, src1
-    v_cmp_nlg_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nlg_f32                  dst, src0, src1
-    v_cmp_nlg_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nlg_f64                  dst, src0, src1
-    v_cmp_nlt_f16                  dst, src0, src1
-    v_cmp_nlt_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nlt_f32                  dst, src0, src1
-    v_cmp_nlt_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nlt_f64                  dst, src0, src1
-    v_cmp_o_f16                    dst, src0, src1
-    v_cmp_o_f16_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_o_f32                    dst, src0, src1
-    v_cmp_o_f32_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_o_f64                    dst, src0, src1
-    v_cmp_t_i16                    dst, src0, src1
-    v_cmp_t_i16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_t_i32                    dst, src0, src1
-    v_cmp_t_i32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_t_i64                    dst, src0, src1
-    v_cmp_t_u16                    dst, src0, src1
-    v_cmp_t_u16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_t_u32                    dst, src0, src1
-    v_cmp_t_u32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_t_u64                    dst, src0, src1
-    v_cmp_tru_f16                  dst, src0, src1
-    v_cmp_tru_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_tru_f32                  dst, src0, src1
-    v_cmp_tru_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_tru_f64                  dst, src0, src1
-    v_cmp_u_f16                    dst, src0, src1
-    v_cmp_u_f16_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_u_f32                    dst, src0, src1
-    v_cmp_u_f32_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_u_f64                    dst, src0, src1
-    v_cmpx_class_f16               dst, src0, src1
-    v_cmpx_class_f16_sdwa          dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_class_f32               dst, src0, src1
-    v_cmpx_class_f32_sdwa          dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_class_f64               dst, src0, src1
-    v_cmpx_eq_f16                  dst, src0, src1
-    v_cmpx_eq_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_eq_f32                  dst, src0, src1
-    v_cmpx_eq_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_eq_f64                  dst, src0, src1
-    v_cmpx_eq_i16                  dst, src0, src1
-    v_cmpx_eq_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_eq_i32                  dst, src0, src1
-    v_cmpx_eq_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_eq_i64                  dst, src0, src1
-    v_cmpx_eq_u16                  dst, src0, src1
-    v_cmpx_eq_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_eq_u32                  dst, src0, src1
-    v_cmpx_eq_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_eq_u64                  dst, src0, src1
-    v_cmpx_f_f16                   dst, src0, src1
-    v_cmpx_f_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_f_f32                   dst, src0, src1
-    v_cmpx_f_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_f_f64                   dst, src0, src1
-    v_cmpx_f_i16                   dst, src0, src1
-    v_cmpx_f_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_f_i32                   dst, src0, src1
-    v_cmpx_f_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_f_i64                   dst, src0, src1
-    v_cmpx_f_u16                   dst, src0, src1
-    v_cmpx_f_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_f_u32                   dst, src0, src1
-    v_cmpx_f_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_f_u64                   dst, src0, src1
-    v_cmpx_ge_f16                  dst, src0, src1
-    v_cmpx_ge_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ge_f32                  dst, src0, src1
-    v_cmpx_ge_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ge_f64                  dst, src0, src1
-    v_cmpx_ge_i16                  dst, src0, src1
-    v_cmpx_ge_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ge_i32                  dst, src0, src1
-    v_cmpx_ge_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ge_i64                  dst, src0, src1
-    v_cmpx_ge_u16                  dst, src0, src1
-    v_cmpx_ge_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ge_u32                  dst, src0, src1
-    v_cmpx_ge_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ge_u64                  dst, src0, src1
-    v_cmpx_gt_f16                  dst, src0, src1
-    v_cmpx_gt_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_gt_f32                  dst, src0, src1
-    v_cmpx_gt_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_gt_f64                  dst, src0, src1
-    v_cmpx_gt_i16                  dst, src0, src1
-    v_cmpx_gt_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_gt_i32                  dst, src0, src1
-    v_cmpx_gt_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_gt_i64                  dst, src0, src1
-    v_cmpx_gt_u16                  dst, src0, src1
-    v_cmpx_gt_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_gt_u32                  dst, src0, src1
-    v_cmpx_gt_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_gt_u64                  dst, src0, src1
-    v_cmpx_le_f16                  dst, src0, src1
-    v_cmpx_le_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_le_f32                  dst, src0, src1
-    v_cmpx_le_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_le_f64                  dst, src0, src1
-    v_cmpx_le_i16                  dst, src0, src1
-    v_cmpx_le_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_le_i32                  dst, src0, src1
-    v_cmpx_le_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_le_i64                  dst, src0, src1
-    v_cmpx_le_u16                  dst, src0, src1
-    v_cmpx_le_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_le_u32                  dst, src0, src1
-    v_cmpx_le_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_le_u64                  dst, src0, src1
-    v_cmpx_lg_f16                  dst, src0, src1
-    v_cmpx_lg_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lg_f32                  dst, src0, src1
-    v_cmpx_lg_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lg_f64                  dst, src0, src1
-    v_cmpx_lt_f16                  dst, src0, src1
-    v_cmpx_lt_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lt_f32                  dst, src0, src1
-    v_cmpx_lt_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lt_f64                  dst, src0, src1
-    v_cmpx_lt_i16                  dst, src0, src1
-    v_cmpx_lt_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lt_i32                  dst, src0, src1
-    v_cmpx_lt_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lt_i64                  dst, src0, src1
-    v_cmpx_lt_u16                  dst, src0, src1
-    v_cmpx_lt_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lt_u32                  dst, src0, src1
-    v_cmpx_lt_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lt_u64                  dst, src0, src1
-    v_cmpx_ne_i16                  dst, src0, src1
-    v_cmpx_ne_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ne_i32                  dst, src0, src1
-    v_cmpx_ne_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ne_i64                  dst, src0, src1
-    v_cmpx_ne_u16                  dst, src0, src1
-    v_cmpx_ne_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ne_u32                  dst, src0, src1
-    v_cmpx_ne_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ne_u64                  dst, src0, src1
-    v_cmpx_neq_f16                 dst, src0, src1
-    v_cmpx_neq_f16_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_neq_f32                 dst, src0, src1
-    v_cmpx_neq_f32_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_neq_f64                 dst, src0, src1
-    v_cmpx_nge_f16                 dst, src0, src1
-    v_cmpx_nge_f16_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nge_f32                 dst, src0, src1
-    v_cmpx_nge_f32_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nge_f64                 dst, src0, src1
-    v_cmpx_ngt_f16                 dst, src0, src1
-    v_cmpx_ngt_f16_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ngt_f32                 dst, src0, src1
-    v_cmpx_ngt_f32_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ngt_f64                 dst, src0, src1
-    v_cmpx_nle_f16                 dst, src0, src1
-    v_cmpx_nle_f16_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nle_f32                 dst, src0, src1
-    v_cmpx_nle_f32_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nle_f64                 dst, src0, src1
-    v_cmpx_nlg_f16                 dst, src0, src1
-    v_cmpx_nlg_f16_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nlg_f32                 dst, src0, src1
-    v_cmpx_nlg_f32_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nlg_f64                 dst, src0, src1
-    v_cmpx_nlt_f16                 dst, src0, src1
-    v_cmpx_nlt_f16_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nlt_f32                 dst, src0, src1
-    v_cmpx_nlt_f32_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nlt_f64                 dst, src0, src1
-    v_cmpx_o_f16                   dst, src0, src1
-    v_cmpx_o_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_o_f32                   dst, src0, src1
-    v_cmpx_o_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_o_f64                   dst, src0, src1
-    v_cmpx_t_i16                   dst, src0, src1
-    v_cmpx_t_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_t_i32                   dst, src0, src1
-    v_cmpx_t_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_t_i64                   dst, src0, src1
-    v_cmpx_t_u16                   dst, src0, src1
-    v_cmpx_t_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_t_u32                   dst, src0, src1
-    v_cmpx_t_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_t_u64                   dst, src0, src1
-    v_cmpx_tru_f16                 dst, src0, src1
-    v_cmpx_tru_f16_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_tru_f32                 dst, src0, src1
-    v_cmpx_tru_f32_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_tru_f64                 dst, src0, src1
-    v_cmpx_u_f16                   dst, src0, src1
-    v_cmpx_u_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_u_f32                   dst, src0, src1
-    v_cmpx_u_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_u_f64                   dst, src0, src1

diff --git a/docs/AMDGPUAsmGFX9.rst b/docs/AMDGPUAsmGFX9.rst
deleted file mode 100644 (file)
index 97c13f2..0000000
--- a/docs/AMDGPUAsmGFX9.rst
+++ /dev/null
@@ -1,1906 +0,0 @@
-..
-    **************************************************
-    *                                                *
-    *   Automatically generated file, do not edit!   *
-    *                                                *
-    **************************************************
-
-===========================
-Syntax of GFX9 Instructions
-===========================
-
-.. contents::
-  :local:
-
-
-DS
-===========================
-
-.. parsed-literal::
-
-    ds_add_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_src2_f32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_add_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_b32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_b64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_rtn_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_rtn_b64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_src2_b32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_and_src2_b64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_append                      dst                            :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_bpermute_b32                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
-    ds_cmpst_b32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_b64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_f32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_f64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_rtn_b32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_rtn_b64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_rtn_f32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_cmpst_rtn_f64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_condxchg32_rtn_b64          dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_consume                     dst                            :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_dec_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_barrier                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_init                    src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_sema_br                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_sema_p                                                 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_sema_release_all                                       :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_gws_sema_v                                                 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_inc_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_f64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_i32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_i64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_f64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_i32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_i64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_f32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_f64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_i32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_i64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_max_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_f64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_i32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_i64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_f64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_i32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_i64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_f32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_f64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_i32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_i64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_min_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_mskor_b32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_mskor_b64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_mskor_rtn_b32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_mskor_rtn_b64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_nop
-    ds_or_b32                      src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_b64                      src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_rtn_b32                  dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_rtn_b64                  dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_src2_b32                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_or_src2_b64                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_ordered_count               dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_permute_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
-    ds_read2_b32                   dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read2_b64                   dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read2st64_b32               dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read2st64_b64               dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_b128                   dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_b32                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_b64                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_b96                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_i16                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_i8                     dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_i8_d16                 dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_i8_d16_hi              dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_u16                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_u16_d16                dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_u16_d16_hi             dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_u8                     dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_u8_d16                 dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_read_u8_d16_hi              dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_rtn_u32                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_rtn_u64                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_src2_u32               src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_src2_u64               src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_u32                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_rsub_u64                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_sub_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_swizzle_b32                 dst, src0                      :ref:`sw_offset16<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrap_rtn_b32                dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write2_b32                  src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write2_b64                  src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write2st64_b32              src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write2st64_b64              src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b128                  src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b16                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b16_d16_hi            src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b32                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b64                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b8                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b8_d16_hi             src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_b96                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_src2_b32              src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_write_src2_b64              src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg2_rtn_b32             dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg2_rtn_b64             dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg2st64_rtn_b32         dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg2st64_rtn_b64         dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg_rtn_b32              dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_wrxchg_rtn_b64              dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_b32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_b64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_rtn_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_rtn_b64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_src2_b32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-    ds_xor_src2_b64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-
-EXP
-===========================
-
-.. parsed-literal::
-
-    exp                            dst, src0, src1, src2, src3    :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
-
-FLAT
-===========================
-
-.. parsed-literal::
-
-    flat_atomic_add                dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_add_x2             dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_and                dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_and_x2             dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_cmpswap            dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_cmpswap_x2         dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_dec                dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_dec_x2             dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_inc                dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_inc_x2             dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_or                 dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_or_x2              dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_smax               dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_smax_x2            dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_smin               dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_smin_x2            dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_sub                dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_sub_x2             dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_swap               dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_swap_x2            dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_umax               dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_umax_x2            dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_umin               dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_umin_x2            dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_xor                dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_atomic_xor_x2             dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_dword                dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_dwordx2              dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_dwordx3              dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_dwordx4              dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_sbyte                dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_sbyte_d16            dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_sbyte_d16_hi         dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_short_d16            dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_short_d16_hi         dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_sshort               dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_ubyte                dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_ubyte_d16            dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_ubyte_d16_hi         dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_load_ushort               dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_byte                src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_byte_d16_hi         src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_dword               src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_dwordx2             src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_dwordx3             src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_dwordx4             src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_short               src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    flat_store_short_d16_hi        src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    global_atomic_add              dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_add_x2           dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_and              dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_and_x2           dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_cmpswap          dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_cmpswap_x2       dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_dec              dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_dec_x2           dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_inc              dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_inc_x2           dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_or               dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_or_x2            dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_smax             dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_smax_x2          dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_smin             dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_smin_x2          dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_sub              dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_sub_x2           dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_swap             dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_swap_x2          dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_umax             dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_umax_x2          dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_umin             dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_umin_x2          dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_xor              dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_atomic_xor_x2           dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_load_dword              dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_load_dwordx2            dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_load_dwordx3            dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_load_dwordx4            dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_load_sbyte              dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_load_sbyte_d16          dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_load_sbyte_d16_hi       dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_load_short_d16          dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_load_short_d16_hi       dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_load_sshort             dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_load_ubyte              dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_load_ubyte_d16          dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_load_ubyte_d16_hi       dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_load_ushort             dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_store_byte              src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_store_byte_d16_hi       src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_store_dword             src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_store_dwordx2           src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_store_dwordx3           src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_store_dwordx4           src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_store_short             src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    global_store_short_d16_hi      src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
-    scratch_load_dword             dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_load_dwordx2           dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_load_dwordx3           dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_load_dwordx4           dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_load_sbyte             dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_load_sbyte_d16         dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_load_sbyte_d16_hi      dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_load_short_d16         dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_load_short_d16_hi      dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_load_sshort            dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_load_ubyte             dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_load_ubyte_d16         dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_load_ubyte_d16_hi      dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_load_ushort            dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_store_byte             src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_store_byte_d16_hi      src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_store_dword            src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_store_dwordx2          src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_store_dwordx3          src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_store_dwordx4          src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_store_short            src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    scratch_store_short_d16_hi     src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-
-MIMG
-===========================
-
-.. parsed-literal::
-
-    image_atomic_add               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_and               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_cmpswap           dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_dec               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_inc               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_or                dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_smax              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_smin              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_sub               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_swap              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_umax              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_umin              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_xor               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4                  dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_b                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_lz             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_cl               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_l                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_lz               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_lz_o             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_o                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_get_lod                  dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_get_resinfo              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load                     dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_load_mip                 dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_load_mip_pck             dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_mip_pck_sgn         dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_pck                 dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_pck_sgn             dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample                   dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_lz              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cl                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_l                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_lz                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_lz_o              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_o                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_store                    src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_store_mip                src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_store_mip_pck            src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_store_pck                src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-
-MUBUF
-===========================
-
-.. parsed-literal::
-
-    buffer_atomic_add              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_add_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_and              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_and_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_cmpswap          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_cmpswap_x2       dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_dec              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_dec_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_inc              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_inc_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_or               dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_or_x2            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smax             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smax_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smin             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smin_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_sub              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_sub_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_swap             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_swap_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umax             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umax_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umin             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umin_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_xor              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_xor_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_dword              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_dwordx2            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_dwordx3            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_dwordx4            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_d16_hi_x    dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_d16_x       dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_d16_xy      dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_d16_xyz     dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_d16_xyzw    dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_x           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_format_xy          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_xyz         dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_xyzw        dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_sbyte              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_sbyte_d16          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_sbyte_d16_hi       dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_short_d16          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_short_d16_hi       dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_sshort             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_ubyte              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_ubyte_d16          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_ubyte_d16_hi       dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_ushort             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_store_byte              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_byte_d16_hi       src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dword             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dwordx2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dwordx3           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dwordx4           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_d16_hi_x   src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_d16_x      src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_d16_xy     src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_d16_xyz    src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_d16_xyzw   src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_x          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_xy         src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_xyz        src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_xyzw       src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_lds_dword         src0, src1                     :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_store_short             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_short_d16_hi      src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_wbinvl1
-    buffer_wbinvl1_vol
-
-SMEM
-===========================
-
-.. parsed-literal::
-
-    s_atc_probe                    src0, src1, src2
-    s_atc_probe_buffer             src0, src1, src2
-    s_atomic_add                   dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_add_x2                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_and                   dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_and_x2                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_cmpswap               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_cmpswap_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_dec                   dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_dec_x2                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_inc                   dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_inc_x2                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_or                    dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_or_x2                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_smax                  dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_smax_x2               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_smin                  dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_smin_x2               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_sub                   dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_sub_x2                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_swap                  dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_swap_x2               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_umax                  dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_umax_x2               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_umin                  dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_umin_x2               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_xor                   dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_atomic_xor_x2                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_add            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_add_x2         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_and            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_and_x2         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_cmpswap        dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_cmpswap_x2     dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_dec            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_dec_x2         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_inc            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_inc_x2         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_or             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_or_x2          dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_smax           dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_smax_x2        dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_smin           dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_smin_x2        dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_sub            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_sub_x2         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_swap           dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_swap_x2        dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_umax           dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_umax_x2        dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_umin           dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_umin_x2        dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_xor            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_atomic_xor_x2         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_load_dword            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_load_dwordx16         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_load_dwordx2          dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_load_dwordx4          dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_load_dwordx8          dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_store_dword           src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_store_dwordx2         src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-    s_buffer_store_dwordx4         src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-    s_dcache_discard               src0, src1
-    s_dcache_discard_x2            src0, src1
-    s_dcache_inv
-    s_dcache_inv_vol
-    s_dcache_wb
-    s_dcache_wb_vol
-    s_load_dword                   dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_load_dwordx16                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_load_dwordx2                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_load_dwordx4                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_load_dwordx8                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_memrealtime                  dst
-    s_memtime                      dst
-    s_scratch_load_dword           dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_scratch_load_dwordx2         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_scratch_load_dwordx4         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
-    s_scratch_store_dword          src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-    s_scratch_store_dwordx2        src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-    s_scratch_store_dwordx4        src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-    s_store_dword                  src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-    s_store_dwordx2                src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-    s_store_dwordx4                src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
-
-SOP1
-===========================
-
-.. parsed-literal::
-
-    s_abs_i32                      dst, src0
-    s_and_saveexec_b64             dst, src0
-    s_andn1_saveexec_b64           dst, src0
-    s_andn1_wrexec_b64             dst, src0
-    s_andn2_saveexec_b64           dst, src0
-    s_andn2_wrexec_b64             dst, src0
-    s_bcnt0_i32_b32                dst, src0
-    s_bcnt0_i32_b64                dst, src0
-    s_bcnt1_i32_b32                dst, src0
-    s_bcnt1_i32_b64                dst, src0
-    s_bitreplicate_b64_b32         dst, src0
-    s_bitset0_b32                  dst, src0
-    s_bitset0_b64                  dst, src0
-    s_bitset1_b32                  dst, src0
-    s_bitset1_b64                  dst, src0
-    s_brev_b32                     dst, src0
-    s_brev_b64                     dst, src0
-    s_cbranch_join                 src0
-    s_cmov_b32                     dst, src0
-    s_cmov_b64                     dst, src0
-    s_ff0_i32_b32                  dst, src0
-    s_ff0_i32_b64                  dst, src0
-    s_ff1_i32_b32                  dst, src0
-    s_ff1_i32_b64                  dst, src0
-    s_flbit_i32                    dst, src0
-    s_flbit_i32_b32                dst, src0
-    s_flbit_i32_b64                dst, src0
-    s_flbit_i32_i64                dst, src0
-    s_getpc_b64                    dst
-    s_mov_b32                      dst, src0
-    s_mov_b64                      dst, src0
-    s_mov_fed_b32                  dst, src0
-    s_movreld_b32                  dst, src0
-    s_movreld_b64                  dst, src0
-    s_movrels_b32                  dst, src0
-    s_movrels_b64                  dst, src0
-    s_nand_saveexec_b64            dst, src0
-    s_nor_saveexec_b64             dst, src0
-    s_not_b32                      dst, src0
-    s_not_b64                      dst, src0
-    s_or_saveexec_b64              dst, src0
-    s_orn1_saveexec_b64            dst, src0
-    s_orn2_saveexec_b64            dst, src0
-    s_quadmask_b32                 dst, src0
-    s_quadmask_b64                 dst, src0
-    s_rfe_b64                      src0
-    s_set_gpr_idx_idx              src0
-    s_setpc_b64                    src0
-    s_sext_i32_i16                 dst, src0
-    s_sext_i32_i8                  dst, src0
-    s_swappc_b64                   dst, src0
-    s_wqm_b32                      dst, src0
-    s_wqm_b64                      dst, src0
-    s_xnor_saveexec_b64            dst, src0
-    s_xor_saveexec_b64             dst, src0
-
-SOP2
-===========================
-
-.. parsed-literal::
-
-    s_absdiff_i32                  dst, src0, src1
-    s_add_i32                      dst, src0, src1
-    s_add_u32                      dst, src0, src1
-    s_addc_u32                     dst, src0, src1
-    s_and_b32                      dst, src0, src1
-    s_and_b64                      dst, src0, src1
-    s_andn2_b32                    dst, src0, src1
-    s_andn2_b64                    dst, src0, src1
-    s_ashr_i32                     dst, src0, src1
-    s_ashr_i64                     dst, src0, src1
-    s_bfe_i32                      dst, src0, src1
-    s_bfe_i64                      dst, src0, src1
-    s_bfe_u32                      dst, src0, src1
-    s_bfe_u64                      dst, src0, src1
-    s_bfm_b32                      dst, src0, src1
-    s_bfm_b64                      dst, src0, src1
-    s_cbranch_g_fork               src0, src1
-    s_cselect_b32                  dst, src0, src1
-    s_cselect_b64                  dst, src0, src1
-    s_lshl1_add_u32                dst, src0, src1
-    s_lshl2_add_u32                dst, src0, src1
-    s_lshl3_add_u32                dst, src0, src1
-    s_lshl4_add_u32                dst, src0, src1
-    s_lshl_b32                     dst, src0, src1
-    s_lshl_b64                     dst, src0, src1
-    s_lshr_b32                     dst, src0, src1
-    s_lshr_b64                     dst, src0, src1
-    s_max_i32                      dst, src0, src1
-    s_max_u32                      dst, src0, src1
-    s_min_i32                      dst, src0, src1
-    s_min_u32                      dst, src0, src1
-    s_mul_hi_i32                   dst, src0, src1
-    s_mul_hi_u32                   dst, src0, src1
-    s_mul_i32                      dst, src0, src1
-    s_nand_b32                     dst, src0, src1
-    s_nand_b64                     dst, src0, src1
-    s_nor_b32                      dst, src0, src1
-    s_nor_b64                      dst, src0, src1
-    s_or_b32                       dst, src0, src1
-    s_or_b64                       dst, src0, src1
-    s_orn2_b32                     dst, src0, src1
-    s_orn2_b64                     dst, src0, src1
-    s_pack_hh_b32_b16              dst, src0, src1
-    s_pack_lh_b32_b16              dst, src0, src1
-    s_pack_ll_b32_b16              dst, src0, src1
-    s_rfe_restore_b64              src0, src1
-    s_sub_i32                      dst, src0, src1
-    s_sub_u32                      dst, src0, src1
-    s_subb_u32                     dst, src0, src1
-    s_xnor_b32                     dst, src0, src1
-    s_xnor_b64                     dst, src0, src1
-    s_xor_b32                      dst, src0, src1
-    s_xor_b64                      dst, src0, src1
-
-SOPC
-===========================
-
-.. parsed-literal::
-
-    s_bitcmp0_b32                  src0, src1
-    s_bitcmp0_b64                  src0, src1
-    s_bitcmp1_b32                  src0, src1
-    s_bitcmp1_b64                  src0, src1
-    s_cmp_eq_i32                   src0, src1
-    s_cmp_eq_u32                   src0, src1
-    s_cmp_eq_u64                   src0, src1
-    s_cmp_ge_i32                   src0, src1
-    s_cmp_ge_u32                   src0, src1
-    s_cmp_gt_i32                   src0, src1
-    s_cmp_gt_u32                   src0, src1
-    s_cmp_le_i32                   src0, src1
-    s_cmp_le_u32                   src0, src1
-    s_cmp_lg_i32                   src0, src1
-    s_cmp_lg_u32                   src0, src1
-    s_cmp_lg_u64                   src0, src1
-    s_cmp_lt_i32                   src0, src1
-    s_cmp_lt_u32                   src0, src1
-    s_set_gpr_idx_on               src0, src1
-    s_setvskip                     src0, src1
-
-SOPK
-===========================
-
-.. parsed-literal::
-
-    s_addk_i32                     dst, src0
-    s_call_b64                     dst, src0
-    s_cbranch_i_fork               src0, src1
-    s_cmovk_i32                    dst, src0
-    s_cmpk_eq_i32                  src0, src1
-    s_cmpk_eq_u32                  src0, src1
-    s_cmpk_ge_i32                  src0, src1
-    s_cmpk_ge_u32                  src0, src1
-    s_cmpk_gt_i32                  src0, src1
-    s_cmpk_gt_u32                  src0, src1
-    s_cmpk_le_i32                  src0, src1
-    s_cmpk_le_u32                  src0, src1
-    s_cmpk_lg_i32                  src0, src1
-    s_cmpk_lg_u32                  src0, src1
-    s_cmpk_lt_i32                  src0, src1
-    s_cmpk_lt_u32                  src0, src1
-    s_getreg_b32                   dst, src0
-    s_movk_i32                     dst, src0
-    s_mulk_i32                     dst, src0
-    s_setreg_b32                   dst, src0
-    s_setreg_imm32_b32             dst, src0
-
-SOPP
-===========================
-
-.. parsed-literal::
-
-    s_barrier
-    s_branch                       src0
-    s_cbranch_cdbgsys              src0
-    s_cbranch_cdbgsys_and_user     src0
-    s_cbranch_cdbgsys_or_user      src0
-    s_cbranch_cdbguser             src0
-    s_cbranch_execnz               src0
-    s_cbranch_execz                src0
-    s_cbranch_scc0                 src0
-    s_cbranch_scc1                 src0
-    s_cbranch_vccnz                src0
-    s_cbranch_vccz                 src0
-    s_decperflevel                 src0
-    s_endpgm
-    s_endpgm_ordered_ps_done
-    s_endpgm_saved
-    s_icache_inv
-    s_incperflevel                 src0
-    s_nop                          src0
-    s_sendmsg                      src0
-    s_sendmsghalt                  src0
-    s_set_gpr_idx_mode             src0
-    s_set_gpr_idx_off
-    s_sethalt                      src0
-    s_setkill                      src0
-    s_setprio                      src0
-    s_sleep                        src0
-    s_trap                         src0
-    s_ttracedata
-    s_waitcnt                      src0
-    s_wakeup
-
-VINTRP
-===========================
-
-.. parsed-literal::
-
-    v_interp_mov_f32               dst, src0, src1
-    v_interp_p1_f32                dst, src0, src1
-    v_interp_p2_f32                dst, src0, src1
-
-VOP1
-===========================
-
-.. parsed-literal::
-
-    v_bfrev_b32                    dst, src0
-    v_bfrev_b32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_bfrev_b32_sdwa               dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_ceil_f16                     dst, src0
-    v_ceil_f16_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ceil_f16_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_ceil_f32                     dst, src0
-    v_ceil_f32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ceil_f32_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_ceil_f64                     dst, src0
-    v_clrexcp
-    v_cos_f16                      dst, src0
-    v_cos_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cos_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cos_f32                      dst, src0
-    v_cos_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cos_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f16_f32                  dst, src0
-    v_cvt_f16_f32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f16_f32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f16_i16                  dst, src0
-    v_cvt_f16_i16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f16_i16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f16_u16                  dst, src0
-    v_cvt_f16_u16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f16_u16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f32_f16                  dst, src0
-    v_cvt_f32_f16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f32_f16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f32_f64                  dst, src0
-    v_cvt_f32_i32                  dst, src0
-    v_cvt_f32_i32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f32_i32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f32_u32                  dst, src0
-    v_cvt_f32_u32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f32_u32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f32_ubyte0               dst, src0
-    v_cvt_f32_ubyte0_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f32_ubyte0_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f32_ubyte1               dst, src0
-    v_cvt_f32_ubyte1_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f32_ubyte1_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f32_ubyte2               dst, src0
-    v_cvt_f32_ubyte2_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f32_ubyte2_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f32_ubyte3               dst, src0
-    v_cvt_f32_ubyte3_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f32_ubyte3_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f64_f32                  dst, src0
-    v_cvt_f64_i32                  dst, src0
-    v_cvt_f64_u32                  dst, src0
-    v_cvt_flr_i32_f32              dst, src0
-    v_cvt_flr_i32_f32_dpp          dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_flr_i32_f32_sdwa         dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_i16_f16                  dst, src0
-    v_cvt_i16_f16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_i16_f16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_i32_f32                  dst, src0
-    v_cvt_i32_f32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_i32_f32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_i32_f64                  dst, src0
-    v_cvt_norm_i16_f16             dst, src0
-    v_cvt_norm_i16_f16_dpp         dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_norm_i16_f16_sdwa        dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_norm_u16_f16             dst, src0
-    v_cvt_norm_u16_f16_dpp         dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_norm_u16_f16_sdwa        dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_off_f32_i4               dst, src0
-    v_cvt_off_f32_i4_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_off_f32_i4_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_rpi_i32_f32              dst, src0
-    v_cvt_rpi_i32_f32_dpp          dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_rpi_i32_f32_sdwa         dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_u16_f16                  dst, src0
-    v_cvt_u16_f16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_u16_f16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_u32_f32                  dst, src0
-    v_cvt_u32_f32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_u32_f32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_u32_f64                  dst, src0
-    v_exp_f16                      dst, src0
-    v_exp_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_exp_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_exp_f32                      dst, src0
-    v_exp_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_exp_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_exp_legacy_f32               dst, src0
-    v_exp_legacy_f32_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_exp_legacy_f32_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_ffbh_i32                     dst, src0
-    v_ffbh_i32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ffbh_i32_sdwa                dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_ffbh_u32                     dst, src0
-    v_ffbh_u32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ffbh_u32_sdwa                dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_ffbl_b32                     dst, src0
-    v_ffbl_b32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ffbl_b32_sdwa                dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_floor_f16                    dst, src0
-    v_floor_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_floor_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_floor_f32                    dst, src0
-    v_floor_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_floor_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_floor_f64                    dst, src0
-    v_fract_f16                    dst, src0
-    v_fract_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_fract_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_fract_f32                    dst, src0
-    v_fract_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_fract_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_fract_f64                    dst, src0
-    v_frexp_exp_i16_f16            dst, src0
-    v_frexp_exp_i16_f16_dpp        dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_frexp_exp_i16_f16_sdwa       dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_frexp_exp_i32_f32            dst, src0
-    v_frexp_exp_i32_f32_dpp        dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_frexp_exp_i32_f32_sdwa       dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_frexp_exp_i32_f64            dst, src0
-    v_frexp_mant_f16               dst, src0
-    v_frexp_mant_f16_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_frexp_mant_f16_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_frexp_mant_f32               dst, src0
-    v_frexp_mant_f32_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_frexp_mant_f32_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_frexp_mant_f64               dst, src0
-    v_log_f16                      dst, src0
-    v_log_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_log_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_log_f32                      dst, src0
-    v_log_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_log_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_log_legacy_f32               dst, src0
-    v_log_legacy_f32_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_log_legacy_f32_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_mov_b32                      dst, src0
-    v_mov_b32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mov_b32_sdwa                 dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_mov_fed_b32                  dst, src0
-    v_mov_fed_b32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mov_fed_b32_sdwa             dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_nop
-    v_not_b32                      dst, src0
-    v_not_b32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_not_b32_sdwa                 dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_rcp_f16                      dst, src0
-    v_rcp_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_rcp_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_rcp_f32                      dst, src0
-    v_rcp_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_rcp_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_rcp_f64                      dst, src0
-    v_rcp_iflag_f32                dst, src0
-    v_rcp_iflag_f32_dpp            dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_rcp_iflag_f32_sdwa           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_readfirstlane_b32            dst, src0
-    v_rndne_f16                    dst, src0
-    v_rndne_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_rndne_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_rndne_f32                    dst, src0
-    v_rndne_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_rndne_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_rndne_f64                    dst, src0
-    v_rsq_f16                      dst, src0
-    v_rsq_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_rsq_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_rsq_f32                      dst, src0
-    v_rsq_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_rsq_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_rsq_f64                      dst, src0
-    v_sat_pk_u8_i16                dst, src0
-    v_sat_pk_u8_i16_dpp            dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sat_pk_u8_i16_sdwa           dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_screen_partition_4se_b32     dst, src0
-    v_screen_partition_4se_b32_dpp dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_screen_partition_4se_b32_sdwa dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_sin_f16                      dst, src0
-    v_sin_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sin_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_sin_f32                      dst, src0
-    v_sin_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sin_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_sqrt_f16                     dst, src0
-    v_sqrt_f16_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sqrt_f16_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_sqrt_f32                     dst, src0
-    v_sqrt_f32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sqrt_f32_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_sqrt_f64                     dst, src0
-    v_swap_b32                     dst, src0
-    v_trunc_f16                    dst, src0
-    v_trunc_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_trunc_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_trunc_f32                    dst, src0
-    v_trunc_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_trunc_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_trunc_f64                    dst, src0
-
-VOP2
-===========================
-
-.. parsed-literal::
-
-    v_add_co_u32                   dst0, dst1, src0, src1
-    v_add_co_u32_dpp               dst0, dst1, src0, src1         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_add_co_u32_sdwa              dst0, dst1, src0, src1         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_add_f16                      dst, src0, src1
-    v_add_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_add_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_add_f32                      dst, src0, src1
-    v_add_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_add_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_add_u16                      dst, src0, src1
-    v_add_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_add_u16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_add_u32                      dst, src0, src1
-    v_add_u32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_add_u32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_addc_co_u32                  dst0, dst1, src0, src1, src2
-    v_addc_co_u32_dpp              dst0, dst1, src0, src1, src2   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_addc_co_u32_sdwa             dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_and_b32                      dst, src0, src1
-    v_and_b32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_and_b32_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_ashrrev_i16                  dst, src0, src1
-    v_ashrrev_i16_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ashrrev_i16_sdwa             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_ashrrev_i32                  dst, src0, src1
-    v_ashrrev_i32_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ashrrev_i32_sdwa             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cndmask_b32                  dst, src0, src1, src2
-    v_cndmask_b32_dpp              dst, src0, src1, src2          :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cndmask_b32_sdwa             dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_ldexp_f16                    dst, src0, src1
-    v_ldexp_f16_dpp                dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ldexp_f16_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshlrev_b16                  dst, src0, src1
-    v_lshlrev_b16_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshlrev_b16_sdwa             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshlrev_b32                  dst, src0, src1
-    v_lshlrev_b32_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshlrev_b32_sdwa             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshrrev_b16                  dst, src0, src1
-    v_lshrrev_b16_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshrrev_b16_sdwa             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshrrev_b32                  dst, src0, src1
-    v_lshrrev_b32_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshrrev_b32_sdwa             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mac_f16                      dst, src0, src1
-    v_mac_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mac_f32                      dst, src0, src1
-    v_mac_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_madak_f16                    dst, src0, src1, src2
-    v_madak_f32                    dst, src0, src1, src2
-    v_madmk_f16                    dst, src0, src1, src2
-    v_madmk_f32                    dst, src0, src1, src2
-    v_max_f16                      dst, src0, src1
-    v_max_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_max_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_max_f32                      dst, src0, src1
-    v_max_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_max_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_max_i16                      dst, src0, src1
-    v_max_i16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_max_i16_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_max_i32                      dst, src0, src1
-    v_max_i32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_max_i32_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_max_u16                      dst, src0, src1
-    v_max_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_max_u16_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_max_u32                      dst, src0, src1
-    v_max_u32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_max_u32_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_f16                      dst, src0, src1
-    v_min_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_min_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_f32                      dst, src0, src1
-    v_min_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_min_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_i16                      dst, src0, src1
-    v_min_i16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_min_i16_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_i32                      dst, src0, src1
-    v_min_i32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_min_i32_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_u16                      dst, src0, src1
-    v_min_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_min_u16_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_u32                      dst, src0, src1
-    v_min_u32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_min_u32_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_f16                      dst, src0, src1
-    v_mul_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_f32                      dst, src0, src1
-    v_mul_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_hi_i32_i24               dst, src0, src1
-    v_mul_hi_i32_i24_dpp           dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_hi_i32_i24_sdwa          dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_hi_u32_u24               dst, src0, src1
-    v_mul_hi_u32_u24_dpp           dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_hi_u32_u24_sdwa          dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_i32_i24                  dst, src0, src1
-    v_mul_i32_i24_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_i32_i24_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_legacy_f32               dst, src0, src1
-    v_mul_legacy_f32_dpp           dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_legacy_f32_sdwa          dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_lo_u16                   dst, src0, src1
-    v_mul_lo_u16_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_lo_u16_sdwa              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_u32_u24                  dst, src0, src1
-    v_mul_u32_u24_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_u32_u24_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_or_b32                       dst, src0, src1
-    v_or_b32_dpp                   dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_or_b32_sdwa                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_sub_co_u32                   dst0, dst1, src0, src1
-    v_sub_co_u32_dpp               dst0, dst1, src0, src1         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sub_co_u32_sdwa              dst0, dst1, src0, src1         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_sub_f16                      dst, src0, src1
-    v_sub_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sub_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_sub_f32                      dst, src0, src1
-    v_sub_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sub_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_sub_u16                      dst, src0, src1
-    v_sub_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sub_u16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_sub_u32                      dst, src0, src1
-    v_sub_u32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sub_u32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subb_co_u32                  dst0, dst1, src0, src1, src2
-    v_subb_co_u32_dpp              dst0, dst1, src0, src1, src2   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subb_co_u32_sdwa             dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subbrev_co_u32               dst0, dst1, src0, src1, src2
-    v_subbrev_co_u32_dpp           dst0, dst1, src0, src1, src2   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subbrev_co_u32_sdwa          dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_co_u32                dst0, dst1, src0, src1
-    v_subrev_co_u32_dpp            dst0, dst1, src0, src1         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_co_u32_sdwa           dst0, dst1, src0, src1         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_f16                   dst, src0, src1
-    v_subrev_f16_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_f32                   dst, src0, src1
-    v_subrev_f32_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_u16                   dst, src0, src1
-    v_subrev_u16_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_u16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_u32                   dst, src0, src1
-    v_subrev_u32_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_u32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_xor_b32                      dst, src0, src1
-    v_xor_b32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_xor_b32_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-
-VOP3
-===========================
-
-.. parsed-literal::
-
-    v_add3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_add_co_u32_e64               dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
-    v_add_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_i16                      dst, src0, src1                :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_i32                      dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_add_lshl_u32                 dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_add_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_add_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_addc_co_u32_e64              dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_alignbit_b32                 dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
-    v_alignbyte_b32                dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
-    v_and_b32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_and_or_b32                   dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_ashrrev_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_ashrrev_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_ashrrev_i64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_bcnt_u32_b32                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_bfe_i32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_bfe_u32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_bfi_b32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_bfm_b32                      dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_bfrev_b32_e64                dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_ceil_f16_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ceil_f32_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ceil_f64_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_clrexcp_e64                                                 :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_class_f16_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_class_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_class_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_eq_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_f32_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_f64_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_i16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_i32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_i64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_u16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_u32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_f_u64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ge_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_gt_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_le_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lg_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lg_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lg_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_lt_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ne_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_neq_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_neq_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_neq_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nge_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nge_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nge_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ngt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ngt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_ngt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nle_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nle_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nle_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlg_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlg_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlg_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_nlt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_o_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_o_f32_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_o_f64_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_i16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_i32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_i64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_u16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_u32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_t_u64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_tru_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_tru_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_tru_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_u_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_u_f32_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmp_u_f64_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_class_f16_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_class_f32_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_class_f64_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_eq_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_f_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ge_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_gt_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_le_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lg_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lg_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lg_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_lt_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ne_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_neq_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_neq_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_neq_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nge_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nge_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nge_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ngt_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ngt_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_ngt_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nle_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nle_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nle_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlg_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlg_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlg_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlt_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlt_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_nlt_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_o_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_o_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_o_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_t_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_tru_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_tru_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_tru_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_u_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_u_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cmpx_u_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cndmask_b32_e64              dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_cos_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cos_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubeid_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubema_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubesc_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubetc_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_f32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_i16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_u16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_f16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_f64_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_i32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_u32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte0_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte1_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte2_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte3_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_f32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_i32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_u32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_flr_i32_f32_e64          dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_i16_f16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_i32_f32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_i32_f64_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_norm_i16_f16_e64         dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_norm_u16_f16_e64         dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_off_f32_i4_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_i16_i32               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_u16_u32               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_u8_f32                dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pkaccum_u8_f32           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pknorm_i16_f16           dst, src0, src1                :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pknorm_i16_f32           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pknorm_u16_f16           dst, src0, src1                :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pknorm_u16_f32           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pkrtz_f16_f32            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_rpi_i32_f32_e64          dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_u16_f16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_u32_f32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_u32_f64_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fixup_f16                dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fixup_f32                dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fixup_f64                dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fixup_legacy_f16         dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fmas_f32                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fmas_f64                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_scale_f32                dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_div_scale_f64                dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_exp_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_exp_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_exp_legacy_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ffbh_i32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_ffbh_u32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_ffbl_b32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_floor_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_floor_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_floor_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_f16                      dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_f32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_f64                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_legacy_f16               dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fract_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fract_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fract_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_exp_i16_f16_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_exp_i32_f32_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_exp_i32_f64_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_mant_f16_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_mant_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_mant_f64_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_interp_mov_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_interp_p1_f32_e64            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_interp_p1ll_f16              dst, src0, src1                :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_interp_p1lv_f16              dst, src0, src1, src2          :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_interp_p2_f16                dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_interp_p2_f32_e64            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_interp_p2_legacy_f16         dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f32                    dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f64                    dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lerp_u8                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_log_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_log_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_log_legacy_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lshl_add_u32                 dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_lshl_or_b32                  dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_lshlrev_b16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshlrev_b32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshlrev_b64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshrrev_b16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshrrev_b32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_lshrrev_b64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mac_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mac_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_f16                      dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_f32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i16                      dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i32_i16                  dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i32_i24                  dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i64_i32                  dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_legacy_f16               dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_legacy_f32               dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_legacy_i16               dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_legacy_u16               dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_u16                      dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_u32_u16                  dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_u32_u24                  dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_u64_u32                  dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max3_f16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max3_i16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
-    v_max3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_max3_u16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
-    v_max3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_max_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_i16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_max_i32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_max_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_max_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mbcnt_hi_u32_b32             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mbcnt_lo_u32_b32             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_med3_f16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_med3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_med3_i16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
-    v_med3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_med3_u16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
-    v_med3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_min3_f16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min3_i16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
-    v_min3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_min3_u16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
-    v_min3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_min_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_i16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_min_i32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_min_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_min_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mov_b32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_mov_fed_b32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_mqsad_pk_u16_u8              dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mqsad_u32_u8                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_msad_u8                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_i32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_i32_i24_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_u32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_u32_u24_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_i32_i24_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_legacy_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_lo_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_lo_u32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_mul_u32_u24_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_nop_e64                                                     :ref:`omod<amdgpu_synid_omod>`
-    v_not_b32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_or3_b32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_or_b32_e64                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_pack_b32_f16                 dst, src0, src1                :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
-    v_perm_b32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_qsad_pk_u16_u8               dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_f64_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_iflag_f32_e64            dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_readlane_b32                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_rndne_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rndne_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rndne_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_f64_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_hi_u8                    dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_u16                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_u32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_u8                       dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sat_pk_u8_i16_e64            dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_screen_partition_4se_b32_e64 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
-    v_sin_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sin_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sqrt_f16_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sqrt_f32_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sqrt_f64_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_co_u32_e64               dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
-    v_sub_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_i16                      dst, src0, src1                :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_i32                      dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_sub_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_sub_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_subb_co_u32_e64              dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_subbrev_co_u32_e64           dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_co_u32_e64            dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_trig_preop_f64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_trunc_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_trunc_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_trunc_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_writelane_b32                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-    v_xad_u32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
-    v_xor_b32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
-
-VOP3P
-===========================
-
-.. parsed-literal::
-
-    v_mad_mix_f32                  dst, src0, src1, src2          :ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_mixhi_f16                dst, src0, src1, src2          :ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_mixlo_f16                dst, src0, src1, src2          :ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_add_f16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_add_i16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_add_u16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_ashrrev_i16               dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_fma_f16                   dst, src0, src1, src2          :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_lshlrev_b16               dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_lshrrev_b16               dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_mad_i16                   dst, src0, src1, src2          :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_mad_u16                   dst, src0, src1, src2          :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_max_f16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_max_i16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_max_u16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_min_f16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_min_i16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_min_u16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_mul_f16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_mul_lo_u16                dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_sub_i16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_sub_u16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-
-VOPC
-===========================
-
-.. parsed-literal::
-
-    v_cmp_class_f16                dst, src0, src1
-    v_cmp_class_f16_sdwa           dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_class_f32                dst, src0, src1
-    v_cmp_class_f32_sdwa           dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_class_f64                dst, src0, src1
-    v_cmp_eq_f16                   dst, src0, src1
-    v_cmp_eq_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_eq_f32                   dst, src0, src1
-    v_cmp_eq_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_eq_f64                   dst, src0, src1
-    v_cmp_eq_i16                   dst, src0, src1
-    v_cmp_eq_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_eq_i32                   dst, src0, src1
-    v_cmp_eq_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_eq_i64                   dst, src0, src1
-    v_cmp_eq_u16                   dst, src0, src1
-    v_cmp_eq_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_eq_u32                   dst, src0, src1
-    v_cmp_eq_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_eq_u64                   dst, src0, src1
-    v_cmp_f_f16                    dst, src0, src1
-    v_cmp_f_f16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_f_f32                    dst, src0, src1
-    v_cmp_f_f32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_f_f64                    dst, src0, src1
-    v_cmp_f_i16                    dst, src0, src1
-    v_cmp_f_i16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_f_i32                    dst, src0, src1
-    v_cmp_f_i32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_f_i64                    dst, src0, src1
-    v_cmp_f_u16                    dst, src0, src1
-    v_cmp_f_u16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_f_u32                    dst, src0, src1
-    v_cmp_f_u32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_f_u64                    dst, src0, src1
-    v_cmp_ge_f16                   dst, src0, src1
-    v_cmp_ge_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ge_f32                   dst, src0, src1
-    v_cmp_ge_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ge_f64                   dst, src0, src1
-    v_cmp_ge_i16                   dst, src0, src1
-    v_cmp_ge_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ge_i32                   dst, src0, src1
-    v_cmp_ge_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ge_i64                   dst, src0, src1
-    v_cmp_ge_u16                   dst, src0, src1
-    v_cmp_ge_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ge_u32                   dst, src0, src1
-    v_cmp_ge_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ge_u64                   dst, src0, src1
-    v_cmp_gt_f16                   dst, src0, src1
-    v_cmp_gt_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_gt_f32                   dst, src0, src1
-    v_cmp_gt_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_gt_f64                   dst, src0, src1
-    v_cmp_gt_i16                   dst, src0, src1
-    v_cmp_gt_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_gt_i32                   dst, src0, src1
-    v_cmp_gt_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_gt_i64                   dst, src0, src1
-    v_cmp_gt_u16                   dst, src0, src1
-    v_cmp_gt_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_gt_u32                   dst, src0, src1
-    v_cmp_gt_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_gt_u64                   dst, src0, src1
-    v_cmp_le_f16                   dst, src0, src1
-    v_cmp_le_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_le_f32                   dst, src0, src1
-    v_cmp_le_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_le_f64                   dst, src0, src1
-    v_cmp_le_i16                   dst, src0, src1
-    v_cmp_le_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_le_i32                   dst, src0, src1
-    v_cmp_le_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_le_i64                   dst, src0, src1
-    v_cmp_le_u16                   dst, src0, src1
-    v_cmp_le_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_le_u32                   dst, src0, src1
-    v_cmp_le_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_le_u64                   dst, src0, src1
-    v_cmp_lg_f16                   dst, src0, src1
-    v_cmp_lg_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lg_f32                   dst, src0, src1
-    v_cmp_lg_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lg_f64                   dst, src0, src1
-    v_cmp_lt_f16                   dst, src0, src1
-    v_cmp_lt_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lt_f32                   dst, src0, src1
-    v_cmp_lt_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lt_f64                   dst, src0, src1
-    v_cmp_lt_i16                   dst, src0, src1
-    v_cmp_lt_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lt_i32                   dst, src0, src1
-    v_cmp_lt_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lt_i64                   dst, src0, src1
-    v_cmp_lt_u16                   dst, src0, src1
-    v_cmp_lt_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lt_u32                   dst, src0, src1
-    v_cmp_lt_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lt_u64                   dst, src0, src1
-    v_cmp_ne_i16                   dst, src0, src1
-    v_cmp_ne_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ne_i32                   dst, src0, src1
-    v_cmp_ne_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ne_i64                   dst, src0, src1
-    v_cmp_ne_u16                   dst, src0, src1
-    v_cmp_ne_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ne_u32                   dst, src0, src1
-    v_cmp_ne_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ne_u64                   dst, src0, src1
-    v_cmp_neq_f16                  dst, src0, src1
-    v_cmp_neq_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_neq_f32                  dst, src0, src1
-    v_cmp_neq_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_neq_f64                  dst, src0, src1
-    v_cmp_nge_f16                  dst, src0, src1
-    v_cmp_nge_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nge_f32                  dst, src0, src1
-    v_cmp_nge_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nge_f64                  dst, src0, src1
-    v_cmp_ngt_f16                  dst, src0, src1
-    v_cmp_ngt_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ngt_f32                  dst, src0, src1
-    v_cmp_ngt_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ngt_f64                  dst, src0, src1
-    v_cmp_nle_f16                  dst, src0, src1
-    v_cmp_nle_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nle_f32                  dst, src0, src1
-    v_cmp_nle_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nle_f64                  dst, src0, src1
-    v_cmp_nlg_f16                  dst, src0, src1
-    v_cmp_nlg_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nlg_f32                  dst, src0, src1
-    v_cmp_nlg_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nlg_f64                  dst, src0, src1
-    v_cmp_nlt_f16                  dst, src0, src1
-    v_cmp_nlt_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nlt_f32                  dst, src0, src1
-    v_cmp_nlt_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_nlt_f64                  dst, src0, src1
-    v_cmp_o_f16                    dst, src0, src1
-    v_cmp_o_f16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_o_f32                    dst, src0, src1
-    v_cmp_o_f32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_o_f64                    dst, src0, src1
-    v_cmp_t_i16                    dst, src0, src1
-    v_cmp_t_i16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_t_i32                    dst, src0, src1
-    v_cmp_t_i32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_t_i64                    dst, src0, src1
-    v_cmp_t_u16                    dst, src0, src1
-    v_cmp_t_u16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_t_u32                    dst, src0, src1
-    v_cmp_t_u32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_t_u64                    dst, src0, src1
-    v_cmp_tru_f16                  dst, src0, src1
-    v_cmp_tru_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_tru_f32                  dst, src0, src1
-    v_cmp_tru_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_tru_f64                  dst, src0, src1
-    v_cmp_u_f16                    dst, src0, src1
-    v_cmp_u_f16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_u_f32                    dst, src0, src1
-    v_cmp_u_f32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_u_f64                    dst, src0, src1
-    v_cmpx_class_f16               dst, src0, src1
-    v_cmpx_class_f16_sdwa          dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_class_f32               dst, src0, src1
-    v_cmpx_class_f32_sdwa          dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_class_f64               dst, src0, src1
-    v_cmpx_eq_f16                  dst, src0, src1
-    v_cmpx_eq_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_eq_f32                  dst, src0, src1
-    v_cmpx_eq_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_eq_f64                  dst, src0, src1
-    v_cmpx_eq_i16                  dst, src0, src1
-    v_cmpx_eq_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_eq_i32                  dst, src0, src1
-    v_cmpx_eq_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_eq_i64                  dst, src0, src1
-    v_cmpx_eq_u16                  dst, src0, src1
-    v_cmpx_eq_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_eq_u32                  dst, src0, src1
-    v_cmpx_eq_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_eq_u64                  dst, src0, src1
-    v_cmpx_f_f16                   dst, src0, src1
-    v_cmpx_f_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_f_f32                   dst, src0, src1
-    v_cmpx_f_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_f_f64                   dst, src0, src1
-    v_cmpx_f_i16                   dst, src0, src1
-    v_cmpx_f_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_f_i32                   dst, src0, src1
-    v_cmpx_f_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_f_i64                   dst, src0, src1
-    v_cmpx_f_u16                   dst, src0, src1
-    v_cmpx_f_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_f_u32                   dst, src0, src1
-    v_cmpx_f_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_f_u64                   dst, src0, src1
-    v_cmpx_ge_f16                  dst, src0, src1
-    v_cmpx_ge_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ge_f32                  dst, src0, src1
-    v_cmpx_ge_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ge_f64                  dst, src0, src1
-    v_cmpx_ge_i16                  dst, src0, src1
-    v_cmpx_ge_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ge_i32                  dst, src0, src1
-    v_cmpx_ge_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ge_i64                  dst, src0, src1
-    v_cmpx_ge_u16                  dst, src0, src1
-    v_cmpx_ge_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ge_u32                  dst, src0, src1
-    v_cmpx_ge_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ge_u64                  dst, src0, src1
-    v_cmpx_gt_f16                  dst, src0, src1
-    v_cmpx_gt_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_gt_f32                  dst, src0, src1
-    v_cmpx_gt_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_gt_f64                  dst, src0, src1
-    v_cmpx_gt_i16                  dst, src0, src1
-    v_cmpx_gt_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_gt_i32                  dst, src0, src1
-    v_cmpx_gt_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_gt_i64                  dst, src0, src1
-    v_cmpx_gt_u16                  dst, src0, src1
-    v_cmpx_gt_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_gt_u32                  dst, src0, src1
-    v_cmpx_gt_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_gt_u64                  dst, src0, src1
-    v_cmpx_le_f16                  dst, src0, src1
-    v_cmpx_le_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_le_f32                  dst, src0, src1
-    v_cmpx_le_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_le_f64                  dst, src0, src1
-    v_cmpx_le_i16                  dst, src0, src1
-    v_cmpx_le_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_le_i32                  dst, src0, src1
-    v_cmpx_le_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_le_i64                  dst, src0, src1
-    v_cmpx_le_u16                  dst, src0, src1
-    v_cmpx_le_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_le_u32                  dst, src0, src1
-    v_cmpx_le_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_le_u64                  dst, src0, src1
-    v_cmpx_lg_f16                  dst, src0, src1
-    v_cmpx_lg_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lg_f32                  dst, src0, src1
-    v_cmpx_lg_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lg_f64                  dst, src0, src1
-    v_cmpx_lt_f16                  dst, src0, src1
-    v_cmpx_lt_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lt_f32                  dst, src0, src1
-    v_cmpx_lt_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lt_f64                  dst, src0, src1
-    v_cmpx_lt_i16                  dst, src0, src1
-    v_cmpx_lt_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lt_i32                  dst, src0, src1
-    v_cmpx_lt_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lt_i64                  dst, src0, src1
-    v_cmpx_lt_u16                  dst, src0, src1
-    v_cmpx_lt_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lt_u32                  dst, src0, src1
-    v_cmpx_lt_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lt_u64                  dst, src0, src1
-    v_cmpx_ne_i16                  dst, src0, src1
-    v_cmpx_ne_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ne_i32                  dst, src0, src1
-    v_cmpx_ne_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ne_i64                  dst, src0, src1
-    v_cmpx_ne_u16                  dst, src0, src1
-    v_cmpx_ne_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ne_u32                  dst, src0, src1
-    v_cmpx_ne_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ne_u64                  dst, src0, src1
-    v_cmpx_neq_f16                 dst, src0, src1
-    v_cmpx_neq_f16_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_neq_f32                 dst, src0, src1
-    v_cmpx_neq_f32_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_neq_f64                 dst, src0, src1
-    v_cmpx_nge_f16                 dst, src0, src1
-    v_cmpx_nge_f16_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nge_f32                 dst, src0, src1
-    v_cmpx_nge_f32_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nge_f64                 dst, src0, src1
-    v_cmpx_ngt_f16                 dst, src0, src1
-    v_cmpx_ngt_f16_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ngt_f32                 dst, src0, src1
-    v_cmpx_ngt_f32_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ngt_f64                 dst, src0, src1
-    v_cmpx_nle_f16                 dst, src0, src1
-    v_cmpx_nle_f16_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nle_f32                 dst, src0, src1
-    v_cmpx_nle_f32_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nle_f64                 dst, src0, src1
-    v_cmpx_nlg_f16                 dst, src0, src1
-    v_cmpx_nlg_f16_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nlg_f32                 dst, src0, src1
-    v_cmpx_nlg_f32_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nlg_f64                 dst, src0, src1
-    v_cmpx_nlt_f16                 dst, src0, src1
-    v_cmpx_nlt_f16_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nlt_f32                 dst, src0, src1
-    v_cmpx_nlt_f32_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_nlt_f64                 dst, src0, src1
-    v_cmpx_o_f16                   dst, src0, src1
-    v_cmpx_o_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_o_f32                   dst, src0, src1
-    v_cmpx_o_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_o_f64                   dst, src0, src1
-    v_cmpx_t_i16                   dst, src0, src1
-    v_cmpx_t_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_t_i32                   dst, src0, src1
-    v_cmpx_t_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_t_i64                   dst, src0, src1
-    v_cmpx_t_u16                   dst, src0, src1
-    v_cmpx_t_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_t_u32                   dst, src0, src1
-    v_cmpx_t_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_t_u64                   dst, src0, src1
-    v_cmpx_tru_f16                 dst, src0, src1
-    v_cmpx_tru_f16_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_tru_f32                 dst, src0, src1
-    v_cmpx_tru_f32_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_tru_f64                 dst, src0, src1
-    v_cmpx_u_f16                   dst, src0, src1
-    v_cmpx_u_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_u_f32                   dst, src0, src1
-    v_cmpx_u_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_u_f64                   dst, src0, src1

diff --git a/docs/AMDGPUInstructionNotation.rst b/docs/AMDGPUInstructionNotation.rst
new file mode 100644 (file)
index 0000000..a2b617c
--- /dev/null
+++ b/docs/AMDGPUInstructionNotation.rst
@@ -0,0 +1,110 @@
+============================
+AMDGPU Instructions Notation
+============================
+
+.. contents::
+   :local:
+
+.. _amdgpu_syn_instruction_notation:
+
+Introduction
+============
+
+This is an overview of notation used to describe the syntax of AMDGPU assembler instructions.
+
+This notation mimics the :ref:`syntax of assembler instructions<amdgpu_syn_instructions>`
+except that instead of real operands and modifiers it provides references to their description.
+
+Instructions
+============
+
+Notation
+~~~~~~~~
+
+This is the notation used to describe AMDGPU instructions:
+
+    ``<``\ :ref:`opcode description<amdgpu_syn_opcode_notation>`\ ``>  <``\ :ref:`operands description<amdgpu_syn_instruction_operands_notation>`\ ``>  <``\ :ref:`modifiers description<amdgpu_syn_instruction_modifiers_notation>`\ ``>``
+
+.. _amdgpu_syn_opcode_notation:
+
+Opcode
+======
+
+Notation
+~~~~~~~~
+
+TBD
+
+.. _amdgpu_syn_instruction_operands_notation:
+
+Operands
+========
+
+An instruction may have zero or more *operands*. They are comma-separated in the description:
+
+    ``<``\ :ref:`description of operand 0<amdgpu_syn_instruction_operand_notation>`\ ``>, <``\ :ref:`description of operand 1<amdgpu_syn_instruction_operand_notation>`\ ``>, ...``
+
+The order of *operands* is fixed. *Operands* cannot be omitted
+except for special cases described below.
+
+.. _amdgpu_syn_instruction_operand_notation:
+
+Notation
+~~~~~~~~
+
+An operand is described using the following notation:
+
+    *<name><tag0><tag1>...*
+
+Where:
+
+* *name* is a link to a description of the operand.
+* *tags* are optional. They are used to indicate special operand properties:
+
+.. _amdgpu_syn_instruction_operand_tags:
+
+    ============== =================================================================================
+    Operand tag    Meaning
+    ============== =================================================================================
+    :opt           An optional operand.
+    :m             An operand which may be used with
+                   :ref:`VOP3 operand modifiers<amdgpu_synid_vop3_operand_modifiers>` or
+                   :ref:`SDWA operand modifiers<amdgpu_synid_sdwa_operand_modifiers>`.
+    :dst           An input operand which may also serve as a destination
+                   if :ref:`glc<amdgpu_synid_glc>` modifier is specified.
+    :fx            This is an *f32* or *f16* operand depending on
+                   :ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` modifier.
+    :<type>        Operand *type* differs from *type*
+                   :ref:`implied by the opcode name<amdgpu_syn_instruction_type>`.
+                   This tag specifies actual operand *type*.
+    ============== =================================================================================
+
+Examples:
+
+.. code-block:: nasm
+
+    src1:m             // src1 operand may be used with operand modifiers
+    vdata:dst          // vdata operand may be used as both source and destination
+    vdst:u32           // vdst operand has u32 type
+
+.. _amdgpu_syn_instruction_modifiers_notation:
+
+Modifiers
+=========
+
+An instruction may have zero or more optional *modifiers*. They are space-separated in the description:
+
+    ``<``\ :ref:`description of modifier 0<amdgpu_syn_instruction_modifier_notation>`\ ``> <``\ :ref:`description of modifier 1<amdgpu_syn_instruction_modifier_notation>`\ ``> ...``
+
+The order of *modifiers* is fixed.
+
+.. _amdgpu_syn_instruction_modifier_notation:
+
+Notation
+~~~~~~~~
+
+A *modifier* is described using the following notation:
+
+    *<name>*
+
+Where *name* is a link to a description of the *modifier*.

diff --git a/docs/AMDGPUInstructionSyntax.rst b/docs/AMDGPUInstructionSyntax.rst
new file mode 100644 (file)
index 0000000..3beb1c3
--- /dev/null
+++ b/docs/AMDGPUInstructionSyntax.rst
@@ -0,0 +1,170 @@
+=========================
+AMDGPU Instruction Syntax
+=========================
+
+.. contents::
+   :local:
+
+.. _amdgpu_syn_instructions:
+
+Instructions
+============
+
+Syntax
+~~~~~~
+
+An instruction has the following syntax:
+
+    ``<``\ *opcode mnemonic*\ ``>    <``\ *operand0*\ ``>, <``\ *operand1*\ ``>,...    <``\ *modifier0*\ ``> <``\ *modifier1*\ ``>...``
+
+:doc:`Operands<AMDGPUOperandSyntax>` are normally comma-separated while
+:doc:`modifiers<AMDGPUModifierSyntax>` are space-separated.
+
+The order of *operands* and *modifiers* is fixed.
+Most *modifiers* are optional and may be omitted.
+
+.. _amdgpu_syn_instruction_mnemo:
+
+Opcode Mnemonic
+~~~~~~~~~~~~~~~
+
+Opcode mnemonic describes opcode semantics and may include one or more suffices in this order:
+
+* :ref:`Destination operand type suffix<amdgpu_syn_instruction_type>`.
+* :ref:`Source operand type suffix<amdgpu_syn_instruction_type>`.
+* :ref:`Encoding suffix<amdgpu_syn_instruction_enc>`.
+
+.. _amdgpu_syn_instruction_type:
+
+Type and Size Suffices
+~~~~~~~~~~~~~~~~~~~~~~
+
+Instructions which operate with data have an implied type of *data* operands.
+This data type is specified as a suffix of instruction mnemonic.
+
+There are instructions which have 2 type suffices:
+the first is the data type of the destination operand,
+the second is the data type of source *data* operand(s).
+
+Note that data type specified by an instruction does not apply
+to other kinds of operands such as *addresses*, *offsets* and so on.
+
+The following table enumerates the most frequently used type suffices.
+
+    ============================================ ======================= =================
+    Type Suffices                                Packed instruction?     Data Type
+    ============================================ ======================= =================
+    _b512, _b256, _b128, _b64, _b32, _b16, _b8   No                      Bits.
+    _u64, _u32, _u16, _u8                        No                      Unsigned integer.
+    _i64, _i32, _i16, _i8                        No                      Signed integer.
+    _f64, _f32, _f16                             No                      Floating-point.
+    _b16, _u16, _i16, _f16                       Yes                     Packed.
+    ============================================ ======================= =================
+
+Instructions which have no type suffices are assumed to operate with typeless data.
+The size of data is specified by size suffices:
+
+    ================= =================== =====================================
+    Size Suffix       Implied data type   Required register size in dwords
+    ================= =================== =====================================
+    \-                b32                 1
+    x2                b64                 2
+    x3                b96                 3
+    x4                b128                4
+    x8                b256                8
+    x16               b512                16
+    x                 b32                 1
+    xy                b64                 2
+    xyz               b96                 3
+    xyzw              b128                4
+    d16_x             b16                 1
+    d16_xy            b16x2               2 for GFX8.0, 1 for GFX8.1 and GFX9
+    d16_xyz           b16x3               3 for GFX8.0, 2 for GFX8.1 and GFX9
+    d16_xyzw          b16x4               4 for GFX8.0, 2 for GFX8.1 and GFX9
+    ================= =================== =====================================
+
+.. WARNING::
+    There are exceptions from rules described above.
+    Operands which have type different from type specified by the opcode are
+    :ref:`tagged<amdgpu_syn_instruction_operand_tags>` in the description.
+
+Examples of instructions with different types of source and destination operands:
+
+.. code-block:: nasm
+
+    s_bcnt0_i32_b64
+    v_cvt_f32_u32
+
+Examples of instructions with one data type:
+
+.. code-block:: nasm
+
+    v_max3_f32
+    v_max3_i16
+
+Examples of instructions which operate with packed data:
+
+.. code-block:: nasm
+
+    v_pk_add_u16
+    v_pk_add_i16
+    v_pk_add_f16
+
+Examples of typeless instructions which operate on b128 data:
+
+.. code-block:: nasm
+
+    buffer_store_dwordx4
+    flat_load_dwordx4
+
+.. _amdgpu_syn_instruction_enc:
+
+Encoding Suffices
+~~~~~~~~~~~~~~~~~
+
+Most *VOP1*, *VOP2* and *VOPC* instructions have several variants:
+they may also be encoded in *VOP3*, *DPP* and *SDWA* formats.
+
+The assembler will automatically use optimal encoding based on instruction operands.
+To force specific encoding, one can add a suffix to the opcode of the instruction:
+
+    =================================================== =================
+    Encoding                                            Encoding Suffix
+    =================================================== =================
+    Native 32-bit encoding (*VOP1*, *VOP2* or *VOPC*)   _e32
+    *VOP3* (64-bit) encoding                            _e64
+    *DPP* encoding                                      _dpp
+    *SDWA* encoding                                     _sdwa
+    =================================================== =================
+
+These suffices are used in this reference to indicate the assumed encoding.
+When no suffix is specified, a native encoding is implied.
+
+Operands
+========
+
+Syntax
+~~~~~~
+
+Syntax of most operands is described :doc:`in this document<AMDGPUOperandSyntax>`.
+
+For detailed information about operands follow *operand links* in GPU-specific documents:
+
+* :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`
+* :doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>`
+* :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`
+
+Modifiers
+=========
+
+Syntax
+~~~~~~
+
+Syntax of modifiers is described :doc:`in this document<AMDGPUModifierSyntax>`.
+
+Information about modifiers supported for individual instructions may be found in GPU-specific documents:
+
+* :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`
+* :doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>`
+* :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`
+

diff --git a/docs/AMDGPUModifierSyntax.rst b/docs/AMDGPUModifierSyntax.rst
new file mode 100644 (file)
index 0000000..bc2ddd0
--- /dev/null
+++ b/docs/AMDGPUModifierSyntax.rst
@@ -0,0 +1,1248 @@
+======================================
+Syntax of AMDGPU Instruction Modifiers
+======================================
+
+.. contents::
+   :local:
+
+Conventions
+===========
+
+The following notation is used throughout this document:
+
+    =================== =============================================================
+    Notation            Description
+    =================== =============================================================
+    {0..N}              Any integer value in the range from 0 to N (inclusive).
+    <x>                 Syntax and meaning of *x* is explained elsewhere.
+    =================== =============================================================
+
+.. _amdgpu_syn_modifiers:
+
+Modifiers
+=========
+
+DS Modifiers
+------------
+
+.. _amdgpu_synid_ds_offset8:
+
+ds_offset8
+~~~~~~~~~~
+
+Specifies an immediate unsigned 8-bit offset, in bytes. The default value is 0.
+
+Used with DS instructions which have 2 addresses.
+
+    =================== =====================================================
+    Syntax              Description
+    =================== =====================================================
+    offset:{0..0xFF}    Specifies an unsigned 8-bit offset as a positive
+                        :ref:`integer number <amdgpu_synid_integer_number>`.
+    =================== =====================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  offset:255
+  offset:0xff
+
+.. _amdgpu_synid_ds_offset16:
+
+ds_offset16
+~~~~~~~~~~~
+
+Specifies an immediate unsigned 16-bit offset, in bytes. The default value is 0.
+
+Used with DS instructions which have 1 address.
+
+    ==================== ======================================================
+    Syntax               Description
+    ==================== ======================================================
+    offset:{0..0xFFFF}   Specifies an unsigned 16-bit offset as a positive
+                         :ref:`integer number <amdgpu_synid_integer_number>`.
+    ==================== ======================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  offset:65535
+  offset:0xffff
+
+.. _amdgpu_synid_sw_offset16:
+
+sw_offset16
+~~~~~~~~~~~
+
+This is a special modifier which may be used with *ds_swizzle_b32* instruction only.
+It specifies a swizzle pattern in numeric or symbolic form. The default value is 0.
+
+See AMD documentation for more information.
+
+    ======================================================= ===========================================================
+    Syntax                                                  Description
+    ======================================================= ===========================================================
+    offset:{0..0xFFFF}                                      Specifies a 16-bit swizzle pattern.
+    offset:swizzle(QUAD_PERM,{0..3},{0..3},{0..3},{0..3})   Specifies a quad permute mode pattern
+
+                                                            Each number is a lane *id*.
+    offset:swizzle(BITMASK_PERM, "<mask>")                  Specifies a bitmask permute mode pattern.
+
+                                                            The pattern converts a 5-bit lane *id* to another
+                                                            lane *id* with which the lane interacts.
+
+                                                            *mask* is a 5 character sequence which
+                                                            specifies how to transform the bits of the
+                                                            lane *id*. 
+
+                                                            The following characters are allowed:
+
+                                                            * "0" - set bit to 0.
+
+                                                            * "1" - set bit to 1.
+
+                                                            * "p" - preserve bit.
+
+                                                            * "i" - inverse bit.
+
+    offset:swizzle(BROADCAST,{2..32},{0..N})                Specifies a broadcast mode.
+
+                                                            Broadcasts the value of any particular lane to
+                                                            all lanes in its group.
+
+                                                            The first numeric parameter is a group
+                                                            size and must be equal to 2, 4, 8, 16 or 32.
+
+                                                            The second numeric parameter is an index of the
+                                                            lane being broadcasted. 
+
+                                                            The index must not exceed group size.
+    offset:swizzle(SWAP,{1..16})                            Specifies a swap mode.
+
+                                                            Swaps the neighboring groups of
+                                                            1, 2, 4, 8 or 16 lanes.
+    offset:swizzle(REVERSE,{2..32})                         Specifies a reverse mode.
+
+                                                            Reverses the lanes for groups of 2, 4, 8, 16 or 32 lanes.
+    ======================================================= ===========================================================
+
+Numeric parameters may be specified as either :ref:`integer numbers<amdgpu_synid_integer_number>` or
+:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. code-block:: nasm
+
+  offset:255
+  offset:0xffff
+  offset:swizzle(QUAD_PERM, 0, 1, 2 ,3)
+  offset:swizzle(BITMASK_PERM, "01pi0")
+  offset:swizzle(BROADCAST, 2, 0)
+  offset:swizzle(SWAP, 8)
+  offset:swizzle(REVERSE, 30 + 2)
+
+.. _amdgpu_synid_gds:
+
+gds
+~~~
+
+Specifies whether to use GDS or LDS memory (LDS is the default).
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    gds                                      Use GDS memory.
+    ======================================== ================================================
+
+
+EXP Modifiers
+-------------
+
+.. _amdgpu_synid_done:
+
+done
+~~~~
+
+Specifies if this is the last export from the shader to the target. By default, current
+instruction does not finish an export sequence.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    done                                     Indicates the last export operation.
+    ======================================== ================================================
+
+.. _amdgpu_synid_compr:
+
+compr
+~~~~~
+
+Indicates if the data are compressed (data are not compressed by default).
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    compr                                    Data are compressed.
+    ======================================== ================================================
+
+.. _amdgpu_synid_vm:
+
+vm
+~~
+
+Specifies valid mask flag state (off by default).
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    vm                                       Set valid mask flag.
+    ======================================== ================================================
+
+FLAT Modifiers
+--------------
+
+.. _amdgpu_synid_flat_offset12:
+
+flat_offset12
+~~~~~~~~~~~~~
+
+Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.
+
+Cannot be used with *global/scratch* opcodes. GFX9 only.
+
+    ================= ======================================================
+    Syntax            Description
+    ================= ======================================================
+    offset:{0..4095}  Specifies a 12-bit unsigned offset as a positive
+                      :ref:`integer number <amdgpu_synid_integer_number>`.
+    ================= ======================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  offset:4095
+  offset:0xff
+
+.. _amdgpu_synid_flat_offset13:
+
+flat_offset13
+~~~~~~~~~~~~~
+
+Specifies an immediate signed 13-bit offset, in bytes. The default value is 0.
+
+Can be used with *global/scratch* opcodes only. GFX9 only.
+
+    ============================ =======================================================
+    Syntax                       Description
+    ============================ =======================================================
+    offset:{-4096..+4095}        Specifies a 13-bit signed offset as an
+                                 :ref:`integer number <amdgpu_synid_integer_number>`.
+    ============================ =======================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  offset:-4000
+  offset:0x10
+
+glc
+~~~
+
+See a description :ref:`here<amdgpu_synid_glc>`.
+
+slc
+~~~
+
+See a description :ref:`here<amdgpu_synid_slc>`.
+
+tfe
+~~~
+
+See a description :ref:`here<amdgpu_synid_tfe>`.
+
+nv
+~~
+
+See a description :ref:`here<amdgpu_synid_nv>`.
+
+MIMG Modifiers
+--------------
+
+.. _amdgpu_synid_dmask:
+
+dmask
+~~~~~
+
+Specifies which channels (image components) are used by the operation. By default, no channels
+are used.
+
+    =============== =====================================================
+    Syntax          Description
+    =============== =====================================================
+    dmask:{0..15}   Specifies image channels as a positive
+                    :ref:`integer number <amdgpu_synid_integer_number>`.
+
+                    Each bit corresponds to one of 4 image
+                    components (RGBA).
+
+                    If the specified bit value
+                    is 0, the component is not used, value 1 means
+                    that the component is used.
+    =============== =====================================================
+
+This modifier has some limitations depending on instruction kind:
+
+    =================================================== ========================
+    Instruction Kind                                    Valid dmask Values
+    =================================================== ========================
+    32-bit atomic *cmpswap*                             0x3
+    32-bit atomic instructions except for *cmpswap*     0x1
+    64-bit atomic *cmpswap*                             0xF
+    64-bit atomic instructions except for *cmpswap*     0x3
+    *gather4*                                           0x1, 0x2, 0x4, 0x8
+    Other instructions                                  any value
+    =================================================== ========================
+
+Examples:
+
+.. code-block:: nasm
+
+  dmask:0xf
+  dmask:0b1111
+  dmask:3
+
+.. _amdgpu_synid_unorm:
+
+unorm
+~~~~~
+
+Specifies whether the address is normalized or not (the address is normalized by default).
+
+    ======================== ========================================
+    Syntax                   Description
+    ======================== ========================================
+    unorm                    Force the address to be unnormalized.
+    ======================== ========================================
+
+glc
+~~~
+
+See a description :ref:`here<amdgpu_synid_glc>`.
+
+slc
+~~~
+
+See a description :ref:`here<amdgpu_synid_slc>`.
+
+.. _amdgpu_synid_r128:
+
+r128
+~~~~
+
+Specifies texture resource size. The default size is 256 bits.
+
+GFX7 and GFX8 only.
+
+    =================== ================================================
+    Syntax              Description
+    =================== ================================================
+    r128                Specifies 128 bits texture resource size.
+    =================== ================================================
+
+.. WARNING:: Using this modifier should descrease *rsrc* register size from 8 to 4 dwords, but assembler does not currently support this feature.
+
+tfe
+~~~
+
+See a description :ref:`here<amdgpu_synid_tfe>`.
+
+.. _amdgpu_synid_lwe:
+
+lwe
+~~~
+
+Specifies LOD warning status (LOD warning is disabled by default).
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    lwe                                      Enables LOD warning.
+    ======================================== ================================================
+
+.. _amdgpu_synid_da:
+
+da
+~~
+
+Specifies if an array index must be sent to TA. By default, array index is not sent.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    da                                       Send an array-index to TA.
+    ======================================== ================================================
+
+.. _amdgpu_synid_d16:
+
+d16
+~~~
+
+Specifies data size: 16 or 32 bits (32 bits by default). Not supported by GFX7.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    d16                                      Enables 16-bits data mode.
+
+                                             On loads, convert data in memory to 16-bit
+                                             format before storing it in VGPRs.
+
+                                             For stores, convert 16-bit data in VGPRs to
+                                             32 bits before going to memory.
+
+                                             Note that GFX8.0 does not support data packing.
+                                             Each 16-bit data element occupies 1 VGPR.
+
+                                             GFX8.1 and GFX9 support data packing.
+                                             Each pair of 16-bit data elements 
+                                             occupies 1 VGPR.
+    ======================================== ================================================
+
+.. _amdgpu_synid_a16:
+
+a16
+~~~
+
+Specifies size of image address components: 16 or 32 bits (32 bits by default). GFX9 only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    a16                                      Enables 16-bits image address components.
+    ======================================== ================================================
+
+Miscellaneous Modifiers
+-----------------------
+
+.. _amdgpu_synid_glc:
+
+glc
+~~~
+
+This modifier has different meaning for loads, stores, and atomic operations.
+The default value is off (0).
+
+See AMD documentation for details.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    glc                                      Set glc bit to 1.
+    ======================================== ================================================
+
+.. _amdgpu_synid_slc:
+
+slc
+~~~
+
+Specifies cache policy. The default value is off (0).
+
+See AMD documentation for details.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    slc                                      Set slc bit to 1.
+    ======================================== ================================================
+
+.. _amdgpu_synid_tfe:
+
+tfe
+~~~
+
+Controls access to partially resident textures. The default value is off (0).
+
+See AMD documentation for details.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    tfe                                      Set tfe bit to 1.
+    ======================================== ================================================
+
+.. _amdgpu_synid_nv:
+
+nv
+~~
+
+Specifies if instruction is operating on non-volatile memory. By default, memory is volatile.
+
+GFX9 only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    nv                                       Indicates that instruction operates on
+                                             non-volatile memory.
+    ======================================== ================================================
+
+MUBUF/MTBUF Modifiers
+---------------------
+
+.. _amdgpu_synid_idxen:
+
+idxen
+~~~~~
+
+Specifies whether address components include an index. By default, no components are used.
+
+Can be used together with :ref:`offen<amdgpu_synid_offen>`.
+
+Cannot be used with :ref:`addr64<amdgpu_synid_addr64>`.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    idxen                                    Address components include an index.
+    ======================================== ================================================
+
+.. _amdgpu_synid_offen:
+
+offen
+~~~~~
+
+Specifies whether address components include an offset. By default, no components are used.
+
+Can be used together with :ref:`idxen<amdgpu_synid_idxen>`.
+
+Cannot be used with :ref:`addr64<amdgpu_synid_addr64>`.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    offen                                    Address components include an offset.
+    ======================================== ================================================
+
+.. _amdgpu_synid_addr64:
+
+addr64
+~~~~~~
+
+Specifies whether a 64-bit address is used. By default, no address is used.
+
+GFX7 only. Cannot be used with :ref:`offen<amdgpu_synid_offen>` and
+:ref:`idxen<amdgpu_synid_idxen>` modifiers.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    addr64                                   A 64-bit address is used.
+    ======================================== ================================================
+
+.. _amdgpu_synid_buf_offset12:
+
+buf_offset12
+~~~~~~~~~~~~
+
+Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.
+
+    =============================== ======================================================
+    Syntax                          Description
+    =============================== ======================================================
+    offset:{0..0xFFF}               Specifies a 12-bit unsigned offset as a positive
+                                    :ref:`integer number <amdgpu_synid_integer_number>`.
+    =============================== ======================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  offset:0
+  offset:0x10
+
+glc
+~~~
+
+See a description :ref:`here<amdgpu_synid_glc>`.
+
+slc
+~~~
+
+See a description :ref:`here<amdgpu_synid_slc>`.
+
+.. _amdgpu_synid_lds:
+
+lds
+~~~
+
+Specifies where to store the result: VGPRs or LDS (VGPRs by default).
+
+    ======================================== ===========================
+    Syntax                                   Description
+    ======================================== ===========================
+    lds                                      Store result in LDS.
+    ======================================== ===========================
+
+tfe
+~~~
+
+See a description :ref:`here<amdgpu_synid_tfe>`.
+
+.. _amdgpu_synid_dfmt:
+
+dfmt
+~~~~
+
+TBD
+
+.. _amdgpu_synid_nfmt:
+
+nfmt
+~~~~
+
+TBD
+
+SMRD/SMEM Modifiers
+-------------------
+
+glc
+~~~
+
+See a description :ref:`here<amdgpu_synid_glc>`.
+
+nv
+~~
+
+See a description :ref:`here<amdgpu_synid_nv>`.
+
+VINTRP Modifiers
+----------------
+
+.. _amdgpu_synid_high:
+
+high
+~~~~
+
+Specifies which half of the LDS word to use. Low half of LDS word is used by default.
+GFX9 only.
+
+    ======================================== ================================
+    Syntax                                   Description
+    ======================================== ================================
+    high                                     Use high half of LDS word.
+    ======================================== ================================
+
+VOP1/VOP2 DPP Modifiers
+-----------------------
+
+GFX8 and GFX9 only.
+
+.. _amdgpu_synid_dpp_ctrl:
+
+dpp_ctrl
+~~~~~~~~
+
+Specifies how data are shared between threads. This is a mandatory modifier.
+There is no default value.
+
+Note. The lanes of a wavefront are organized in four banks and four rows.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    quad_perm:[{0..3},{0..3},{0..3},{0..3}]  Full permute of 4 threads.
+    row_mirror                               Mirror threads within row.
+    row_half_mirror                          Mirror threads within 1/2 row (8 threads).
+    row_bcast:15                             Broadcast 15th thread of each row to next row.
+    row_bcast:31                             Broadcast thread 31 to rows 2 and 3.
+    wave_shl:1                               Wavefront left shift by 1 thread.
+    wave_rol:1                               Wavefront left rotate by 1 thread.
+    wave_shr:1                               Wavefront right shift by 1 thread.
+    wave_ror:1                               Wavefront right rotate by 1 thread.
+    row_shl:{1..15}                          Row shift left by 1-15 threads.
+    row_shr:{1..15}                          Row shift right by 1-15 threads.
+    row_ror:{1..15}                          Row rotate right by 1-15 threads.
+    ======================================== ================================================
+
+Note: Numeric parameters may be specified as either
+:ref:`integer numbers<amdgpu_synid_integer_number>` or
+:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. code-block:: nasm
+
+  quad_perm:[0, 1, 2, 3]
+  row_shl:3
+
+.. _amdgpu_synid_row_mask:
+
+row_mask
+~~~~~~~~
+
+Controls which rows are enabled for data sharing. By default, all rows are enabled.
+
+Note. The lanes of a wavefront are organized in four banks and four rows.
+
+    ======================================== =====================================================
+    Syntax                                   Description
+    ======================================== =====================================================
+    row_mask:{0..15}                         Specifies a *row mask* as a positive
+                                             :ref:`integer number <amdgpu_synid_integer_number>`.
+
+                                             Each of 4 bits in the mask controls one
+                                             row (0 - disabled, 1 - enabled).
+    ======================================== =====================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  row_mask:0xf
+  row_mask:0b1010
+  row_mask:0b1111
+
+.. _amdgpu_synid_bank_mask:
+
+bank_mask
+~~~~~~~~~
+
+Controls which banks are enabled for data sharing. By default, all banks are enabled.
+
+Note. The lanes of a wavefront are organized in four banks and four rows.
+
+    ======================================== =======================================================
+    Syntax                                   Description
+    ======================================== =======================================================
+    bank_mask:{0..15}                        Specifies a *bank mask* as a positive
+                                             :ref:`integer number <amdgpu_synid_integer_number>`.
+
+                                             Each of 4 bits in the mask controls one
+                                             bank (0 - disabled, 1 - enabled).
+    ======================================== =======================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  bank_mask:0x3
+  bank_mask:0b0011
+  bank_mask:0b1111
+
+.. _amdgpu_synid_bound_ctrl:
+
+bound_ctrl
+~~~~~~~~~~
+
+Controls data sharing when accessing an invalid lane. By default, data sharing with
+invalid lanes is disabled.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    bound_ctrl:0                             Enables data sharing with invalid lanes.
+
+                                             Accessing data from an invalid lane will
+                                             return zero.
+    ======================================== ================================================
+
+VOP1/VOP2/VOPC SDWA Modifiers
+-----------------------------
+
+GFX8 and GFX9 only.
+
+clamp
+~~~~~
+
+See a description :ref:`here<amdgpu_synid_clamp>`.
+
+omod
+~~~~
+
+See a description :ref:`here<amdgpu_synid_omod>`.
+
+GFX9 only.
+
+.. _amdgpu_synid_dst_sel:
+
+dst_sel
+~~~~~~~
+
+Selects which bits in the destination are affected. By default, all bits are affected.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    dst_sel:DWORD                            Use bits 31:0.
+    dst_sel:BYTE_0                           Use bits 7:0.
+    dst_sel:BYTE_1                           Use bits 15:8.
+    dst_sel:BYTE_2                           Use bits 23:16.
+    dst_sel:BYTE_3                           Use bits 31:24.
+    dst_sel:WORD_0                           Use bits 15:0.
+    dst_sel:WORD_1                           Use bits 31:16.
+    ======================================== ================================================
+
+
+.. _amdgpu_synid_dst_unused:
+
+dst_unused
+~~~~~~~~~~
+
+Controls what to do with the bits in the destination which are not selected
+by :ref:`dst_sel<amdgpu_synid_dst_sel>`.
+By default, unused bits are preserved.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    dst_unused:UNUSED_PAD                    Pad with zeros.
+    dst_unused:UNUSED_SEXT                   Sign-extend upper bits, zero lower bits.
+    dst_unused:UNUSED_PRESERVE               Preserve bits.
+    ======================================== ================================================
+
+.. _amdgpu_synid_src0_sel:
+
+src0_sel
+~~~~~~~~
+
+Controls which bits in the src0 are used. By default, all bits are used.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    src0_sel:DWORD                           Use bits 31:0.
+    src0_sel:BYTE_0                          Use bits 7:0.
+    src0_sel:BYTE_1                          Use bits 15:8.
+    src0_sel:BYTE_2                          Use bits 23:16.
+    src0_sel:BYTE_3                          Use bits 31:24.
+    src0_sel:WORD_0                          Use bits 15:0.
+    src0_sel:WORD_1                          Use bits 31:16.
+    ======================================== ================================================
+
+.. _amdgpu_synid_src1_sel:
+
+src1_sel
+~~~~~~~~
+
+Controls which bits in the src1 are used. By default, all bits are used.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    src1_sel:DWORD                           Use bits 31:0.
+    src1_sel:BYTE_0                          Use bits 7:0.
+    src1_sel:BYTE_1                          Use bits 15:8.
+    src1_sel:BYTE_2                          Use bits 23:16.
+    src1_sel:BYTE_3                          Use bits 31:24.
+    src1_sel:WORD_0                          Use bits 15:0.
+    src1_sel:WORD_1                          Use bits 31:16.
+    ======================================== ================================================
+
+.. _amdgpu_synid_sdwa_operand_modifiers:
+
+VOP1/VOP2/VOPC SDWA Operand Modifiers
+-------------------------------------
+
+Operand modifiers are not used separately. They are applied to source operands.
+
+GFX8 and GFX9 only.
+
+abs
+~~~
+
+See a description :ref:`here<amdgpu_synid_abs>`.
+
+neg
+~~~
+
+See a description :ref:`here<amdgpu_synid_neg>`.
+
+.. _amdgpu_synid_sext:
+
+sext
+~~~~
+
+Sign-extends value of a (sub-dword) operand to fill all 32 bits.
+Has no effect for 32-bit operands.
+
+Valid for integer operands only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    sext(<operand>)                          Sign-extend operand value.
+    ======================================== ================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  sext(v4)
+  sext(v255)
+
+VOP3 Modifiers
+--------------
+
+.. _amdgpu_synid_vop3_op_sel:
+
+vop3_op_sel
+~~~~~~~~~~~
+
+Selects the low [15:0] or high [31:16] operand bits for source and destination operands.
+By default, low bits are used for all operands.
+
+The number of values specified with the op_sel modifier must match the number of instruction
+operands (both source and destination). First value controls src0, second value controls src1
+and so on, except that the last value controls destination.
+The value 0 selects the low bits, while 1 selects the high bits.
+
+Note. op_sel modifier affects 16-bit operands only. For 32-bit operands the value specified
+by op_sel must be 0.
+
+GFX9 only.
+
+    ======================================== ============================================================
+    Syntax                                   Description
+    ======================================== ============================================================
+    op_sel:[{0..1},{0..1}]                   Select operand bits for instructions with 1 source operand.
+    op_sel:[{0..1},{0..1},{0..1}]            Select operand bits for instructions with 2 source operands.
+    op_sel:[{0..1},{0..1},{0..1},{0..1}]     Select operand bits for instructions with 3 source operands.
+    ======================================== ============================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  op_sel:[0,0]
+  op_sel:[0,1]
+
+.. _amdgpu_synid_clamp:
+
+clamp
+~~~~~
+
+Clamp meaning depends on instruction.
+
+For *v_cmp* instructions, clamp modifier indicates that the compare signals
+if a floating point exception occurs. By default, signaling is disabled.
+Not supported by GFX7.
+
+For integer operations, clamp modifier indicates that the result must be clamped
+to the largest and smallest representable value. By default, there is no clamping.
+Integer clamping is not supported by GFX7.
+
+For floating point operations, clamp modifier indicates that the result must be clamped
+to the range [0.0, 1.0]. By default, there is no clamping.
+
+Note. Clamp modifier is applied after :ref:`output modifiers<amdgpu_synid_omod>` (if any).
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    clamp                                    Enables clamping (or signaling).
+    ======================================== ================================================
+
+.. _amdgpu_synid_omod:
+
+omod
+~~~~
+
+Specifies if an output modifier must be applied to the result.
+By default, no output modifiers are applied.
+
+Note. Output modifiers are applied before :ref:`clamping<amdgpu_synid_clamp>` (if any).
+
+Output modifiers are valid for f32 and f64 floating point results only.
+They must not be used with f16.
+
+Note. *v_cvt_f16_f32* is an exception. This instruction produces f16 result
+but accepts output modifiers.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    mul:2                                    Multiply the result by 2.
+    mul:4                                    Multiply the result by 4.
+    div:2                                    Multiply the result by 0.5.
+    ======================================== ================================================
+
+.. _amdgpu_synid_vop3_operand_modifiers:
+
+VOP3 Operand Modifiers
+----------------------
+
+Operand modifiers are not used separately. They are applied to source operands.
+
+.. _amdgpu_synid_abs:
+
+abs
+~~~
+
+Computes absolute value of its operand. Applied before :ref:`neg<amdgpu_synid_neg>` (if any).
+Valid for floating point operands only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    abs(<operand>)                           Get absolute value of operand.
+    \|<operand>|                             The same as above.
+    ======================================== ================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  abs(v36)
+  |v36|
+
+.. _amdgpu_synid_neg:
+
+neg
+~~~
+
+Computes negative value of its operand. Applied after :ref:`abs<amdgpu_synid_abs>` (if any).
+Valid for floating point operands only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    neg(<operand>)                           Get negative value of operand.
+    -<operand>                               The same as above.
+    ======================================== ================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  neg(v[0])
+  -v4
+
+VOP3P Modifiers
+---------------
+
+This section describes modifiers of *regular* VOP3P instructions.
+
+*v_mad_mix_f32*, *v_mad_mixhi_f16* and *v_mad_mixlo_f16*
+instructions use these modifiers :ref:`in a special manner<amdgpu_synid_mad_mix>`.
+
+GFX9 only.
+
+.. _amdgpu_synid_op_sel:
+
+op_sel
+~~~~~~
+
+Selects the low [15:0] or high [31:16] operand bits as input to the operation
+which results in the lower-half of the destination.
+By default, low bits are used for all operands.
+
+The number of values specified by the *op_sel* modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.
+
+The value 0 selects the low bits, while 1 selects the high bits.
+
+    ================================= =============================================================
+    Syntax                            Description
+    ================================= =============================================================
+    op_sel:[{0..1}]                   Select operand bits for instructions with 1 source operand.
+    op_sel:[{0..1},{0..1}]            Select operand bits for instructions with 2 source operands.
+    op_sel:[{0..1},{0..1},{0..1}]     Select operand bits for instructions with 3 source operands.
+    ================================= =============================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  op_sel:[0,0]
+  op_sel:[0,1,0]
+
+.. _amdgpu_synid_op_sel_hi:
+
+op_sel_hi
+~~~~~~~~~
+
+Selects the low [15:0] or high [31:16] operand bits as input to the operation
+which results in the upper-half of the destination.
+By default, high bits are used for all operands.
+
+The number of values specified by the *op_sel_hi* modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.
+
+The value 0 selects the low bits, while 1 selects the high bits.
+
+    =================================== =============================================================
+    Syntax                              Description
+    =================================== =============================================================
+    op_sel_hi:[{0..1}]                  Select operand bits for instructions with 1 source operand.
+    op_sel_hi:[{0..1},{0..1}]           Select operand bits for instructions with 2 source operands.
+    op_sel_hi:[{0..1},{0..1},{0..1}]    Select operand bits for instructions with 3 source operands.
+    =================================== =============================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  op_sel_hi:[0,0]
+  op_sel_hi:[0,0,1]
+
+.. _amdgpu_synid_neg_lo:
+
+neg_lo
+~~~~~~
+
+Specifies whether to change sign of operand values selected by
+:ref:`op_sel<amdgpu_synid_op_sel>`. These values are then used
+as input to the operation which results in the upper-half of the destination.
+
+The number of values specified by this modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.
+
+The value 0 indicates that the corresponding operand value is used unmodified,
+the value 1 indicates that negative value of the operand must be used.
+
+By default, operand values are used unmodified.
+
+This modifier is valid for floating point operands only.
+
+    ================================ ==================================================================
+    Syntax                           Description
+    ================================ ==================================================================
+    neg_lo:[{0..1}]                  Select affected operands for instructions with 1 source operand.
+    neg_lo:[{0..1},{0..1}]           Select affected operands for instructions with 2 source operands.
+    neg_lo:[{0..1},{0..1},{0..1}]    Select affected operands for instructions with 3 source operands.
+    ================================ ==================================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  neg_lo:[0]
+  neg_lo:[0,1]
+
+.. _amdgpu_synid_neg_hi:
+
+neg_hi
+~~~~~~
+
+Specifies whether to change sign of operand values selected by
+:ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`. These values are then used
+as input to the operation which results in the upper-half of the destination.
+
+The number of values specified by this modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.
+
+The value 0 indicates that the corresponding operand value is used unmodified,
+the value 1 indicates that negative value of the operand must be used.
+
+By default, operand values are used unmodified.
+
+This modifier is valid for floating point operands only.
+
+    =============================== ==================================================================
+    Syntax                          Description
+    =============================== ==================================================================
+    neg_hi:[{0..1}]                 Select affected operands for instructions with 1 source operand.
+    neg_hi:[{0..1},{0..1}]          Select affected operands for instructions with 2 source operands.
+    neg_hi:[{0..1},{0..1},{0..1}]   Select affected operands for instructions with 3 source operands.
+    =============================== ==================================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  neg_hi:[1,0]
+  neg_hi:[0,1,1]
+
+clamp
+~~~~~
+
+See a description :ref:`here<amdgpu_synid_clamp>`.
+
+.. _amdgpu_synid_mad_mix:
+
+VOP3P V_MAD_MIX Modifiers
+-------------------------
+
+*v_mad_mix_f32*, *v_mad_mixhi_f16* and *v_mad_mixlo_f16* instructions
+use *op_sel* and *op_sel_hi* modifiers 
+in a manner different from *regular* VOP3P instructions.
+
+See a description below.
+
+GFX9 only.
+
+.. _amdgpu_synid_mad_mix_op_sel:
+
+mad_mix_op_sel
+~~~~~~~~~~~~~~
+
+This operand has meaning only for 16-bit source operands as indicated by
+:ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
+It specifies to select either the low [15:0] or high [31:16] operand bits
+as input to the operation.
+
+The number of values specified by the *op_sel* modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.
+
+The value 0 indicates the low bits, the value 1 indicates the high 16 bits.
+
+By default, low bits are used for all operands.
+
+    =============================== ================================================
+    Syntax                          Description
+    =============================== ================================================
+    op_sel:[{0..1},{0..1},{0..1}]   Select location of each 16-bit source operand.
+    =============================== ================================================
+
+Examples:
+
+.. code-block:: nasm
+
+  op_sel:[0,1]
+
+.. _amdgpu_synid_mad_mix_op_sel_hi:
+
+mad_mix_op_sel_hi
+~~~~~~~~~~~~~~~~~
+
+Selects the size of source operands: either 32 bits or 16 bits.
+By default, 32 bits are used for all source operands.
+
+The number of values specified by the *op_sel_hi* modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.
+
+The value 0 indicates 32 bits, the value 1 indicates 16 bits.
+
+The location of 16 bits in the operand may be specified by
+:ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>`.
+
+    ======================================== ====================================
+    Syntax                                   Description
+    ======================================== ====================================
+    op_sel_hi:[{0..1},{0..1},{0..1}]         Select size of each source operand.
+    ======================================== ====================================
+
+Examples:
+
+.. code-block:: nasm
+
+  op_sel_hi:[1,1,1]
+
+abs
+~~~
+
+See a description :ref:`here<amdgpu_synid_abs>`.
+
+neg
+~~~
+
+See a description :ref:`here<amdgpu_synid_neg>`.
+
+clamp
+~~~~~
+
+See a description :ref:`here<amdgpu_synid_clamp>`.

diff --git a/docs/AMDGPUOperandSyntax.rst b/docs/AMDGPUOperandSyntax.rst
index 4f3536e..4fa2bb2 100644 (file)
--- a/docs/AMDGPUOperandSyntax.rst
+++ b/docs/AMDGPUOperandSyntax.rst
@@ -1,6 +1,6 @@
-=================================================
-Syntax of AMDGPU Assembler Operands and Modifiers
-=================================================
+=====================================
+Syntax of AMDGPU Instruction Operands
+=====================================
 
 .. contents::
    :local:
@@ -8,1048 +8,1058 @@ Syntax of AMDGPU Assembler Operands and Modifiers
 Conventions
 ===========
 
-The following conventions are used in syntax description:
+The following notation is used throughout this document:
 
-    =================== =============================================================
+    =================== =============================================================================
     Notation            Description
-    =================== =============================================================
+    =================== =============================================================================
     {0..N}              Any integer value in the range from 0 to N (inclusive).
-                        Unless stated otherwise, this value may be specified as
-                        either a literal or an llvm expression.
-    <x>                 Syntax and meaning of *<x>* is explained elsewhere.
-    =================== =============================================================
+    <x>                 Syntax and meaning of *x* is explained elsewhere.
+    =================== =============================================================================
 
 .. _amdgpu_syn_operands:
 
 Operands
 ========
 
-TBD
+.. _amdgpu_synid_v:
 
-.. _amdgpu_syn_modifiers:
+v
+-
 
-Modifiers
-=========
+Vector registers. There are 256 32-bit vector registers.
 
-DS Modifiers
-------------
-
-.. _amdgpu_synid_ds_offset8:
-
-ds_offset8
-~~~~~~~~~~
-
-Specifies an immediate unsigned 8-bit offset, in bytes. The default value is 0.
-
-Used with DS instructions which have 2 addresses.
-
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    offset:{0..0xFF}                         Specifies a 8-bit offset.
-    ======================================== ================================================
-
-.. _amdgpu_synid_ds_offset16:
-
-ds_offset16
-~~~~~~~~~~~
-
-Specifies an immediate unsigned 16-bit offset, in bytes. The default value is 0.
-
-Used with DS instructions which have 1 address.
-
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    offset:{0..0xFFFF}                       Specifies a 16-bit offset.
-    ======================================== ================================================
-
-.. _amdgpu_synid_sw_offset16:
-
-sw_offset16
-~~~~~~~~~~~
-
-This is a special modifier which may be used with *ds_swizzle_b32* instruction only.
-Specifies a sizzle pattern in numeric or symbolic form. The default value is 0.
-
-See AMD documentation for more information.
-
-    ======================================================= ===================================================
-    Syntax                                                  Description
-    ======================================================= ===================================================
-    offset:{0..0xFFFF}                                      Specifies a 16-bit swizzle pattern
-                                                            in a numeric form.
-    offset:swizzle(QUAD_PERM,{0..3},{0..3},{0..3},{0..3})   Specifies a quad permute mode pattern; each
-                                                            number is a lane id.
-    offset:swizzle(BITMASK_PERM, "<mask>")                  Specifies a bitmask permute mode pattern
-                                                            which converts a 5-bit lane id to another
-                                                            lane id with which the lane interacts.
-
-                                                            <mask> is a 5 character sequence which
-                                                            specifies how to transform the bits of the
-                                                            lane id. The following characters are allowed:
-
-                                                              * "0" - set bit to 0.
+A sequence of *vector* registers may be used to operate with more than 32 bits of data.
 
-                                                              * "1" - set bit to 1.
+Assembler currently supports sequences of 1, 2, 3, 4, 8 and 16 *vector* registers.
 
-                                                              * "p" - preserve bit.
+    =================================================== ====================================================================
+    Syntax                                              Description
+    =================================================== ====================================================================
+    **v**\<N>                                           A single 32-bit *vector* register.
 
-                                                              * "i" - inverse bit.
+                                                        *N* must be a decimal integer number.
+    **v[**\ <N>\ **]**                                  A single 32-bit *vector* register.
 
-    offset:swizzle(BROADCAST,{2..32},{0..N})                Specifies a broadcast mode.
-                                                            Broadcasts the value of any particular lane to
-                                                            all lanes in its group.
+                                                        *N* may be specified as an
+                                                        :ref:`integer number<amdgpu_synid_integer_number>`
+                                                        or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+    **v[**\ <N>:<K>\ **]**                              A sequence of (\ *K-N+1*\ ) *vector* registers.
 
-                                                            The first numeric parameter is a group
-                                                            size and must be equal to 2, 4, 8, 16 or 32.
+                                                        *N* and *K* may be specified as
+                                                        :ref:`integer numbers<amdgpu_synid_integer_number>`
+                                                        or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+    **[v**\ <N>, \ **v**\ <N+1>, ... **v**\ <K>\ **]**  A sequence of (\ *K-N+1*\ ) *vector* registers.
 
-                                                            The second numeric parameter is an index of the
-                                                            lane being broadcasted. The index must not exceed
-                                                            group size.
-    offset:swizzle(SWAP,{1..16})                            Specifies a swap mode.
-                                                            Swaps the neighboring groups of
-                                                            1, 2, 4, 8 or 16 lanes.
-    offset:swizzle(REVERSE,{2..32})                         Specifies a reverse mode. Reverses
-                                                            the lanes for groups of 2, 4, 8, 16 or 32 lanes.
-    ======================================================= ===================================================
+                                                        Register indices must be specified as decimal integer numbers.
+    =================================================== ====================================================================
 
-.. _amdgpu_synid_gds:
+Note. *N* and *K* must satisfy the following conditions:
 
-gds
-~~~
+* *N* <= *K*.
+* 0 <= *N* <= 255.
+* 0 <= *K* <= 255.
+* *K-N+1* must be equal to 1, 2, 3, 4, 8 or 16.
 
-Specifies whether to use GDS or LDS memory (LDS is the default).
+Examples:
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    gds                                      Use GDS memory.
-    ======================================== ================================================
+.. code-block:: nasm
 
+  v255
+  v[0]
+  v[0:1]
+  v[1:1]
+  v[0:3]
+  v[2*2]
+  v[1-1:2-1]
+  [v252]
+  [v252,v253,v254,v255]
 
-EXP Modifiers
--------------
+.. _amdgpu_synid_s:
 
-.. _amdgpu_synid_done:
+s
+-
 
-done
-~~~~
+Scalar 32-bit registers. The number of available *scalar* registers depends on GPU:
 
-Specifies if this is the last export from the shader to the target. By default, current
-instruction does not finish an export sequence.
+    ======= ============================
+    GPU     Number of *scalar* registers
+    ======= ============================
+    GFX7    104
+    GFX8    102
+    GFX9    102
+    ======= ============================
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    done                                     Indicates the last export operation.
-    ======================================== ================================================
+A sequence of *scalar* registers may be used to operate with more than 32 bits of data.
+Assembler currently supports sequences of 1, 2, 4, 8 and 16 *scalar* registers.
 
-.. _amdgpu_synid_compr:
+Pairs of *scalar* registers must be even-aligned (the first register must be even).
+Sequences of 4 and more *scalar* registers must be quad-aligned.
 
-compr
-~~~~~
+    ======================================================== ====================================================================
+    Syntax                                                   Description
+    ======================================================== ====================================================================
+    **s**\ <N>                                               A single 32-bit *scalar* register.
 
-Indicates if the data are compressed (not compressed by default).
+                                                             *N* must be a decimal integer number.
+    **s[**\ <N>\ **]**                                       A single 32-bit *scalar* register.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    compr                                    Data are compressed.
-    ======================================== ================================================
+                                                             *N* may be specified as an
+                                                             :ref:`integer number<amdgpu_synid_integer_number>`
+                                                             or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+    **s[**\ <N>:<K>\ **]**                                   A sequence of (\ *K-N+1*\ ) *scalar* registers.
 
-.. _amdgpu_synid_vm:
+                                                             *N* and *K* may be specified as
+                                                             :ref:`integer numbers<amdgpu_synid_integer_number>`
+                                                             or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+    **[s**\ <N>, \ **s**\ <N+1>, ... **s**\ <K>\ **]**       A sequence of (\ *K-N+1*\ ) *scalar* registers.
 
-vm
-~~
+                                                             Register indices must be specified as decimal integer numbers.
+    ======================================================== ====================================================================
 
-Specifies valid mask flag state (off by default).
+Note. *N* and *K* must satisfy the following conditions:
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    vm                                       Set valid mask flag.
-    ======================================== ================================================
+* *N* must be properly aligned based on sequence size.
+* *N* <= *K*.
+* 0 <= *N* < *SMAX*\ , where *SMAX* is the number of available *scalar* registers.
+* 0 <= *K* < *SMAX*\ , where *SMAX* is the number of available *scalar* registers.
+* *K-N+1* must be equal to 1, 2, 4, 8 or 16.
 
-FLAT Modifiers
---------------
+Examples:
 
-.. _amdgpu_synid_flat_offset12:
+.. code-block:: nasm
 
-flat_offset12
-~~~~~~~~~~~~~
+  s0
+  s[0]
+  s[0:1]
+  s[1:1]
+  s[0:3]
+  s[2*2]
+  s[1-1:2-1]
+  [s4]
+  [s4,s5,s6,s7]
 
-Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.
+Examples of *scalar* registers with an invalid alignment:
 
-Cannot be used with *global/scratch* opcodes. GFX9 only.
+.. code-block:: nasm
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    offset:{0..4095}                         Specifies a 12-bit unsigned offset.
-    ======================================== ================================================
+  s[1:2]
+  s[2:5]
 
-.. _amdgpu_synid_flat_offset13:
+.. _amdgpu_synid_trap:
 
-flat_offset13
-~~~~~~~~~~~~~
+trap
+----
 
-Specifies an immediate signed 13-bit offset, in bytes. The default value is 0.
+A set of trap handler registers:
 
-Can be used with *global/scratch* opcodes only. GFX9 only.
+* :ref:`ttmp<amdgpu_synid_ttmp>`
+* :ref:`tba<amdgpu_synid_tba>`
+* :ref:`tma<amdgpu_synid_tma>`
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    offset:{-4096..+4095}                    Specifies a 13-bit signed offset.
-    ======================================== ================================================
+.. _amdgpu_synid_ttmp:
 
-glc
-~~~
+ttmp
+----
 
-See a description :ref:`here<amdgpu_synid_glc>`.
+Trap handler temporary scalar registers, 32-bits wide.
+The number of available *ttmp* registers depends on GPU:
 
-slc
-~~~
+    ======= ===========================
+    GPU     Number of *ttmp* registers
+    ======= ===========================
+    GFX7    12
+    GFX8    12
+    GFX9    16
+    ======= ===========================
 
-See a description :ref:`here<amdgpu_synid_slc>`.
+A sequence of *ttmp* registers may be used to operate with more than 32 bits of data.
+Assembler currently supports sequences of 1, 2, 4, 8 and 16 *ttmp* registers.
 
-tfe
-~~~
+Pairs of *ttmp* registers must be even-aligned (the first register must be even).
+Sequences of 4 and more *ttmp* registers must be quad-aligned.
 
-See a description :ref:`here<amdgpu_synid_tfe>`.
+    ============================================================= ====================================================================
+    Syntax                                                        Description
+    ============================================================= ====================================================================
+    **ttmp**\ <N>                                                 A single 32-bit *ttmp* register.
 
-nv
-~~
+                                                                  *N* must be a decimal integer number.
+    **ttmp[**\ <N>\ **]**                                         A single 32-bit *ttmp* register.
 
-See a description :ref:`here<amdgpu_synid_nv>`.
+                                                                  *N* may be specified as an
+                                                                  :ref:`integer number<amdgpu_synid_integer_number>`
+                                                                  or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+    **ttmp[**\ <N>:<K>\ **]**                                     A sequence of (\ *K-N+1*\ ) *ttmp* registers.
 
-MIMG Modifiers
---------------
+                                                                  *N* and *K* may be specified as
+                                                                  :ref:`integer numbers<amdgpu_synid_integer_number>`
+                                                                  or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+    **[ttmp**\ <N>, \ **ttmp**\ <N+1>, ... **ttmp**\ <K>\ **]**   A sequence of (\ *K-N+1*\ ) *ttmp* registers.
 
-.. _amdgpu_synid_dmask:
+                                                                  Register indices must be specified as decimal integer numbers.
+    ============================================================= ====================================================================
 
-dmask
-~~~~~
+Note. *N* and *K* must satisfy the following conditions:
 
-Specifies which channels (image components) are used by the operation. By default, no channels
-are used.
+* *N* must be properly aligned based on sequence size.
+* *N* <= *K*.
+* 0 <= *N* < *TMAX*, where *TMAX* is the number of available *ttmp* registers.
+* 0 <= *K* < *TMAX*, where *TMAX* is the number of available *ttmp* registers.
+* *K-N+1* must be equal to 1, 2, 4, 8 or 16.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    dmask:{0..15}                            Each bit corresponds to one of 4 image
-                                             components (RGBA). If the specified bit value
-                                             is 0, the component is not used, value 1 means
-                                             that the component is used.
-    ======================================== ================================================
+Examples:
 
-This modifier has some limitations depending on instruction kind:
+.. code-block:: nasm
 
-    ======================================== ================================================
-    Instruction Kind                         Valid dmask Values
-    ======================================== ================================================
-    32-bit atomic cmpswap                    0x3
-    other 32-bit atomic instructions         0x1
-    64-bit atomic cmpswap                    0xF
-    other 64-bit atomic instructions         0x3
-    GATHER4                                  0x1, 0x2, 0x4, 0x8
-    Other instructions                       any value
-    ======================================== ================================================
+  ttmp0
+  ttmp[0]
+  ttmp[0:1]
+  ttmp[1:1]
+  ttmp[0:3]
+  ttmp[2*2]
+  ttmp[1-1:2-1]
+  [ttmp4]
+  [ttmp4,ttmp5,ttmp6,ttmp7]
 
-.. _amdgpu_synid_unorm:
+Examples of *ttmp* registers with an invalid alignment:
 
-unorm
-~~~~~
+.. code-block:: nasm
 
-Specifies whether address is normalized or not (normalized by default).
+  ttmp[1:2]
+  ttmp[2:5]
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    unorm                                    Force address to be un-normalized.
-    ======================================== ================================================
+.. _amdgpu_synid_tba:
 
-glc
-~~~
+tba
+---
 
-See a description :ref:`here<amdgpu_synid_glc>`.
+Trap base address, 64-bits wide. Holds the pointer to the current trap handler program.
 
-slc
-~~~
+    ================== ======================================================================= =============
+    Syntax             Description                                                             Availability
+    ================== ======================================================================= =============
+    tba                64-bit *trap base address* register.                                    GFX7, GFX8
+    [tba]              64-bit *trap base address* register (an alternative syntax).            GFX7, GFX8
+    [tba_lo,tba_hi]    64-bit *trap base address* register (an alternative syntax).            GFX7, GFX8
+    ================== ======================================================================= =============
 
-See a description :ref:`here<amdgpu_synid_slc>`.
+High and low 32 bits of *trap base address* may be accessed as separate registers:
 
-.. _amdgpu_synid_r128:
+    ================== ======================================================================= =============
+    Syntax             Description                                                             Availability
+    ================== ======================================================================= =============
+    tba_lo             Low 32 bits of *trap base address* register.                            GFX7, GFX8
+    tba_hi             High 32 bits of *trap base address* register.                           GFX7, GFX8
+    [tba_lo]           Low 32 bits of *trap base address* register (an alternative syntax).    GFX7, GFX8
+    [tba_hi]           High 32 bits of *trap base address* register (an alternative syntax).   GFX7, GFX8
+    ================== ======================================================================= =============
 
-r128
-~~~~
+Note that *tba*, *tba_lo* and *tba_hi* are not accessible as assembler registers in GFX9,
+but *tba* is readable/writable with the help of *s_get_reg* and *s_set_reg* instructions.
 
-Specifies texture resource size. The default size is 256 bits.
+.. _amdgpu_synid_tma:
 
-GFX7 and GFX8 only.
+tma
+---
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    r128                                     Specifies 128 bits texture resource size.
-    ======================================== ================================================
+Trap memory address, 64-bits wide.
 
-tfe
-~~~
+    ================= ======================================================================= ==================
+    Syntax            Description                                                             Availability
+    ================= ======================================================================= ==================
+    tma               64-bit *trap memory address* register.                                  GFX7, GFX8
+    [tma]             64-bit *trap memory address* register (an alternative syntax).          GFX7, GFX8
+    [tma_lo,tma_hi]   64-bit *trap memory address* register (an alternative syntax).          GFX7, GFX8
+    ================= ======================================================================= ==================
 
-See a description :ref:`here<amdgpu_synid_tfe>`.
+High and low 32 bits of *trap memory address* may be accessed as separate registers:
 
-.. _amdgpu_synid_lwe:
+    ================= ======================================================================= ==================
+    Syntax            Description                                                             Availability
+    ================= ======================================================================= ==================
+    tma_lo            Low 32 bits of *trap memory address* register.                          GFX7, GFX8
+    tma_hi            High 32 bits of *trap memory address* register.                         GFX7, GFX8
+    [tma_lo]          Low 32 bits of *trap memory address* register (an alternative syntax).  GFX7, GFX8
+    [tma_hi]          High 32 bits of *trap memory address* register (an alternative syntax). GFX7, GFX8
+    ================= ======================================================================= ==================
 
-lwe
-~~~
+Note that *tma*, *tma_lo* and *tma_hi* are not accessible as assembler registers in GFX9,
+but *tma* is readable/writable with the help of *s_get_reg* and *s_set_reg* instructions.
 
-Specifies LOD warning status (LOD warning is disabled by default).
+.. _amdgpu_synid_flat_scratch:
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    lwe                                      Enables LOD warning.
-    ======================================== ================================================
-
-.. _amdgpu_synid_da:
-
-da
-~~
-
-Specifies if an array index must be sent to TA. By default, array index is not sent.
-
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    da                                       Send an array-index to TA.
-    ======================================== ================================================
+flat_scratch
+------------
 
-.. _amdgpu_synid_d16:
+Flat scratch address, 64-bits wide. Holds the base address of scratch memory.
 
-d16
-~~~
+    ================================== ================================================================
+    Syntax                             Description
+    ================================== ================================================================
+    flat_scratch                       64-bit *flat scratch* address register.
+    [flat_scratch]                     64-bit *flat scratch* address register (an alternative syntax).
+    [flat_scratch_lo,flat_scratch_hi]  64-bit *flat scratch* address register (an alternative syntax).
+    ================================== ================================================================
+
+High and low 32 bits of *flat scratch* address may be accessed as separate registers:
+
+    ========================= =========================================================================
+    Syntax                    Description
+    ========================= =========================================================================
+    flat_scratch_lo           Low 32 bits of *flat scratch* address register.
+    flat_scratch_hi           High 32 bits of *flat scratch* address register.
+    [flat_scratch_lo]         Low 32 bits of *flat scratch* address register (an alternative syntax).
+    [flat_scratch_hi]         High 32 bits of *flat scratch* address register (an alternative syntax).
+    ========================= =========================================================================
+
+.. _amdgpu_synid_xnack:
+
+xnack
+-----
+
+Xnack mask, 64-bits wide. Holds a 64-bit mask of which threads
+received an *XNACK* due to a vector memory operation.
 
-Specifies data size: 16 or 32 bits (32 bits by default). Not supported by GFX7.
+.. WARNING:: GFX7 does not support *xnack* feature. Not all GFX8 and GFX9 :ref:`processors<amdgpu-processors>` support *xnack* feature.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    d16                                      Enables 16-bits data mode.
+\
 
-                                             On loads, convert data in memory to 16-bit
-                                             format before storing it in VGPRs.
+    ============================== =====================================================
+    Syntax                         Description
+    ============================== =====================================================
+    xnack_mask                     64-bit *xnack mask* register.
+    [xnack_mask]                   64-bit *xnack mask* register (an alternative syntax).
+    [xnack_mask_lo,xnack_mask_hi]  64-bit *xnack mask* register (an alternative syntax).
+    ============================== =====================================================
 
-                                             For stores, convert 16-bit data in VGPRs to
-                                             32 bits before going to memory.
+High and low 32 bits of *xnack mask* may be accessed as separate registers:
 
-                                             Note that 16-bit data are stored in VGPRs
-                                             unpacked in GFX8.0. In GFX8.1 and GFX9 16-bit
-                                             data are packed.
-    ======================================== ================================================
+    ===================== ==============================================================
+    Syntax                Description
+    ===================== ==============================================================
+    xnack_mask_lo         Low 32 bits of *xnack mask* register.
+    xnack_mask_hi         High 32 bits of *xnack mask* register.
+    [xnack_mask_lo]       Low 32 bits of *xnack mask* register (an alternative syntax).
+    [xnack_mask_hi]       High 32 bits of *xnack mask* register (an alternative syntax).
+    ===================== ==============================================================
 
-.. _amdgpu_synid_a16:
+.. _amdgpu_synid_vcc:
 
-a16
-~~~
+vcc
+---
 
-Specifies size of image address components: 16 or 32 bits (32 bits by default). GFX9 only.
+Vector condition code, 64-bits wide. A bit mask with one bit per thread;
+it holds the result of a vector compare operation.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    a16                                      Enables 16-bits image address components.
-    ======================================== ================================================
+    ================ =========================================================================
+    Syntax           Description
+    ================ =========================================================================
+    vcc              64-bit *vector condition code* register.
+    [vcc]            64-bit *vector condition code* register (an alternative syntax).
+    [vcc_lo,vcc_hi]  64-bit *vector condition code* register (an alternative syntax).
+    ================ =========================================================================
 
-Miscellaneous Modifiers
------------------------
+High and low 32 bits of *vector condition code* may be accessed as separate registers:
 
-.. _amdgpu_synid_glc:
+    ================ =========================================================================
+    Syntax           Description
+    ================ =========================================================================
+    vcc_lo           Low 32 bits of *vector condition code* register.
+    vcc_hi           High 32 bits of *vector condition code* register.
+    [vcc_lo]         Low 32 bits of *vector condition code* register (an alternative syntax).
+    [vcc_hi]         High 32 bits of *vector condition code* register (an alternative syntax).
+    ================ =========================================================================
 
-glc
-~~~
+.. _amdgpu_synid_m0:
 
-This modifier has different meaning for loads, stores, and atomic operations.
-The default value is off (0).
+m0
+--
 
-See AMD documentation for details.
+A 32-bit memory register. It has various uses,
+including register indexing and bounds checking.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    glc                                      Set glc bit to 1.
-    ======================================== ================================================
+    =========== ===================================================
+    Syntax      Description
+    =========== ===================================================
+    m0          A 32-bit *memory* register.
+    [m0]        A 32-bit *memory* register (an alternative syntax).
+    =========== ===================================================
 
-.. _amdgpu_synid_slc:
+.. _amdgpu_synid_exec:
 
-slc
-~~~
+exec
+----
 
-Specifies cache policy. The default value is off (0).
+Execute mask, 64-bits wide. A bit mask with one bit per thread,
+which is applied to vector instructions and controls which threads execute
+and which ignore the instruction.
 
-See AMD documentation for details.
+    ===================== =================================================================
+    Syntax                Description
+    ===================== =================================================================
+    exec                  64-bit *execute mask* register.
+    [exec]                64-bit *execute mask* register (an alternative syntax).
+    [exec_lo,exec_hi]     64-bit *execute mask* register (an alternative syntax).
+    ===================== =================================================================
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    slc                                      Set slc bit to 1.
-    ======================================== ================================================
+High and low 32 bits of *execute mask* may be accessed as separate registers:
 
-.. _amdgpu_synid_tfe:
+    ===================== =================================================================
+    Syntax                Description
+    ===================== =================================================================
+    exec_lo               Low 32 bits of *execute mask* register.
+    exec_hi               High 32 bits of *execute mask* register.
+    [exec_lo]             Low 32 bits of *execute mask* register (an alternative syntax).
+    [exec_hi]             High 32 bits of *execute mask* register (an alternative syntax).
+    ===================== =================================================================
 
-tfe
-~~~
+.. _amdgpu_synid_vccz:
 
-Controls access to partially resident textures. The default value is off (0).
+vccz
+----
 
-See AMD documentation for details.
+A single bit-flag indicating that the :ref:`vcc<amdgpu_synid_vcc>` is all zeros.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    tfe                                      Set tfe bit to 1.
-    ======================================== ================================================
+.. WARNING:: This operand is not currently supported by AMDGPU assembler.
 
-.. _amdgpu_synid_nv:
+.. _amdgpu_synid_execz:
 
-nv
-~~
+execz
+-----
 
-Specifies if instruction is operating on non-volatile memory. By default, memory is volatile.
+A single bit flag indicating that the :ref:`exec<amdgpu_synid_exec>` is all zeros.
 
-GFX9 only.
+.. WARNING:: This operand is not currently supported by AMDGPU assembler.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    nv                                       Indicates that instruction operates on
-                                             non-volatile memory.
-    ======================================== ================================================
+.. _amdgpu_synid_scc:
 
-MUBUF/MTBUF Modifiers
----------------------
+scc
+---
 
-.. _amdgpu_synid_idxen:
+A single bit flag indicating the result of a scalar compare operation.
 
-idxen
-~~~~~
+.. WARNING:: This operand is not currently supported by AMDGPU assembler.
 
-Specifies whether address components include an index. By default, no components are used.
+.. _amdgpu_synid_ldsdirect:
 
-Can be used together with :ref:`offen<amdgpu_synid_offen>`.
+lds_direct
+----------
 
-Cannot be used with :ref:`addr64<amdgpu_synid_addr64>`.
+A special operand which supplies a 32-bit value
+fetched from *LDS* memory using :ref:`m0<amdgpu_synid_m0>` as an address.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    idxen                                    Address components include an index.
-    ======================================== ================================================
+.. WARNING:: This operand is not currently supported by AMDGPU assembler.
 
-.. _amdgpu_synid_offen:
+.. _amdgpu_synid_constant:
 
-offen
-~~~~~
+constant
+--------
 
-Specifies whether address components include an offset. By default, no components are used.
+A set of integer and floating-point *inline constants*:
 
-Can be used together with :ref:`idxen<amdgpu_synid_idxen>`.
+* :ref:`iconst<amdgpu_synid_iconst>`
+* :ref:`fconst<amdgpu_synid_fconst>`
 
-Cannot be used with :ref:`addr64<amdgpu_synid_addr64>`.
+These operands are encoded as a part of instruction.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    offen                                    Address components include an offset.
-    ======================================== ================================================
+If a number may be encoded as either
+a :ref:`literal<amdgpu_synid_literal>` or 
+an :ref:`inline constant<amdgpu_synid_constant>`,
+assembler selects the latter encoding as more efficient.
 
-.. _amdgpu_synid_addr64:
+.. _amdgpu_synid_iconst:
 
-addr64
-~~~~~~
+iconst
+------
 
-Specifies whether a 64-bit address is used. By default, no address is used.
+An :ref:`integer number<amdgpu_synid_integer_number>`
+encoded as an *inline constant*.
 
-GFX7 only. Cannot be used with :ref:`offen<amdgpu_synid_offen>` and
-:ref:`idxen<amdgpu_synid_idxen>` modifiers.
+Only a small fraction of integer numbers may be encoded as *inline constants*.
+They are enumerated in the table below.
+Other integer numbers have to be encoded as :ref:`literals<amdgpu_synid_literal>`.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    addr64                                   A 64-bit address is used.
-    ======================================== ================================================
+Integer *inline constants* are converted to
+:ref:`expected operand type<amdgpu_syn_instruction_type>`
+as described :ref:`here<amdgpu_synid_int_const_conv>`.
 
-.. _amdgpu_synid_buf_offset12:
+    ================================== ====================================
+    Value                              Note
+    ================================== ====================================
+    {0..64}                            Positive integer inline constants.
+    {-16..-1}                          Negative integer inline constants.
+    ================================== ====================================
 
-buf_offset12
-~~~~~~~~~~~~
+.. WARNING:: GFX7 does not support inline constants for *f16* operands.
 
-Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.
+There are also symbolic inline constants which provide read-only access to H/W registers.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    offset:{0..0xFFF}                        Specifies a 12-bit unsigned offset.
-    ======================================== ================================================
+.. WARNING:: These inline constants are not currently supported by AMDGPU assembler.
 
-glc
-~~~
+\
 
-See a description :ref:`here<amdgpu_synid_glc>`.
+    ======================== ================================================ =============
+    Syntax                   Note                                             Availability
+    ======================== ================================================ =============
+    shared_base              Base address of shared memory region.            GFX9
+    shared_limit             Address of the end of shared memory region.      GFX9
+    private_base             Base address of private memory region.           GFX9
+    private_limit            Address of the end of private memory region.     GFX9
+    pops_exiting_wave_id     A dedicated counter for POPS.                    GFX9
+    ======================== ================================================ =============
 
-slc
-~~~
+.. _amdgpu_synid_fconst:
 
-See a description :ref:`here<amdgpu_synid_slc>`.
+fconst
+------
 
-.. _amdgpu_synid_lds:
+A :ref:`floating-point number<amdgpu_synid_floating-point_number>`
+encoded as an *inline constant*.
 
-lds
-~~~
+Only a small fraction of floating-point numbers may be encoded as *inline constants*.
+They are enumerated in the table below.
+Other floating-point numbers have to be encoded as :ref:`literals<amdgpu_synid_literal>`.
 
-Specifies where to store the result: VGPRs or LDS (VGPRs by default).
+Floating-point *inline constants* are converted to
+:ref:`expected operand type<amdgpu_syn_instruction_type>`
+as described :ref:`here<amdgpu_synid_fp_const_conv>`.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    lds                                      Store result in LDS.
-    ======================================== ================================================
+    ================================== ===================================================== ==================
+    Value                              Note                                                  Availability
+    ================================== ===================================================== ==================
+    0.0                                The same as integer constant 0.                       All GPUs
+    0.5                                Floating-point constant 0.5                           All GPUs
+    1.0                                Floating-point constant 1.0                           All GPUs
+    2.0                                Floating-point constant 2.0                           All GPUs
+    4.0                                Floating-point constant 4.0                           All GPUs
+    -0.5                               Floating-point constant -0.5                          All GPUs
+    -1.0                               Floating-point constant -1.0                          All GPUs
+    -2.0                               Floating-point constant -2.0                          All GPUs
+    -4.0                               Floating-point constant -4.0                          All GPUs
+    0.1592                             1.0/(2.0*pi). Use only for 16-bit operands.           GFX8, GFX9
+    0.15915494                         1.0/(2.0*pi). Use only for 16- and 32-bit operands.   GFX8, GFX9
+    0.159154943091895317852646485335   1.0/(2.0*pi).                                         GFX8, GFX9
+    ================================== ===================================================== ==================
 
-tfe
-~~~
+.. WARNING:: GFX7 does not support inline constants for *f16* operands.
 
-See a description :ref:`here<amdgpu_synid_tfe>`.
+.. _amdgpu_synid_literal:
 
-.. _amdgpu_synid_dfmt:
+literal
+-------
 
-dfmt
-~~~~
+A literal is a 64-bit value which is encoded as a separate 32-bit dword in the instruction stream.
 
-TBD
+If a number may be encoded as either
+a :ref:`literal<amdgpu_synid_literal>` or 
+an :ref:`inline constant<amdgpu_synid_constant>`,
+assembler selects the latter encoding as more efficient.
 
-.. _amdgpu_synid_nfmt:
+Literals may be specified as :ref:`integer numbers<amdgpu_synid_integer_number>`,
+:ref:`floating-point numbers<amdgpu_synid_floating-point_number>` or
+:ref:`expressions<amdgpu_synid_expression>`
+(expressions are currently supported for 32-bit operands only).
 
-nfmt
-~~~~
+A 64-bit literal value is converted by assembler
+to an :ref:`expected operand type<amdgpu_syn_instruction_type>`
+as described :ref:`here<amdgpu_synid_lit_conv>`.
 
-TBD
+An instruction may use only one literal but several operands may refer the same literal.
 
-SMRD/SMEM Modifiers
--------------------
+.. _amdgpu_synid_uimm8:
 
-glc
-~~~
+uimm8
+-----
 
-See a description :ref:`here<amdgpu_synid_glc>`.
+A 8-bit positive :ref:`integer number<amdgpu_synid_integer_number>`.
+The value is encoded as part of the opcode so it is free to use.
 
-nv
-~~
+.. _amdgpu_synid_uimm32:
 
-See a description :ref:`here<amdgpu_synid_nv>`.
+uimm32
+------
 
-VINTRP Modifiers
-----------------
+A 32-bit positive :ref:`integer number<amdgpu_synid_integer_number>`.
+The value is stored as a separate 32-bit dword in the instruction stream.
 
-.. _amdgpu_synid_high:
+.. _amdgpu_synid_uimm20:
 
-high
-~~~~
+uimm20
+------
 
-Specifies which half of the LDS word to use. Low half of LDS word is used by default.
-GFX9 only.
+A 20-bit positive :ref:`integer number<amdgpu_synid_integer_number>`.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    high                                     Use high half of LDS word.
-    ======================================== ================================================
+.. _amdgpu_synid_uimm21:
 
-VOP1/VOP2 DPP Modifiers
------------------------
+uimm21
+------
 
-GFX8 and GFX9 only.
+A 21-bit positive :ref:`integer number<amdgpu_synid_integer_number>`.
 
-.. _amdgpu_synid_dpp_ctrl:
+.. WARNING:: Assembler currently supports 20-bit offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` as a replacement.
 
-dpp_ctrl
-~~~~~~~~
+.. _amdgpu_synid_simm21:
 
-Specifies how data are shared between threads. This is a mandatory modifier.
-There is no default value.
+simm21
+------
 
-Note. The lanes of a wavefront are organized in four banks and four rows.
+A 21-bit :ref:`integer number<amdgpu_synid_integer_number>`.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    quad_perm:[{0..3},{0..3},{0..3},{0..3}]  Full permute of 4 threads.
-    row_mirror                               Mirror threads within row.
-    row_half_mirror                          Mirror threads within 1/2 row (8 threads).
-    row_bcast:15                             Broadcast 15th thread of each row to next row.
-    row_bcast:31                             Broadcast thread 31 to rows 2 and 3.
-    wave_shl:1                               Wavefront left shift by 1 thread.
-    wave_rol:1                               Wavefront left rotate by 1 thread.
-    wave_shr:1                               Wavefront right shift by 1 thread.
-    wave_ror:1                               Wavefront right rotate by 1 thread.
-    row_shl:{1..15}                          Row shift left by 1-15 threads.
-    row_shr:{1..15}                          Row shift right by 1-15 threads.
-    row_ror:{1..15}                          Row rotate right by 1-15 threads.
-    ======================================== ================================================
+.. WARNING:: Assembler currently supports 20-bit unsigned offsets only .Use :ref:`uimm20<amdgpu_synid_uimm20>` as a replacement.
 
-.. _amdgpu_synid_row_mask:
+.. _amdgpu_synid_off:
 
-row_mask
-~~~~~~~~
+off
+---
 
-Controls which rows are enabled for data sharing. By default, all rows are enabled.
+A special entity which indicates that the value of this operand is not used.
 
-Note. The lanes of a wavefront are organized in four banks and four rows.
+    ================================== ===================================================
+    Syntax                             Description
+    ================================== ===================================================
+    off                                Indicates an unused operand.
+    ================================== ===================================================
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    row_mask:{0..15}                         Each of 4 bits in the mask controls one
-                                             row (0 - disabled, 1 - enabled).
-    ======================================== ================================================
 
-.. _amdgpu_synid_bank_mask:
+.. _amdgpu_synid_number:
 
-bank_mask
-~~~~~~~~~
+Numbers
+=======
 
-Controls which banks are enabled for data sharing. By default, all banks are enabled.
+.. _amdgpu_synid_integer_number:
 
-Note. The lanes of a wavefront are organized in four banks and four rows.
+Integer Numbers
+---------------
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    bank_mask:{0..15}                        Each of 4 bits in the mask controls one
-                                             bank (0 - disabled, 1 - enabled).
-    ======================================== ================================================
+Integer numbers are 64 bits wide.
+They may be specified in binary, octal, hexadecimal and decimal formats:
 
-.. _amdgpu_synid_bound_ctrl:
+    ============== ====================================
+    Format         Syntax
+    ============== ====================================
+    Decimal        [-]?[1-9][0-9]*
+    Binary         [-]?0b[01]+
+    Octal          [-]?0[0-7]+
+    Hexadecimal    [-]?0x[0-9a-fA-F]+
+    \              [-]?[0x]?[0-9][0-9a-fA-F]*[hH]
+    ============== ====================================
 
-bound_ctrl
-~~~~~~~~~~
+Examples:
 
-Controls data sharing when accessing an invalid lane. By default, data sharing with
-invalid lanes is disabled.
+.. code-block:: nasm
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    bound_ctrl:0                             Enables data sharing with invalid lanes.
-                                             Accessing data from an invalid lane will
-                                             return zero.
-    ======================================== ================================================
+  -1234
+  0b1010
+  010
+  0xff
+  0ffh
 
-VOP1/VOP2/VOPC SDWA Modifiers
------------------------------
+.. _amdgpu_synid_floating-point_number:
 
-GFX8 and GFX9 only.
+Floating-Point Numbers
+----------------------
 
-clamp
-~~~~~
+All floating-point numbers are handled as double (64 bits wide).
 
-See a description :ref:`here<amdgpu_synid_clamp>`.
+Floating-point numbers may be specified in hexadecimal and decimal formats:
 
-omod
-~~~~
+    ============== ======================================================== ========================================================
+    Format         Syntax                                                   Note
+    ============== ======================================================== ========================================================
+    Decimal        [-]?[0-9]*[.][0-9]*([eE][+-]?[0-9]*)?                    Must include either a decimal separator or an exponent.
+    Hexadecimal    [-]0x[0-9a-fA-F]*(.[0-9a-fA-F]*)?[pP][+-]?[0-9a-fA-F]+
+    ============== ======================================================== ========================================================
 
-See a description :ref:`here<amdgpu_synid_omod>`.
+Examples:
 
-GFX9 only.
+.. code-block:: nasm
 
-.. _amdgpu_synid_dst_sel:
+ -1.234
+ 234e2
+ -0x1afp-10
+ 0x.1afp10
 
-dst_sel
-~~~~~~~
+.. _amdgpu_synid_expression:
 
-Selects which bits in the destination are affected. By default, all bits are affected.
+Expressions
+===========
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    dst_sel:DWORD                            Use bits 31:0.
-    dst_sel:BYTE_0                           Use bits 7:0.
-    dst_sel:BYTE_1                           Use bits 15:8.
-    dst_sel:BYTE_2                           Use bits 23:16.
-    dst_sel:BYTE_3                           Use bits 31:24.
-    dst_sel:WORD_0                           Use bits 15:0.
-    dst_sel:WORD_1                           Use bits 31:16.
-    ======================================== ================================================
+An expression specifies an address or a numeric value.
+There are two kinds of expressions:
 
+* :ref:`Absolute<amdgpu_synid_absolute_expression>`.
+* :ref:`Relocatable<amdgpu_synid_relocatable_expression>`.
 
-.. _amdgpu_synid_dst_unused:
+.. _amdgpu_synid_absolute_expression:
 
-dst_unused
-~~~~~~~~~~
+Absolute Expressions
+--------------------
 
-Controls what to do with the bits in the destination which are not selected
-by :ref:`dst_sel<amdgpu_synid_dst_sel>`.
-By default, unused bits are preserved.
+The value of an absolute expression remains the same after program relocation.
+Absolute expressions must not include unassigned and relocatable values
+such as labels.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    dst_unused:UNUSED_PAD                    Pad with zeros.
-    dst_unused:UNUSED_SEXT                   Sign-extend upper bits, zero lower bits.
-    dst_unused:UNUSED_PRESERVE               Preserve bits.
-    ======================================== ================================================
+Examples:
 
-.. _amdgpu_synid_src0_sel:
+.. code-block:: nasm
 
-src0_sel
-~~~~~~~~
+    x = -1
+    y = x + 10
 
-Controls which bits in the src0 are used. By default, all bits are used.
+.. _amdgpu_synid_relocatable_expression:
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    src0_sel:DWORD                           Use bits 31:0.
-    src0_sel:BYTE_0                          Use bits 7:0.
-    src0_sel:BYTE_1                          Use bits 15:8.
-    src0_sel:BYTE_2                          Use bits 23:16.
-    src0_sel:BYTE_3                          Use bits 31:24.
-    src0_sel:WORD_0                          Use bits 15:0.
-    src0_sel:WORD_1                          Use bits 31:16.
-    ======================================== ================================================
+Relocatable Expressions
+-----------------------
 
-.. _amdgpu_synid_src1_sel:
+The value of a relocatable expression depends on program relocation.
 
-src1_sel
-~~~~~~~~
+Note that use of relocatable expressions is limited with branch targets
+and 32-bit :ref:`literals<amdgpu_synid_literal>`.
 
-Controls which bits in the src1 are used. By default, all bits are used.
+Addition information about relocation may be found :ref:`here<amdgpu-relocation-records>`.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    src1_sel:DWORD                           Use bits 31:0.
-    src1_sel:BYTE_0                          Use bits 7:0.
-    src1_sel:BYTE_1                          Use bits 15:8.
-    src1_sel:BYTE_2                          Use bits 23:16.
-    src1_sel:BYTE_3                          Use bits 31:24.
-    src1_sel:WORD_0                          Use bits 15:0.
-    src1_sel:WORD_1                          Use bits 31:16.
-    ======================================== ================================================
+Examples:
 
-VOP1/VOP2/VOPC SDWA Operand Modifiers
--------------------------------------
+.. code-block:: nasm
 
-Operand modifiers are not used separately. They are applied to source operands.
+    y = x + 10 // x is not yet defined. Undefined symbols are assumed to be PC-relative.
+    z = .
 
-GFX8 and GFX9 only.
+Expression Data Type
+--------------------
 
-abs
-~~~
+Expressions and operands of expressions are interpreted as 64-bit integers.
 
-See a description :ref:`here<amdgpu_synid_abs>`.
+Expressions may include 64-bit :ref:`floating-point numbers<amdgpu_synid_floating-point_number>` (double).
+However these operands are also handled as 64-bit integers
+using binary representation of specified floating-point numbers.
+No conversion from floating-point to integer is performed.
 
-neg
-~~~
+Examples:
 
-See a description :ref:`here<amdgpu_synid_neg>`.
+.. code-block:: nasm
 
-.. _amdgpu_synid_sext:
+    x = 0.1    // x is assigned an integer 4591870180066957722 which is a binary representation of 0.1.
+    y = x + x  // y is a sum of two integer values; it is not equal to 0.2!
 
-sext
-~~~~
+Syntax
+------
 
-Sign-extends value of a (sub-dword) operand to fill all 32 bits.
-Has no effect for 32-bit operands.
+Expressions are composed of
+:ref:`symbols<amdgpu_synid_symbol>`,
+:ref:`integer numbers<amdgpu_synid_integer_number>`,
+:ref:`floating-point numbers<amdgpu_synid_floating-point_number>`,
+:ref:`binary operators<amdgpu_synid_expression_bin_op>`,
+:ref:`unary operators<amdgpu_synid_expression_un_op>` and subexpressions.
 
-Valid for integer operands only.
+Expressions may also use "." which is a reference to the current PC (program counter).
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    sext(<operand>)                          Sign-extend operand value.
-    ======================================== ================================================
+The syntax of expressions is shown below::
 
-VOP3 Modifiers
---------------
+    expr ::= expr binop expr | primaryexpr ;
 
-.. _amdgpu_synid_vop3_op_sel:
+    primaryexpr ::= '(' expr ')' | symbol | number | '.' | unop primaryexpr ;
 
-vop3_op_sel
-~~~~~~~~~~~
+    binop ::= '&&'
+            | '||'
+            | '|'
+            | '^'
+            | '&'
+            | '!'
+            | '=='
+            | '!='
+            | '<>'
+            | '<'
+            | '<='
+            | '>'
+            | '>='
+            | '<<'
+            | '>>'
+            | '+'
+            | '-'
+            | '*'
+            | '/'
+            | '%' ;
 
-Selects the low [15:0] or high [31:16] operand bits for source and destination operands.
-By default, low bits are used for all operands.
+    unop ::= '~'
+           | '+'
+           | '-'
+           | '!' ;
 
-The number of values specified with the op_sel modifier must match the number of instruction
-operands (both source and destination). First value controls src0, second value controls src1
-and so on, except that the last value controls destination.
-The value 0 selects the low bits, while 1 selects the high bits.
+.. _amdgpu_synid_expression_bin_op:
 
-Note. op_sel modifier affects 16-bit operands only. For 32-bit operands the value specified
-by op_sel must be 0.
+Binary Operators
+----------------
 
-GFX9 only.
+Binary operators are described in the following table.
+They operate on and produce 64-bit integers.
+Operators with higher priority are performed first.
+
+    ========== ========= ===============================================
+    Operator   Priority  Meaning
+    ========== ========= ===============================================
+       \*         5      Integer multiplication.
+       /          5      Integer division.
+       %          5      Integer signed remainder.
+       \+         4      Integer addition.
+       \-         4      Integer subtraction.
+       <<         3      Integer shift left.
+       >>         3      Logical shift right.
+       ==         2      Equality comparison.
+       !=         2      Inequality comparison.
+       <>         2      Inequality comparison.
+       <          2      Signed less than comparison.
+       <=         2      Signed less than or equal comparison.
+       >          2      Signed greater than comparison.
+       >=         2      Signed greater than or equal comparison.
+      \|          1      Bitwise or.
+       ^          1      Bitwise xor.
+       &          1      Bitwise and.
+       &&         0      Logical and.
+       ||         0      Logical or.
+    ========== ========= ===============================================
+
+.. _amdgpu_synid_expression_un_op:
+
+Unary Operators
+---------------
 
-    ======================================== ============================================================
-    Syntax                                   Description
-    ======================================== ============================================================
-    op_sel:[{0..1},{0..1}]                   Select operand bits for instructions with 1 source operand.
-    op_sel:[{0..1},{0..1},{0..1}]            Select operand bits for instructions with 2 source operands.
-    op_sel:[{0..1},{0..1},{0..1},{0..1}]     Select operand bits for instructions with 3 source operands.
-    ======================================== ============================================================
+Unary operators are described in the following table.
+They operate on and produce 64-bit integers.
 
-.. _amdgpu_synid_clamp:
+    ========== ===============================================
+    Operator   Meaning
+    ========== ===============================================
+       !       Logical negation.
+       ~       Bitwise negation.
+       \+      Integer unary plus.
+       \-      Integer unary minus.
+    ========== ===============================================
 
-clamp
-~~~~~
+.. _amdgpu_synid_symbol:
 
-Clamp meaning depends on instruction.
+Symbols
+-------
 
-For *v_cmp* instructions, clamp modifier indicates that the compare signals
-if a floating point exception occurs. By default, signaling is disabled.
-Not supported by GFX7.
+A symbol is a named 64-bit value, representing a relocatable
+address or an absolute (non-relocatable) number.
 
-For integer operations, clamp modifier indicates that the result must be clamped
-to the largest and smallest representable value. By default, there is no clamping.
-Integer clamping is not supported by GFX7.
+Symbol names have the following syntax:
+    ``[a-zA-Z_.][a-zA-Z0-9_$.@]*``
 
-For floating point operations, clamp modifier indicates that the result must be clamped
-to the range [0.0, 1.0]. By default, there is no clamping.
+The table below provides several examples of syntax used for symbol definition.
 
-Note. Clamp modifier is applied after :ref:`output modifiers<amdgpu_synid_omod>` (if any).
+    ================ ==========================================================
+    Syntax           Meaning
+    ================ ==========================================================
+    .globl <S>       Declares a global symbol S without assigning it a value.
+    .set <S>, <E>    Assigns the value of an expression E to a symbol S.
+    <S> = <E>        Assigns the value of an expression E to a symbol S.
+    <S>:             Declares a label S and assigns it the current PC value.
+    ================ ==========================================================
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    clamp                                    Enables clamping (or signaling).
-    ======================================== ================================================
+A symbol may be used before it is declared or assigned;
+unassigned symbols are assumed to be PC-relative.
 
-.. _amdgpu_synid_omod:
+Addition information about symbols may be found :ref:`here<amdgpu-symbols>`.
 
-omod
-~~~~
+.. _amdgpu_synid_conv:
 
-Specifies if an output modifier must be applied to the result.
-By default, no output modifiers are applied.
+Conversions
+===========
 
-Note. Output modifiers are applied before :ref:`clamping<amdgpu_synid_clamp>` (if any).
+This section describes what happens when a 64-bit
+:ref:`integer number<amdgpu_synid_integer_number>`, a
+:ref:`floating-point numbers<amdgpu_synid_floating-point_number>` or a
+:ref:`symbol<amdgpu_synid_symbol>`
+is used for an operand which has a different type or size.
 
-Output modifiers are valid for f32 and f64 floating point results only.
-They must not be used with f16.
+Depending on operand kind, this conversion is performed by either assembler or AMDGPU H/W:
 
-Note. *v_cvt_f16_f32* is an exception. This instruction produces f16 result
-but accepts output modifiers.
+* Values encoded as :ref:`inline constants<amdgpu_synid_constant>` are handled by H/W.
+* Values encoded as :ref:`literals<amdgpu_synid_literal>` are converted by assembler.
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    mul:2                                    Multiply the result by 2.
-    mul:4                                    Multiply the result by 4.
-    div:2                                    Multiply the result by 0.5.
-    ======================================== ================================================
+.. _amdgpu_synid_const_conv:
 
-VOP3 Operand Modifiers
-----------------------
+Inline Constants
+----------------
 
-Operand modifiers are not used separately. They are applied to source operands.
+.. _amdgpu_synid_int_const_conv:
 
-.. _amdgpu_synid_abs:
+Integer Inline Constants
+~~~~~~~~~~~~~~~~~~~~~~~~
 
-abs
-~~~
+Integer :ref:`inline constants<amdgpu_synid_constant>`
+may be thought of as 64-bit
+:ref:`integer numbers<amdgpu_synid_integer_number>`;
+when used as operands they are truncated to the size of
+:ref:`expected operand type<amdgpu_syn_instruction_type>`.
+No data type conversions are performed.
 
-Computes absolute value of its operand. Applied before :ref:`neg<amdgpu_synid_neg>` (if any).
-Valid for floating point operands only.
+Examples:
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    abs(<operand>)                           Get absolute value of operand.
-    \|<operand>|                             The same as above.
-    ======================================== ================================================
+.. code-block:: nasm
 
-.. _amdgpu_synid_neg:
+    // GFX9
 
-neg
-~~~
+    v_add_u16 v0, -1, 0    // v0 = 0xFFFF
+    v_add_f16 v0, -1, 0    // v0 = 0xFFFF (NaN)
 
-Computes negative value of its operand. Applied after :ref:`abs<amdgpu_synid_abs>` (if any).
-Valid for floating point operands only.
+    v_add_u32 v0, -1, 0    // v0 = 0xFFFFFFFF
+    v_add_f32 v0, -1, 0    // v0 = 0xFFFFFFFF (NaN)
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    neg(<operand>)                           Get negative value of operand.
-    -<operand>                               The same as above.
-    ======================================== ================================================
+.. _amdgpu_synid_fp_const_conv:
 
-VOP3P Modifiers
----------------
+Floating-Point Inline Constants
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-This section describes modifiers of regular VOP3P instructions.
-*v_mad_mix* modifiers are described :ref:`in a separate section<amdgpu_synid_mad_mix>`.
+Floating-point :ref:`inline constants<amdgpu_synid_constant>`
+may be thought of as 64-bit
+:ref:`floating-point numbers<amdgpu_synid_floating-point_number>`;
+when used as operands they are converted to a floating-point number of
+:ref:`expected operand size<amdgpu_syn_instruction_type>`.
 
-GFX9 only.
+Examples:
 
-.. _amdgpu_synid_op_sel:
+.. code-block:: nasm
 
-op_sel
-~~~~~~
+    // GFX9
 
-Selects the low [15:0] or high [31:16] operand bits as input to the operation
-which results in the lower-half of the destination.
-By default, low bits are used for all operands.
+    v_add_f16 v0, 1.0, 0    // v0 = 0x3C00 (1.0)
+    v_add_u16 v0, 1.0, 0    // v0 = 0x3C00
 
-The number of values specified with the op_sel modifier must match the number of source
-operands. First value controls src0, second value controls src1 and so on.
-The value 0 selects the low bits, while 1 selects the high bits.
+    v_add_f32 v0, 1.0, 0    // v0 = 0x3F800000 (1.0)
+    v_add_u32 v0, 1.0, 0    // v0 = 0x3F800000
 
-    ======================================== =============================================================
-    Syntax                                   Description
-    ======================================== =============================================================
-    op_sel:[{0..1}]                          Select operand bits for instructions with 1 source operand.
-    op_sel:[{0..1},{0..1}]                   Select operand bits for instructions with 2 source operands.
-    op_sel:[{0..1},{0..1},{0..1}]            Select operand bits for instructions with 3 source operands.
-    ======================================== =============================================================
 
-.. _amdgpu_synid_op_sel_hi:
+.. _amdgpu_synid_lit_conv:
 
-op_sel_hi
-~~~~~~~~~
+Literals
+--------
 
-Selects the low [15:0] or high [31:16] operand bits as input to the operation
-which results in the upper-half of the destination.
-By default, high bits are used for all operands.
+.. _amdgpu_synid_int_lit_conv:
 
-The number of values specified with the op_sel_hi modifier must match the number of source
-operands. First value controls src0, second value controls src1 and so on.
-The value 0 selects the low bits, while 1 selects the high bits.
+Integer Literals
+~~~~~~~~~~~~~~~~
 
-    ======================================== =============================================================
-    Syntax                                   Description
-    ======================================== =============================================================
-    op_sel_hi:[{0..1}]                       Select operand bits for instructions with 1 source operand.
-    op_sel_hi:[{0..1},{0..1}]                Select operand bits for instructions with 2 source operands.
-    op_sel_hi:[{0..1},{0..1},{0..1}]         Select operand bits for instructions with 3 source operands.
-    ======================================== =============================================================
+Integer :ref:`literals<amdgpu_synid_literal>`
+are specified as 64-bit :ref:`integer numbers<amdgpu_synid_integer_number>`.
 
-.. _amdgpu_synid_neg_lo:
+When used as operands they are converted to
+:ref:`expected operand type<amdgpu_syn_instruction_type>` as described below.
 
-neg_lo
-~~~~~~
+    ============== ============== =============== ====================================================================
+    Expected type  Condition      Result          Note
+    ============== ============== =============== ====================================================================
+    i16, u16, b16  cond(num, 16)  num.u16         Truncate to 16 bits.
+    i32, u32, b32  cond(num, 32)  num.u32         Truncate to 32 bits.
+    i64            cond(num, 32)  {-1, num.i32}   Truncate to 32 bits and then sign-extend the result to 64 bits.
+    u64, b64       cond(num, 32)  { 0, num.u32}   Truncate to 32 bits and then zero-extend the result to 64 bits.
+    f16            cond(num, 16)  num.u16         Use low 16 bits as an f16 value.
+    f32            cond(num, 32)  num.u32         Use low 32 bits as an f32 value.
+    f64            cond(num, 32)  {num.u32, 0}    Use low 32 bits of the number as high 32 bits
+                                                  of the result; low 32 bits of the result are zeroed.
+    ============== ============== =============== ====================================================================
 
-Specifies whether to change sign of operand values selected by
-:ref:`op_sel<amdgpu_synid_op_sel>`. These values are then used
-as input to the operation which results in the upper-half of the destination.
+The condition *cond(X,S)* indicates if a 64-bit number *X*
+can be converted to a smaller size *S* by truncation of upper bits.
+There are two cases when the conversion is possible:
 
-The number of values specified with this modifier must match the number of source
-operands. First value controls src0, second value controls src1 and so on.
+* The truncated bits are all 0.
+* The truncated bits are all 1 and the value after truncation has its MSB bit set.
 
-The value 0 indicates that the corresponding operand value is used unmodified,
-the value 1 indicates that negative value of the operand must be used.
+Examples of valid literals:
 
-By default, operand values are used unmodified.
+.. code-block:: nasm
 
-This modifier is valid for floating point operands only.
+    // GFX9
 
-    ======================================== ==================================================================
-    Syntax                                   Description
-    ======================================== ==================================================================
-    neg_lo:[{0..1}]                          Select affected operands for instructions with 1 source operand.
-    neg_lo:[{0..1},{0..1}]                   Select affected operands for instructions with 2 source operands.
-    neg_lo:[{0..1},{0..1},{0..1}]            Select affected operands for instructions with 3 source operands.
-    ======================================== ==================================================================
+    v_add_u16 v0, 0xff00, v0                     // value after conversion: 0xff00
+    v_add_u16 v0, 0xffffffffffffff00, v0         // value after conversion: 0xff00
+    v_add_u16 v0, -256, v0                       // value after conversion: 0xff00
 
-.. _amdgpu_synid_neg_hi:
+    s_bfe_i64 s[0:1], 0xffefffff, s3             // value after conversion: 0xffffffffffefffff
+    s_bfe_u64 s[0:1], 0xffefffff, s3             // value after conversion: 0x00000000ffefffff
+    v_ceil_f64_e32 v[0:1], 0xffefffff            // value after conversion: 0xffefffff00000000 (-1.7976922776554302e308)
 
-neg_hi
-~~~~~~
+Examples of invalid literals:
 
-Specifies whether to change sign of operand values selected by
-:ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`. These values are then used
-as input to the operation which results in the upper-half of the destination.
+.. code-block:: nasm
 
-The number of values specified with this modifier must match the number of source
-operands. First value controls src0, second value controls src1 and so on.
+    // GFX9
 
-The value 0 indicates that the corresponding operand value is used unmodified,
-the value 1 indicates that negative value of the operand must be used.
+    v_add_u16 v0, 0x1ff00, v0               // conversion is not possible as truncated bits are not all 0 or 1
+    v_add_u16 v0, 0xffffffffffff00ff, v0    // conversion is not possible as truncated bits do not match MSB of the result
 
-By default, operand values are used unmodified.
+.. _amdgpu_synid_fp_lit_conv:
 
-This modifier is valid for floating point operands only.
+Floating-Point Literals
+~~~~~~~~~~~~~~~~~~~~~~~
 
-    ======================================== ==================================================================
-    Syntax                                   Description
-    ======================================== ==================================================================
-    neg_hi:[{0..1}]                          Select affected operands for instructions with 1 source operand.
-    neg_hi:[{0..1},{0..1}]                   Select affected operands for instructions with 2 source operands.
-    neg_hi:[{0..1},{0..1},{0..1}]            Select affected operands for instructions with 3 source operands.
-    ======================================== ==================================================================
+Floating-point :ref:`literals<amdgpu_synid_literal>` are specified as 64-bit
+:ref:`floating-point numbers<amdgpu_synid_floating-point_number>`.
 
-clamp
-~~~~~
+When used as operands they are converted to
+:ref:`expected operand type<amdgpu_syn_instruction_type>` as described below.
 
-See a description :ref:`here<amdgpu_synid_clamp>`.
+    ============== ============== ================= =================================================================
+    Expected type  Condition      Result            Note
+    ============== ============== ================= =================================================================
+    i16, u16, b16  cond(num, 16)  f16(num)          Convert to f16 and use bits of the result as an integer value.
+    i32, u32, b32  cond(num, 32)  f32(num)          Convert to f32 and use bits of the result as an integer value.
+    i64, u64, b64  false          \-                Conversion disabled because of an unclear semantics.
+    f16            cond(num, 16)  f16(num)          Convert to f16.
+    f32            cond(num, 32)  f32(num)          Convert to f32.
+    f64            true           {num.u32.hi, 0}   Use high 32 bits of the number as high 32 bits of the result;
+                                                    zero-fill low 32 bits of the result.
 
-.. _amdgpu_synid_mad_mix:
+                                                    Note that the result may differ from the original number.
+    ============== ============== ================= =================================================================
 
-VOP3P V_MAD_MIX Modifiers
--------------------------
+The condition *cond(X,S)* indicates if an f64 number *X* can be converted
+to a smaller *S*-bit floating-point type without overflow or underflow.
+Precision lost is allowed.
 
-These instructions use VOP3P format but have different modifiers.
+Examples of valid literals:
 
-GFX9 only.
+.. code-block:: nasm
 
-.. _amdgpu_synid_mad_mix_op_sel:
+    // GFX9
 
-mad_mix_op_sel
-~~~~~~~~~~~~~~
+    v_add_f16 v1, 65500.0, v2
+    v_add_f32 v1, 65600.0, v2
 
-This operand has meaning only for 16-bit source operands as indicated by
-:ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
-It specifies to select either the low [15:0] or high [31:16] operand bits
-as input to the operation.
+                                                 // value before conversion: 0x7fefffffffffffff (1.7976931348623157e308)
+    v_ceil_f64 v[0:1], 1.7976931348623157e308    // value after conversion:  0x7fefffff00000000 (1.7976922776554302e308)
 
-The value 0 indicates the low bits, the value 1 indicates the high 16 bits.
-By default, low bits are used for all operands.
+Examples of invalid literals:
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    op_sel:[{0..1},{0..1},{0..1}]            Select location of each 16-bit source operand.
-    ======================================== ================================================
+.. code-block:: nasm
 
-.. _amdgpu_synid_mad_mix_op_sel_hi:
+    // GFX9
 
-mad_mix_op_sel_hi
-~~~~~~~~~~~~~~~~~
+    v_add_f16 v1, 65600.0, v2                    // cannot be converted to f16 because of overflow
 
-Selects the size of source operands: either 32 bits or 16 bits.
-By default, 32 bits are used for all source operands.
+.. _amdgpu_synid_exp_conv:
 
-The value 0 indicates 32 bits, the value 1 indicates 16 bits.
-The location of 16 bits in the operand may be specified by
-:ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>`.
+Expressions
+~~~~~~~~~~~
 
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    op_sel_hi:[{0..1},{0..1},{0..1}]         Select size of each source operand.
-    ======================================== ================================================
+Expressions operate with and result in 64-bit integers.
 
-abs
-~~~
+When used as operands they are truncated to
+:ref:`expected operand size<amdgpu_syn_instruction_type>`.
+No data type conversions are performed.
 
-See a description :ref:`here<amdgpu_synid_abs>`.
+Examples:
 
-neg
-~~~
+.. code-block:: nasm
 
-See a description :ref:`here<amdgpu_synid_neg>`.
+    // GFX9
 
-clamp
-~~~~~
+    x = 0.1
+    v_sqrt_f32 v0, x           // v0 = [low 32 bits of 0.1 (double)]
+    v_sqrt_f32 v0, (0.1 + 0)   // the same as above
+    v_sqrt_f32 v0, 0.1         // v0 = [0.1 (double) converted to float]
 
-See a description :ref:`here<amdgpu_synid_clamp>`.

diff --git a/docs/AMDGPUUsage.rst b/docs/AMDGPUUsage.rst
index 5ca4975..c60d60a 100644 (file)
--- a/docs/AMDGPUUsage.rst
+++ b/docs/AMDGPUUsage.rst
@@ -4558,21 +4558,26 @@ Instructions
 .. toctree::
    :hidden:
 
-   AMDGPUAsmGFX7
-   AMDGPUAsmGFX8
-   AMDGPUAsmGFX9
+   AMDGPU/AMDGPUAsmGFX7
+   AMDGPU/AMDGPUAsmGFX8
+   AMDGPU/AMDGPUAsmGFX9
+   AMDGPUModifierSyntax
    AMDGPUOperandSyntax
+   AMDGPUInstructionSyntax
+   AMDGPUInstructionNotation
 
-An instruction has the following syntax:
+An instruction has the following :doc:`syntax<AMDGPUInstructionSyntax>`:
 
-    *<opcode> <operand0>, <operand1>,... <modifier0> <modifier1>...*
+    ``<``\ *opcode*\ ``>    <``\ *operand0*\ ``>, <``\ *operand1*\ ``>,...    <``\ *modifier0*\ ``> <``\ *modifier1*\ ``>...``
 
-Note that operands are normally comma-separated while modifiers are space-separated.
+:doc:`Operands<AMDGPUOperandSyntax>` are normally comma-separated while
+:doc:`modifiers<AMDGPUModifierSyntax>` are space-separated.
 
-The order of operands and modifiers is fixed. Most modifiers are optional and may be omitted.
+The order of *operands* and *modifiers* is fixed.
+Most *modifiers* are optional and may be omitted.
 
-See detailed instruction syntax description for :doc:`GFX7<AMDGPUAsmGFX7>`,
-:doc:`GFX8<AMDGPUAsmGFX8>` and :doc:`GFX9<AMDGPUAsmGFX9>`.
+See detailed instruction syntax description for :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`,
+:doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>` and :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`.
 
 Note that features under development are not included in this description.
 
@@ -4583,22 +4588,12 @@ operands, refer to one of instruction set architecture manuals
 Operands
 ~~~~~~~~
 
-The following syntax for register operands is supported:
-
-* SGPR registers: s0, ... or s[0], ...
-* VGPR registers: v0, ... or v[0], ...
-* TTMP registers: ttmp0, ... or ttmp[0], ...
-* Special registers: exec (exec_lo, exec_hi), vcc (vcc_lo, vcc_hi), flat_scratch (flat_scratch_lo, flat_scratch_hi)
-* Special trap registers: tba (tba_lo, tba_hi), tma (tma_lo, tma_hi)
-* Register pairs, quads, etc: s[2:3], v[10:11], ttmp[5:6], s[4:7], v[12:15], ttmp[4:7], s[8:15], ...
-* Register lists: [s0, s1], [ttmp0, ttmp1, ttmp2, ttmp3]
-* Register index expressions: v[2*2], s[1-1:2-1]
-* 'off' indicates that an operand is not enabled
+Detailed description of operands may be found :doc:`here<AMDGPUOperandSyntax>`.
 
 Modifiers
 ~~~~~~~~~
 
-Detailed description of modifiers may be found :doc:`here<AMDGPUOperandSyntax>`.
+Detailed description of modifiers may be found :doc:`here<AMDGPUModifierSyntax>`.
 
 Instruction Examples
 ~~~~~~~~~~~~~~~~~~~~