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x86/intel: force tsc to be reliable on Baytrail
author
Chih-Wei Huang
<cwhuang@linux.org.tw>
Sun, 8 Feb 2015 15:39:05 +0000
(23:39 +0800)
committer
Chih-Wei Huang
<cwhuang@linux.org.tw>
Mon, 13 Apr 2015 16:41:51 +0000
(
00:41
+0800)
arch/x86/kernel/cpu/intel.c
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diff --git
a/arch/x86/kernel/cpu/intel.c
b/arch/x86/kernel/cpu/intel.c
index
50163fa
..
ae2ab91
100644
(file)
--- a/
arch/x86/kernel/cpu/intel.c
+++ b/
arch/x86/kernel/cpu/intel.c
@@
-95,6
+95,8
@@
static void early_init_intel(struct cpuinfo_x86 *c)
/* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
if (c->x86 == 6) {
switch (c->x86_model) {
+ case 0x37: /* ValleyView */
+ set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
case 0x27: /* Penwell */
case 0x35: /* Cloverview */
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);