arm64: dts: ls1012a: Fix incorrect I2C clock divider

Ls1012a platform, the i2c input clock is actually platform pll CLK / 4
(this is the hardware connection), other clock divider can not get the
correct i2c clock, resulting in the output of SCL pin clock is not
accurate.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index ec6257a..124a7e2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -323,7 +323,7 @@
                        #size-cells = <0>;
                        reg = <0x0 0x2180000 0x0 0x10000>;
                        interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clockgen 4 0>;
+                       clocks = <&clockgen 4 3>;
                        status = "disabled";
                };
 
@@ -333,7 +333,7 @@
                        #size-cells = <0>;
                        reg = <0x0 0x2190000 0x0 0x10000>;
                        interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clockgen 4 0>;
+                       clocks = <&clockgen 4 3>;
                        status = "disabled";
                };