// ARM32::AssemblerARM32::vpop()
// ARM32::AssemblerARM32::vpush()
// ARM32::AssemblerARM:rbit().
+ // ARM32::AssemblerARM::veord()
#endif
DISALLOW_ALLOCATION();
emitVFPddd(Cond, VdivdOpcode, Dd, Dn, Dm);
}
+void AssemblerARM32::veord(const Operand *OpDd, const Operand *OpDn,
+ const Operand *OpDm) {
+ // VEOR - ARM secdtion A8.8.315, encoding A1:
+ // veor<c> <Dd>, <Dn>, <Dm>
+ //
+ // 111100110D00nnnndddd0001N0M1mmmm where Ddddd=Dd, Nnnnn=Dn, and Mmmmm=Dm.
+ constexpr const char *Veord = "veord";
+ IValueT Dd = encodeDRegister(OpDd, "Dd", Veord);
+ IValueT Dn = encodeDRegister(OpDn, "Dn", Veord);
+ IValueT Dm = encodeDRegister(OpDm, "Dm", Veord);
+ AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+ const IValueT Encoding =
+ B25 | B24 | B8 | B4 |
+ (encodeCondition(CondARM32::Cond::kNone) << kConditionShift) |
+ (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |
+ (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) |
+ (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
+ emitInst(Encoding);
+}
+
void AssemblerARM32::vldrd(const Operand *OpDd, const Operand *OpAddress,
CondARM32::Cond Cond, const TargetInfo &TInfo) {
// VLDR - ARM section A8.8.333, encoding A1.
void vdivs(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
CondARM32::Cond Cond);
+ void veord(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm);
+
void vldrd(const Operand *OpDd, const Operand *OpAddress,
CondARM32::Cond Cond, const TargetInfo &TInfo);
assert(!Asm->needsTextFixup());
}
+template <> void InstARM32Veor::emitIAS(const Cfg *Func) const {
+ auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+ const Variable *Dest = getDest();
+ assert(Dest->getType() == IceType_f64);
+ Asm->veord(Dest, getSrc(0), getSrc(1));
+ assert(!Asm->needsTextFixup());
+}
+
template <> void InstARM32Vsub::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
const Variable *Dest = getDest();
--- /dev/null
+; Show that we know how to translate veor. Does this by noting that
+; loading a double 0.0 introduces a veor.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
+; RUN: | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN: --args -Om1 \
+; RUN: | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
+; RUN: | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN: --args -Om1 \
+; RUN: | FileCheck %s --check-prefix=DIS
+
+define internal double @testVeor() {
+; ASM-LABEL: testVeor:
+; DIS: 00000000 <testVeor>:
+
+entry:
+; ASM: .LtestVeor$entry:
+
+ ret double 0.0
+
+; ASM: veor.f64 d0, d0, d0
+; DIS: 0: f3000110
+; IASM-NOT: veor
+
+}