/* Functions required by the cgen interface. These functions add various
kinds of writes to the write queue. */
+void sim_queue_bi_write (SIM_CPU *cpu, BI *target, BI value)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_BI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.bi_write.target = target;
+ element->kinds.bi_write.value = value;
+}
+
void sim_queue_qi_write (SIM_CPU *cpu, UQI *target, UQI value)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_QI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
element->kinds.qi_write.target = target;
element->kinds.qi_write.value = value;
}
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_SI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
element->kinds.si_write.target = target;
element->kinds.si_write.value = value;
}
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_SF_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
element->kinds.sf_write.target = target;
element->kinds.sf_write.value = value;
}
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_PC_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
element->kinds.pc_write.value = value;
}
+void sim_queue_fn_hi_write (
+ SIM_CPU *cpu,
+ void (*write_function)(SIM_CPU *cpu, UINT, UHI),
+ UINT regno,
+ UHI value
+)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_FN_HI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.fn_hi_write.function = write_function;
+ element->kinds.fn_hi_write.regno = regno;
+ element->kinds.fn_hi_write.value = value;
+}
+
void sim_queue_fn_si_write (
SIM_CPU *cpu,
void (*write_function)(SIM_CPU *cpu, UINT, USI),
UINT regno,
- SI value
+ USI value
)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_FN_SI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
element->kinds.fn_si_write.function = write_function;
element->kinds.fn_si_write.regno = regno;
element->kinds.fn_si_write.value = value;
}
+void sim_queue_fn_sf_write (
+ SIM_CPU *cpu,
+ void (*write_function)(SIM_CPU *cpu, UINT, SF),
+ UINT regno,
+ SF value
+)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_FN_SF_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.fn_sf_write.function = write_function;
+ element->kinds.fn_sf_write.regno = regno;
+ element->kinds.fn_sf_write.value = value;
+}
+
void sim_queue_fn_di_write (
SIM_CPU *cpu,
void (*write_function)(SIM_CPU *cpu, UINT, DI),
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_FN_DI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
element->kinds.fn_di_write.function = write_function;
element->kinds.fn_di_write.regno = regno;
element->kinds.fn_di_write.value = value;
}
+void sim_queue_fn_xi_write (
+ SIM_CPU *cpu,
+ void (*write_function)(SIM_CPU *cpu, UINT, SI *),
+ UINT regno,
+ SI *value
+)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_FN_XI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.fn_xi_write.function = write_function;
+ element->kinds.fn_xi_write.regno = regno;
+ element->kinds.fn_xi_write.value[0] = value[0];
+ element->kinds.fn_xi_write.value[1] = value[1];
+ element->kinds.fn_xi_write.value[2] = value[2];
+ element->kinds.fn_xi_write.value[3] = value[3];
+}
+
void sim_queue_fn_df_write (
SIM_CPU *cpu,
- void (*write_function)(SIM_CPU *cpu, UINT, DI),
+ void (*write_function)(SIM_CPU *cpu, UINT, DF),
UINT regno,
DF value
)
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_FN_DF_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
element->kinds.fn_df_write.function = write_function;
element->kinds.fn_df_write.regno = regno;
element->kinds.fn_df_write.value = value;
}
+void sim_queue_fn_pc_write (
+ SIM_CPU *cpu,
+ void (*write_function)(SIM_CPU *cpu, USI),
+ USI value
+)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_FN_PC_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.fn_pc_write.function = write_function;
+ element->kinds.fn_pc_write.value = value;
+}
+
void sim_queue_mem_qi_write (SIM_CPU *cpu, SI address, QI value)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_MEM_QI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
element->kinds.mem_qi_write.address = address;
element->kinds.mem_qi_write.value = value;
}
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_MEM_HI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
element->kinds.mem_hi_write.address = address;
element->kinds.mem_hi_write.value = value;
}
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_MEM_SI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
element->kinds.mem_si_write.address = address;
element->kinds.mem_si_write.value = value;
}
+void sim_queue_mem_di_write (SIM_CPU *cpu, SI address, DI value)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_MEM_DI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.mem_di_write.address = address;
+ element->kinds.mem_di_write.value = value;
+}
+
+void sim_queue_mem_df_write (SIM_CPU *cpu, SI address, DF value)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_MEM_DF_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.mem_df_write.address = address;
+ element->kinds.mem_df_write.value = value;
+}
+
+void sim_queue_mem_xi_write (SIM_CPU *cpu, SI address, SI *value)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_MEM_XI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.mem_xi_write.address = address;
+ element->kinds.mem_xi_write.value[0] = value[0];
+ element->kinds.mem_xi_write.value[1] = value[1];
+ element->kinds.mem_xi_write.value[2] = value[2];
+ element->kinds.mem_xi_write.value[3] = value[3];
+}
+
+void sim_queue_fn_mem_qi_write (
+ SIM_CPU *cpu,
+ void (*write_function)(SIM_CPU *cpu, IADDR, SI, QI),
+ SI address,
+ QI value
+)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_FN_MEM_QI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.fn_mem_qi_write.function = write_function;
+ element->kinds.fn_mem_qi_write.address = address;
+ element->kinds.fn_mem_qi_write.value = value;
+}
+
+void sim_queue_fn_mem_hi_write (
+ SIM_CPU *cpu,
+ void (*write_function)(SIM_CPU *cpu, IADDR, SI, HI),
+ SI address,
+ HI value
+)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_FN_MEM_HI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.fn_mem_hi_write.function = write_function;
+ element->kinds.fn_mem_hi_write.address = address;
+ element->kinds.fn_mem_hi_write.value = value;
+}
+
+void sim_queue_fn_mem_si_write (
+ SIM_CPU *cpu,
+ void (*write_function)(SIM_CPU *cpu, IADDR, SI, SI),
+ SI address,
+ SI value
+)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_FN_MEM_SI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.fn_mem_si_write.function = write_function;
+ element->kinds.fn_mem_si_write.address = address;
+ element->kinds.fn_mem_si_write.value = value;
+}
+
+void sim_queue_fn_mem_di_write (
+ SIM_CPU *cpu,
+ void (*write_function)(SIM_CPU *cpu, IADDR, SI, DI),
+ SI address,
+ DI value
+)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_FN_MEM_DI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.fn_mem_di_write.function = write_function;
+ element->kinds.fn_mem_di_write.address = address;
+ element->kinds.fn_mem_di_write.value = value;
+}
+
+void sim_queue_fn_mem_df_write (
+ SIM_CPU *cpu,
+ void (*write_function)(SIM_CPU *cpu, IADDR, SI, DF),
+ SI address,
+ DF value
+)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_FN_MEM_DF_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.fn_mem_df_write.function = write_function;
+ element->kinds.fn_mem_df_write.address = address;
+ element->kinds.fn_mem_df_write.value = value;
+}
+
+void sim_queue_fn_mem_xi_write (
+ SIM_CPU *cpu,
+ void (*write_function)(SIM_CPU *cpu, IADDR, SI, SI *),
+ SI address,
+ SI *value
+)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_FN_MEM_XI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.fn_mem_xi_write.function = write_function;
+ element->kinds.fn_mem_xi_write.address = address;
+ element->kinds.fn_mem_xi_write.value[0] = value[0];
+ element->kinds.fn_mem_xi_write.value[1] = value[1];
+ element->kinds.fn_mem_xi_write.value[2] = value[2];
+ element->kinds.fn_mem_xi_write.value[3] = value[3];
+}
+
/* Execute a write stored on the write queue. */
void
cgen_write_queue_element_execute (SIM_CPU *cpu, CGEN_WRITE_QUEUE_ELEMENT *item)
IADDR pc;
switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item))
{
+ case CGEN_BI_WRITE:
+ *item->kinds.bi_write.target = item->kinds.bi_write.value;
+ break;
case CGEN_QI_WRITE:
*item->kinds.qi_write.target = item->kinds.qi_write.value;
break;
case CGEN_PC_WRITE:
CPU_PC_SET (cpu, item->kinds.pc_write.value);
break;
+ case CGEN_FN_HI_WRITE:
+ item->kinds.fn_hi_write.function (cpu,
+ item->kinds.fn_hi_write.regno,
+ item->kinds.fn_hi_write.value);
+ break;
case CGEN_FN_SI_WRITE:
item->kinds.fn_si_write.function (cpu,
item->kinds.fn_si_write.regno,
item->kinds.fn_si_write.value);
break;
+ case CGEN_FN_SF_WRITE:
+ item->kinds.fn_sf_write.function (cpu,
+ item->kinds.fn_sf_write.regno,
+ item->kinds.fn_sf_write.value);
+ break;
case CGEN_FN_DI_WRITE:
item->kinds.fn_di_write.function (cpu,
item->kinds.fn_di_write.regno,
item->kinds.fn_df_write.regno,
item->kinds.fn_df_write.value);
break;
+ case CGEN_FN_XI_WRITE:
+ item->kinds.fn_xi_write.function (cpu,
+ item->kinds.fn_xi_write.regno,
+ item->kinds.fn_xi_write.value);
+ break;
+ case CGEN_FN_PC_WRITE:
+ item->kinds.fn_pc_write.function (cpu, item->kinds.fn_pc_write.value);
+ break;
case CGEN_MEM_QI_WRITE:
- pc = CPU_PC_GET (cpu);
+ pc = item->insn_address;
SETMEMQI (cpu, pc, item->kinds.mem_qi_write.address,
item->kinds.mem_qi_write.value);
break;
case CGEN_MEM_HI_WRITE:
- pc = CPU_PC_GET (cpu);
+ pc = item->insn_address;
SETMEMHI (cpu, pc, item->kinds.mem_hi_write.address,
item->kinds.mem_hi_write.value);
break;
case CGEN_MEM_SI_WRITE:
- pc = CPU_PC_GET (cpu);
+ pc = item->insn_address;
SETMEMSI (cpu, pc, item->kinds.mem_si_write.address,
item->kinds.mem_si_write.value);
break;
+ case CGEN_MEM_DI_WRITE:
+ pc = item->insn_address;
+ SETMEMDI (cpu, pc, item->kinds.mem_di_write.address,
+ item->kinds.mem_di_write.value);
+ break;
+ case CGEN_MEM_DF_WRITE:
+ pc = item->insn_address;
+ SETMEMDF (cpu, pc, item->kinds.mem_df_write.address,
+ item->kinds.mem_df_write.value);
+ break;
+ case CGEN_MEM_XI_WRITE:
+ pc = item->insn_address;
+ SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address,
+ item->kinds.mem_xi_write.value[0]);
+ SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 4,
+ item->kinds.mem_xi_write.value[1]);
+ SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 8,
+ item->kinds.mem_xi_write.value[2]);
+ SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 12,
+ item->kinds.mem_xi_write.value[3]);
+ break;
+ case CGEN_FN_MEM_QI_WRITE:
+ pc = item->insn_address;
+ item->kinds.fn_mem_qi_write.function (cpu, pc,
+ item->kinds.fn_mem_qi_write.address,
+ item->kinds.fn_mem_qi_write.value);
+ break;
+ case CGEN_FN_MEM_HI_WRITE:
+ pc = item->insn_address;
+ item->kinds.fn_mem_hi_write.function (cpu, pc,
+ item->kinds.fn_mem_hi_write.address,
+ item->kinds.fn_mem_hi_write.value);
+ break;
+ case CGEN_FN_MEM_SI_WRITE:
+ pc = item->insn_address;
+ item->kinds.fn_mem_si_write.function (cpu, pc,
+ item->kinds.fn_mem_si_write.address,
+ item->kinds.fn_mem_si_write.value);
+ break;
+ case CGEN_FN_MEM_DI_WRITE:
+ pc = item->insn_address;
+ item->kinds.fn_mem_di_write.function (cpu, pc,
+ item->kinds.fn_mem_di_write.address,
+ item->kinds.fn_mem_di_write.value);
+ break;
+ case CGEN_FN_MEM_DF_WRITE:
+ pc = item->insn_address;
+ item->kinds.fn_mem_df_write.function (cpu, pc,
+ item->kinds.fn_mem_df_write.address,
+ item->kinds.fn_mem_df_write.value);
+ break;
+ case CGEN_FN_MEM_XI_WRITE:
+ pc = item->insn_address;
+ item->kinds.fn_mem_xi_write.function (cpu, pc,
+ item->kinds.fn_mem_xi_write.address,
+ item->kinds.fn_mem_xi_write.value);
+ break;
default:
+ abort ();
break; /* FIXME: for now....print message later. */
}
}
/* Kinds of writes stored on the write queue. */
enum cgen_write_queue_kind {
- CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
+ CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
CGEN_PC_WRITE,
- CGEN_FN_SI_WRITE, CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
- CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE,
+ CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_SF_WRITE,
+ CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
+ CGEN_FN_XI_WRITE, CGEN_FN_PC_WRITE,
+ CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE, CGEN_MEM_DI_WRITE,
+ CGEN_MEM_DF_WRITE, CGEN_MEM_XI_WRITE,
+ CGEN_FN_MEM_QI_WRITE, CGEN_FN_MEM_HI_WRITE, CGEN_FN_MEM_SI_WRITE,
+ CGEN_FN_MEM_DI_WRITE, CGEN_FN_MEM_DF_WRITE, CGEN_FN_MEM_XI_WRITE,
CGEN_NUM_WRITE_KINDS
};
/* Element of the write queue. */
typedef struct {
enum cgen_write_queue_kind kind; /* Used to select union member below. */
+ IADDR insn_address; /* Address of the insn performing the write. */
union {
struct {
+ BI *target;
+ BI value;
+ } bi_write;
+ struct {
UQI *target;
QI value;
} qi_write;
} pc_write;
struct {
UINT regno;
+ UHI value;
+ void (*function)(SIM_CPU *, UINT, UHI);
+ } fn_hi_write;
+ struct {
+ UINT regno;
SI value;
void (*function)(SIM_CPU *, UINT, USI);
} fn_si_write;
struct {
UINT regno;
+ SF value;
+ void (*function)(SIM_CPU *, UINT, SF);
+ } fn_sf_write;
+ struct {
+ UINT regno;
DI value;
void (*function)(SIM_CPU *, UINT, DI);
} fn_di_write;
struct {
UINT regno;
- DI value;
- void (*function)(SIM_CPU *, UINT, DI);
+ DF value;
+ void (*function)(SIM_CPU *, UINT, DF);
} fn_df_write;
struct {
+ UINT regno;
+ SI value[4];
+ void (*function)(SIM_CPU *, UINT, SI *);
+ } fn_xi_write;
+ struct {
+ USI value;
+ void (*function)(SIM_CPU *, USI);
+ } fn_pc_write;
+ struct {
SI address;
QI value;
} mem_qi_write;
SI address;
SI value;
} mem_si_write;
+ struct {
+ SI address;
+ DI value;
+ } mem_di_write;
+ struct {
+ SI address;
+ DF value;
+ } mem_df_write;
+ struct {
+ SI address;
+ SI value[4];
+ } mem_xi_write;
+ struct {
+ SI address;
+ QI value;
+ void (*function)(SIM_CPU *, IADDR, SI, QI);
+ } fn_mem_qi_write;
+ struct {
+ SI address;
+ HI value;
+ void (*function)(SIM_CPU *, IADDR, SI, HI);
+ } fn_mem_hi_write;
+ struct {
+ SI address;
+ SI value;
+ void (*function)(SIM_CPU *, IADDR, SI, SI);
+ } fn_mem_si_write;
+ struct {
+ SI address;
+ DI value;
+ void (*function)(SIM_CPU *, IADDR, SI, DI);
+ } fn_mem_di_write;
+ struct {
+ SI address;
+ DF value;
+ void (*function)(SIM_CPU *, IADDR, SI, DF);
+ } fn_mem_df_write;
+ struct {
+ SI address;
+ SI value[4];
+ void (*function)(SIM_CPU *, IADDR, SI, SI *);
+ } fn_mem_xi_write;
} kinds;
} CGEN_WRITE_QUEUE_ELEMENT;
#define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)
+#define CGEN_WRITE_QUEUE_ELEMENT_IADDR(element) ((element)->insn_address)
extern void cgen_write_queue_element_execute (
SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *
/* Instance of the queue for parallel write-after support. */
/* FIXME: Should be dynamic? */
-#define CGEN_WRITE_QUEUE_SIZE (4 * 4) /* 4 writes x 4 insns -- for now. */
+#define CGEN_WRITE_QUEUE_SIZE (64 * 4) /* 64 writes x 4 insns -- for now. */
typedef struct {
int index;
extern CGEN_WRITE_QUEUE_ELEMENT *cgen_write_queue_overflow (CGEN_WRITE_QUEUE *);
/* Functions for queuing writes. Used by semantic code. */
+extern void sim_queue_bi_write (SIM_CPU *, BI *, BI);
extern void sim_queue_qi_write (SIM_CPU *, UQI *, UQI);
extern void sim_queue_si_write (SIM_CPU *, SI *, SI);
extern void sim_queue_sf_write (SIM_CPU *, SI *, SF);
extern void sim_queue_pc_write (SIM_CPU *, USI);
-extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, SI);
+extern void sim_queue_fn_hi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, UHI), UINT, UHI);
+extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, USI);
+extern void sim_queue_fn_sf_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SF), UINT, SF);
extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI);
-extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DF);
+extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DF), UINT, DF);
+extern void sim_queue_fn_xi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SI *), UINT, SI *);
+extern void sim_queue_fn_pc_write (SIM_CPU *, void (*)(SIM_CPU *, USI), USI);
extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);
+extern void sim_queue_mem_di_write (SIM_CPU *, SI, DI);
+extern void sim_queue_mem_df_write (SIM_CPU *, SI, DF);
+extern void sim_queue_mem_xi_write (SIM_CPU *, SI, SI *);
+
+extern void sim_queue_fn_mem_qi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, QI), SI, QI);
+extern void sim_queue_fn_mem_hi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, HI), SI, HI);
+extern void sim_queue_fn_mem_si_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI), SI, SI);
+extern void sim_queue_fn_mem_di_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DI), SI, DI);
+extern void sim_queue_fn_mem_df_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DF), SI, DF);
+extern void sim_queue_fn_mem_xi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI *), SI, SI *);
#endif /* CGEN_PAR_H */