ret i32 0
}
+; (X >>s C1) >>s C2 --> X >>s (C1 + C2)
+
+define i32 @ashr_ashr(i32 %x) {
+; CHECK-LABEL: @ashr_ashr(
+; CHECK-NEXT: [[SH2:%.*]] = ashr i32 %x, 12
+; CHECK-NEXT: ret i32 [[SH2]]
+;
+ %sh1 = ashr i32 %x, 5
+ %sh2 = ashr i32 %sh1, 7
+ ret i32 %sh2
+}
+
; PR3851
+; (X >>s C1) >>s C2 --> X >>s (Bitwidth - 1)
-define i32 @ashr_overshift(i32 %val) {
+define i32 @ashr_overshift(i32 %x) {
; CHECK-LABEL: @ashr_overshift(
-; CHECK-NEXT: [[SHR4:%.*]] = ashr i32 %val, 31
-; CHECK-NEXT: ret i32 [[SHR4]]
+; CHECK-NEXT: [[SH2:%.*]] = ashr i32 %x, 31
+; CHECK-NEXT: ret i32 [[SH2]]
+;
+ %sh1 = ashr i32 %x, 15
+ %sh2 = ashr i32 %sh1, 17
+ ret i32 %sh2
+}
+
+; FIXME:
+; (X >>s C1) >>s C2 --> X >>s (C1 + C2)
+
+define <2 x i32> @ashr_ashr_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @ashr_ashr_splat_vec(
+; CHECK-NEXT: [[SH1:%.*]] = ashr <2 x i32> %x, <i32 5, i32 5>
+; CHECK-NEXT: [[SH2:%.*]] = ashr <2 x i32> [[SH1]], <i32 7, i32 7>
+; CHECK-NEXT: ret <2 x i32> [[SH2]]
+;
+ %sh1 = ashr <2 x i32> %x, <i32 5, i32 5>
+ %sh2 = ashr <2 x i32> %sh1, <i32 7, i32 7>
+ ret <2 x i32> %sh2
+}
+
+; FIXME:
+; (X >>s C1) >>s C2 --> X >>s (Bitwidth - 1)
+
+define <2 x i32> @ashr_overshift_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @ashr_overshift_splat_vec(
+; CHECK-NEXT: [[SH1:%.*]] = ashr <2 x i32> %x, <i32 15, i32 15>
+; CHECK-NEXT: [[SH2:%.*]] = ashr <2 x i32> [[SH1]], <i32 17, i32 17>
+; CHECK-NEXT: ret <2 x i32> [[SH2]]
;
- %shr = ashr i32 %val, 15
- %shr4 = ashr i32 %shr, 17
- ret i32 %shr4
+ %sh1 = ashr <2 x i32> %x, <i32 15, i32 15>
+ %sh2 = ashr <2 x i32> %sh1, <i32 17, i32 17>
+ ret <2 x i32> %sh2
}