- ora zp,x/abs/abs,xy/indir,y supported.

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index 82b125e..a919c5e 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -1722,18 +1722,46 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#15#, dsize) then
                     --zp, x
                     d_print("ora");
+                    a2_zp_xy(true);
+                    if exec_cycle = T3 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        back_we(acc_cmd, '0');
+                        set_nz_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#0d#, dsize) then
                     --abs
                     d_print("ora");
+                    a2_abs;
+                    if exec_cycle = T3 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        back_we(acc_cmd, '0');
+                        set_nz_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#1d#, dsize) then
                     --abs, x
                     d_print("ora");
+                    a2_abs_xy(true);
+                    if exec_cycle = T3 or exec_cycle = T4 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        back_we(acc_cmd, '0');
+                        set_nz_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#19#, dsize) then
                     --abs, y
                     d_print("ora");
+                    a2_abs_xy(false);
+                    if exec_cycle = T3 or exec_cycle = T4 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        back_we(acc_cmd, '0');
+                        set_nz_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#01#, dsize) then
                     --(indir, x)
@@ -1742,6 +1770,13 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#11#, dsize) then
                     --(indir), y
                     d_print("ora");
+                    a2_indir_y;
+                    if exec_cycle = T4 or exec_cycle = T5 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        back_we(acc_cmd, '0');
+                        set_nz_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#e9#, dsize) then
                     --imm

diff --git a/tools/test-image/sample1.asm b/tools/test-image/sample1.asm
index 873c805..1d8070e 100644 (file)
--- a/tools/test-image/sample1.asm
+++ b/tools/test-image/sample1.asm
@@ -659,29 +659,29 @@ bl_test4:
     dex\r
     bpl bl_test3\r
 \r
-;    ;;ora zp, x/abs, x/indir, y\r
-;    lda #$de\r
-;    ldx #$e4\r
-;    sta $a4\r
-;    ;c5|de=df\r
-;    lda #$c5\r
-;    ora $c0, x\r
-;\r
-;    lda #$75\r
-;    stx $0734\r
-;    ;75|e4=f5\r
-;    cmp $0650, x\r
-;\r
-;    ldx #$c9\r
-;    stx $0825\r
-;    lda #$34\r
-;    sta $07\r
-;    lda #$07\r
-;    sta $08\r
-;    ldy #$f1\r
-;    ;page crossing\r
-;    ;07|c9=cf\r
-;    cmp ($07), y\r
+    ;;ora zp, x/abs, x/indir, y\r
+    lda #$de\r
+    ldx #$e4\r
+    sta $a4\r
+    ;c5|de=df\r
+    lda #$c5\r
+    ora $c0, x\r
+\r
+    lda #$75\r
+    stx $0734\r
+    ;75|e4=f5\r
+    ora $0650, x\r
+\r
+    ldx #$c9\r
+    stx $0825\r
+    lda #$34\r
+    sta $07\r
+    lda #$07\r
+    sta $08\r
+    ldy #$f1\r
+    ;page crossing\r
+    ;07|c9=cf\r
+    ora ($07), y\r
 \r
 \r
     ;;done...\r