Subzero. ARM32. Implements the Availability Optimization.

Implements the Availability optimization:

a = b
x = f(a, c)

becomes

a = b
x = f(b, c)

This only triggers if b is an infinite-weight temporary, and it
prevents a potential spill at the cost of higher register pressure.

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1424873003 .

diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index 7e67b71..282fde1 100644 (file)
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -3477,6 +3477,21 @@ Operand *TargetARM32::legalize(Operand *From, LegalMask Allowed,
   // legalize() allow a physical register. Legal_Flex converts registers to the
   // right type OperandARM32FlexReg as needed.
   assert(Allowed & Legal_Reg);
+
+  // Copied ipsis literis from TargetX86Base<Machine>.
+  if (RegNum == Variable::NoRegister) {
+    if (Variable *Subst = getContext().availabilityGet(From)) {
+      // At this point we know there is a potential substitution available.
+      if (Subst->mustHaveReg() && !Subst->hasReg()) {
+        // At this point we know the substitution will have a register.
+        if (From->getType() == Subst->getType()) {
+          // At this point we know the substitution's register is compatible.
+          return Subst;
+        }
+      }
+    }
+  }
+
   // Go through the various types of operands: OperandARM32Mem,
   // OperandARM32Flex, Constant, and Variable. Given the above assertion, if
   // type of operand is not legal (e.g., OperandARM32Mem and !Legal_Mem), we
@@ -3734,6 +3749,7 @@ void TargetARM32::postLower() {
   if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return;
   markRedefinitions();
+  Context.availabilityUpdate();
 }
 
 void TargetARM32::makeRandomRegisterPermutation(

diff --git a/tests_lit/llvm2ice_tests/callindirect.pnacl.ll b/tests_lit/llvm2ice_tests/callindirect.pnacl.ll
index 3f3dbaf..f69f6ee 100644 (file)
--- a/tests_lit/llvm2ice_tests/callindirect.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/callindirect.pnacl.ll
@@ -91,8 +91,8 @@ entry:
 ; OPTM1: call [[TARGET]]
 ;
 ; ARM32-LABEL: CallIndirectGlobal
-; ARM32: blx [[REGISTER:r.*]]
-; ARM32: blx [[REGISTER]]
+; ARM32: blx {{r.*}}
+; ARM32: blx [[REGISTER:r[0-9]*]]
 ; ARM32: blx [[REGISTER]]
 ; ARM32: blx [[REGISTER]]