multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
InstrItinClass itin_upd, bits<6> T1Enc,
- bit L_bit> {
+ bit L_bit, string baseOpc> {
def IA :
T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
let Inst{10-8} = Rn;
let Inst{7-0} = regs;
}
+
def IA_UPD :
- T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
- itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
- T1Encoding<T1Enc> {
- bits<3> Rn;
- bits<8> regs;
- let Inst{10-8} = Rn;
- let Inst{7-0} = regs;
+ InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
+ "$Rn = $wb", itin_upd>,
+ PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
+ GPR:$Rn, pred:$p, reglist:$regs)> {
+ let Size = 2;
+ let OutOperandList = (outs GPR:$wb);
+ let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
+ let Pattern = [];
+ let isCodeGenOnly = 1;
+ let isPseudo = 1;
+ list<Predicate> Predicates = [IsThumb];
}
}
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
- {1,1,0,0,1,?}, 1>;
+ {1,1,0,0,1,?}, 1, "tLDM">;
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
- {1,1,0,0,0,?}, 0>;
+ {1,1,0,0,0,?}, 0, "tSTM">;
} // neverHasSideEffects
static bool DisassembleThumb1LdStMul(bool Ld, MCInst &MI, unsigned Opcode,
uint32_t insn, unsigned short NumOps,
unsigned &NumOpsAdded, BO B) {
- assert((Opcode == ARM::tLDMIA || Opcode == ARM::tLDMIA_UPD ||
- Opcode == ARM::tSTMIA_UPD) && "Unexpected opcode");
+ assert((Opcode == ARM::tLDMIA || Opcode == ARM::tSTMIA) &&
+ "Unexpected opcode");
unsigned tRt = getT1tRt(insn);
NumOpsAdded = 0;
return;
}
+ if (Opcode == ARM::tLDMIA || Opcode == ARM::tSTMIA) {
+ bool Writeback = true;
+ unsigned BaseReg = MI->getOperand(0).getReg();
+ for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
+ if (MI->getOperand(i).getReg() == BaseReg)
+ Writeback = false;
+ }
+
+ if (Opcode == ARM::tLDMIA)
+ O << "\tldmia";
+ else if (Opcode == ARM::tSTMIA)
+ O << "\tstmia";
+ else
+ llvm_unreachable("Unknown opcode!");
+
+ printPredicateOperand(MI, 1, O);
+ O << '\t' << getRegisterName(BaseReg);
+ if (Writeback) O << "!";
+ O << ", ";
+ printRegisterList(MI, 3, O);
+ return;
+ }
+
printInstruction(MI, O);
}