*/
#include "cpureg.h"
+#include "membus.h"
#if defined(SUPPORT_32BIT_ADDRESS)
#include "../i386.h"
#else
void CPUREG::write_io8(uint32_t addr, uint32_t data)
{
+ //out_debug_log(_T("I/O WRITE: %04x %04x\n"), addr, data);
switch(addr) {
case 0x0050:
nmi_enabled = false;
uint32_t CPUREG::read_io8(uint32_t addr)
{
uint32_t value;
+ //out_debug_log(_T("I/O READ: %04x \n"), addr);
switch(addr) {
case 0x00f0:
// value |= 0x20; // Internal 27-type SASI-HDD, 0 = Existing
#endif
// value |= 0x10; // Unknown
- value |= 0x08; // RAM access, 1 = Internal-standard/External-enhanced RAM, 0 = Internal-enhanced RAM
+ value |= ((d_mem->read_signal(SIG_LAST_ACCESS_INTERAM) != 0) ? 0x00: 0x08); // RAM access, 1 = Internal-standard/External-enhanced RAM, 0 = Internal-enhanced RAM
// value |= 0x04; // Refresh mode, 1 = Standard, 0 = High speed
#if defined(HAS_I86) || defined(HAS_V30)
value |= 0x02; // CPU mode, 1 = V30, 0 = 80286/80386
memset(nec_ems, 0, sizeof(nec_ems));
#endif
#endif
+ last_access_is_interam = false;
}
void MEMBUS::reset()
uint32_t MEMBUS::read_data8(uint32_t addr)
{
if(addr < 0x80000) {
+ last_access_is_interam = false;
return MEMORY::read_data8(addr);
} else if(addr < 0xa0000) {
#if defined(SUPPORT_32BIT_ADDRESS)
if(is_shadow_bank_80000h) {
+ last_access_is_interam = true;
return (uint32_t)shadow_bank_i386_80000h[addr & 0x1ffff];
}
#endif
// ToDo: Correctness extra ram emulation.
if(!page08_intram_selected) {
+ last_access_is_interam = false;
return 0xff;
}
addr = (addr & 0x1ffff) | window_80000h;
} else if(addr < 0xc0000) {
#if defined(SUPPORT_32BIT_ADDRESS)
if(is_shadow_bank_a0000h) {
+ last_access_is_interam = true;
return (uint32_t)shadow_bank_i386_80000h[(addr & 0x1ffff) + 0x20000];
}
#endif
addr = (addr & 0x1ffff) | window_a0000h;
}
+ if(addr < 0x10000) {
+ last_access_is_interam = false;
+ } else {
+ last_access_is_interam = true;
+ }
if(addr < UPPER_MEMORY_24BIT) {
return MEMORY::read_data8(addr);
#if defined(SUPPORT_24BIT_ADDRESS)
void MEMBUS::write_data8(uint32_t addr, uint32_t data)
{
if(addr < 0x80000) {
+ last_access_is_interam = false;
MEMORY::write_data8(addr, data);
return;
} else if(addr < 0xa0000) {
#if defined(SUPPORT_32BIT_ADDRESS)
if(is_shadow_bank_80000h) {
+ last_access_is_interam = true;
shadow_bank_i386_80000h[addr & 0x1ffff] = data;
return;
}
#endif
// ToDo: Correctness extra ram emulation.
if(!page08_intram_selected) {
+ last_access_is_interam = false;
return;
}
addr = (addr & 0x1ffff) | window_80000h;
} else if(addr < 0xc0000) {
#if defined(SUPPORT_32BIT_ADDRESS)
if(is_shadow_bank_a0000h) {
+ last_access_is_interam = true;
shadow_bank_i386_80000h[(addr & 0x1ffff) + 0x20000] = data;
return;
}
#endif
addr = (addr & 0x1ffff) | window_a0000h;
}
+ if(addr < 0x10000) {
+ last_access_is_interam = false;
+ } else {
+ last_access_is_interam = true;
+ }
if(addr < UPPER_MEMORY_24BIT) {
MEMORY::write_data8(addr, data);
#if defined(SUPPORT_24BIT_ADDRESS)
}
#endif
+uint32_t MEMBUS::read_signal(int ch)
+{
+ switch(ch) {
+ case SIG_LAST_ACCESS_INTERAM:
+ return ((last_access_is_interam) ? 0xffffffff : 0x00000000);
+ break;
+ }
+ return 0;
+}
+
void MEMBUS::update_bios()
{
#if defined(SUPPORT_BIOS_RAM)
state_fio->StateArray(shadow_ram, sizeof(shadow_ram), 1);
#endif
#endif
+ state_fio->StateValue(last_access_is_interam);
if(!MEMORY::process_state(state_fio, loading)) {
return false;
}