[VM][PC9801][MEMBUS] Truely bootable MS-DOS 6.20,excepts EMM386.EXE.

diff --git a/source/src/vm/pc9801/cpureg.cpp b/source/src/vm/pc9801/cpureg.cpp
index 0b5ddec..769a4a8 100644 (file)
--- a/source/src/vm/pc9801/cpureg.cpp
+++ b/source/src/vm/pc9801/cpureg.cpp
@@ -12,6 +12,7 @@
 */
 
 #include "cpureg.h"
+#include "membus.h"
 #if defined(SUPPORT_32BIT_ADDRESS)
 #include "../i386.h"
 #else
@@ -28,6 +29,7 @@ void CPUREG::reset()
 
 void CPUREG::write_io8(uint32_t addr, uint32_t data)
 {
+       //out_debug_log(_T("I/O WRITE: %04x %04x\n"), addr, data);
        switch(addr) {
        case 0x0050:
                nmi_enabled = false;
@@ -67,6 +69,7 @@ void CPUREG::write_io8(uint32_t addr, uint32_t data)
 uint32_t CPUREG::read_io8(uint32_t addr)
 {
        uint32_t value;
+       //out_debug_log(_T("I/O READ: %04x \n"), addr);
        
        switch(addr) {
        case 0x00f0:
@@ -84,7 +87,7 @@ uint32_t CPUREG::read_io8(uint32_t addr)
 //             value |= 0x20; // Internal 27-type SASI-HDD, 0 = Existing
 #endif
 //             value |= 0x10; // Unknown
-               value |= 0x08; // RAM access, 1 = Internal-standard/External-enhanced RAM, 0 = Internal-enhanced RAM
+               value |= ((d_mem->read_signal(SIG_LAST_ACCESS_INTERAM) != 0) ? 0x00: 0x08); // RAM access, 1 = Internal-standard/External-enhanced RAM, 0 = Internal-enhanced RAM
 //             value |= 0x04; // Refresh mode, 1 = Standard, 0 = High speed
 #if defined(HAS_I86) || defined(HAS_V30)
                value |= 0x02; // CPU mode, 1 = V30, 0 = 80286/80386

diff --git a/source/src/vm/pc9801/membus.cpp b/source/src/vm/pc9801/membus.cpp
index b8e78c7..b4e11a0 100644 (file)
--- a/source/src/vm/pc9801/membus.cpp
+++ b/source/src/vm/pc9801/membus.cpp
@@ -185,6 +185,7 @@ void MEMBUS::initialize()
        memset(nec_ems, 0, sizeof(nec_ems));
 #endif
 #endif
+       last_access_is_interam = false;
 }
 
 void MEMBUS::reset()
@@ -496,26 +497,35 @@ uint32_t MEMBUS::read_io8(uint32_t addr)
 uint32_t MEMBUS::read_data8(uint32_t addr)
 {
        if(addr < 0x80000) {
+               last_access_is_interam = false;
                return MEMORY::read_data8(addr);
        } else if(addr < 0xa0000) {
 #if defined(SUPPORT_32BIT_ADDRESS)
                if(is_shadow_bank_80000h) {
+                       last_access_is_interam = true;
                        return (uint32_t)shadow_bank_i386_80000h[addr & 0x1ffff];
                }
 #endif
                // ToDo: Correctness extra ram emulation.
                if(!page08_intram_selected) {
+                       last_access_is_interam = false;
                        return 0xff;
                }
                addr = (addr & 0x1ffff) | window_80000h;
        } else if(addr < 0xc0000) {
 #if defined(SUPPORT_32BIT_ADDRESS)
                if(is_shadow_bank_a0000h) {
+                       last_access_is_interam = true;
                        return (uint32_t)shadow_bank_i386_80000h[(addr & 0x1ffff) + 0x20000];
                }
 #endif
                addr = (addr & 0x1ffff) | window_a0000h;
        }
+       if(addr < 0x10000) {
+               last_access_is_interam = false;
+       } else {
+               last_access_is_interam = true;
+       }
        if(addr < UPPER_MEMORY_24BIT) {
                return MEMORY::read_data8(addr);
 #if defined(SUPPORT_24BIT_ADDRESS)
@@ -531,29 +541,38 @@ uint32_t MEMBUS::read_data8(uint32_t addr)
 void MEMBUS::write_data8(uint32_t addr, uint32_t data)
 {
        if(addr < 0x80000) {
+               last_access_is_interam = false;
                MEMORY::write_data8(addr, data);
                return;
        } else if(addr < 0xa0000) {
 #if defined(SUPPORT_32BIT_ADDRESS)
                if(is_shadow_bank_80000h) {
+                       last_access_is_interam = true;
                        shadow_bank_i386_80000h[addr & 0x1ffff] = data;
                        return;
                }
 #endif
                // ToDo: Correctness extra ram emulation.
                if(!page08_intram_selected) {
+                       last_access_is_interam = false;
                        return;
                }
                addr = (addr & 0x1ffff) | window_80000h;
        } else if(addr < 0xc0000) {
 #if defined(SUPPORT_32BIT_ADDRESS)
                if(is_shadow_bank_a0000h) {
+                       last_access_is_interam = true;
                        shadow_bank_i386_80000h[(addr & 0x1ffff) + 0x20000] = data;
                        return;
                }
 #endif
                addr = (addr & 0x1ffff) | window_a0000h;
        }
+       if(addr < 0x10000) {
+               last_access_is_interam = false;
+       } else {
+               last_access_is_interam = true;
+       }
        if(addr < UPPER_MEMORY_24BIT) {
                MEMORY::write_data8(addr, data);
 #if defined(SUPPORT_24BIT_ADDRESS)
@@ -582,6 +601,16 @@ void MEMBUS::write_dma_data8(uint32_t addr, uint32_t data)
 }
 #endif
 
+uint32_t MEMBUS::read_signal(int ch)
+{
+       switch(ch) {
+       case SIG_LAST_ACCESS_INTERAM:
+               return ((last_access_is_interam) ? 0xffffffff : 0x00000000);
+               break;
+       }
+       return 0;
+}
+
 void MEMBUS::update_bios()
 {
 #if defined(SUPPORT_BIOS_RAM)
@@ -779,6 +808,7 @@ bool MEMBUS::process_state(FILEIO* state_fio, bool loading)
        state_fio->StateArray(shadow_ram, sizeof(shadow_ram), 1);
        #endif
  #endif
+       state_fio->StateValue(last_access_is_interam);
        if(!MEMORY::process_state(state_fio, loading)) {
                return false;
        }

diff --git a/source/src/vm/pc9801/membus.h b/source/src/vm/pc9801/membus.h
index 70fc4ca..314c630 100644 (file)
--- a/source/src/vm/pc9801/membus.h
+++ b/source/src/vm/pc9801/membus.h
@@ -35,6 +35,8 @@ namespace PC9801 {
 
 namespace PC9801 {
 
+#define SIG_LAST_ACCESS_INTERAM 1
+
 class MEMBUS : public MEMORY
 {
 private:
@@ -66,6 +68,7 @@ private:
 #if defined(SUPPORT_32BIT_ADDRESS)
        uint8_t shadow_ram[0x28000]; // 0xc0000 - 0xe8000
 #endif
+       bool last_access_is_interam;
        
 #endif
 #if defined(SUPPORT_ITF_ROM)
@@ -136,6 +139,7 @@ public:
        // common functions
        void initialize();
        void reset();
+       uint32_t read_signal(int ch);
        void write_io8(uint32_t addr, uint32_t data);
        uint32_t read_io8(uint32_t addr);
 #if defined(SUPPORT_24BIT_ADDRESS) || defined(SUPPORT_32BIT_ADDRESS)

diff --git a/source/src/vm/pc9801/pc9801.h b/source/src/vm/pc9801/pc9801.h
index cda368d..3059fb2 100644 (file)
--- a/source/src/vm/pc9801/pc9801.h
+++ b/source/src/vm/pc9801/pc9801.h
@@ -191,7 +191,7 @@
                #define SUPPORT_EGC
                #define HAS_UPD4990A
        #endif
-       #if !defined(SUPPORT_HIRESO)
+       #if !defined(SUPPORT_HIRESO) && !defined(SUPPORT_32BIT_ADDRESS)
                #define SUPPORT_NEC_EMS
        #endif
        #define SUPPORT_SASI_IF