net: phy: aquantia: check for supported interface modes in config_init

Let config_init check for unsupported interface modes on AQR107/AQCS109.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
[hkallweit1@gmail.com: adjusted for AQR107/AQCS109 specifics]
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/phy/aquantia_main.c b/drivers/net/phy/aquantia_main.c
index 37218e5..74c16b8 100644 (file)
--- a/drivers/net/phy/aquantia_main.c
+++ b/drivers/net/phy/aquantia_main.c
@@ -178,8 +178,24 @@ static int aqr_read_status(struct phy_device *phydev)
        return genphy_c45_read_status(phydev);
 }
 
+static int aqr107_config_init(struct phy_device *phydev)
+{
+       /* Check that the PHY interface type is compatible */
+       if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
+           phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
+           phydev->interface != PHY_INTERFACE_MODE_10GKR)
+               return -ENODEV;
+
+       return 0;
+}
+
 static int aqcs109_config_init(struct phy_device *phydev)
 {
+       /* Check that the PHY interface type is compatible */
+       if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
+           phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
+               return -ENODEV;
+
        /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
         * PMA speed ability bits are the same for all members of the family,
         * AQCS109 however supports speeds up to 2.5G only.
@@ -234,6 +250,7 @@ static struct phy_driver aqr_driver[] = {
        .aneg_done      = genphy_c45_aneg_done,
        .get_features   = genphy_c45_pma_read_abilities,
        .probe          = aqr_hwmon_probe,
+       .config_init    = aqr107_config_init,
        .config_aneg    = aqr_config_aneg,
        .config_intr    = aqr_config_intr,
        .ack_interrupt  = aqr_ack_interrupt,