// and isub_lo can be composed, which leads to all kinds of issues
// with lane masks.
def C8: Rc<8, "c8", [], [USR]>, DwarfRegNum<[75]>;
- def PC: Rc<9, "pc">, DwarfRegNum<[76]>;
+ def PC: Rc<9, "pc", ["c9"]>, DwarfRegNum<[76]>;
def UGP: Rc<10, "ugp", ["c10"]>, DwarfRegNum<[77]>;
def GP: Rc<11, "gp", ["c11"]>, DwarfRegNum<[78]>;
def CS0: Rc<12, "cs0", ["c12"]>, DwarfRegNum<[79]>;
void HexagonMCChecker::init() {
// Initialize read-only registers set.
ReadOnly.insert(Hexagon::PC);
+ ReadOnly.insert(Hexagon::C9_8);
// Figure out the loop-registers definitions.
if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
bool chkP = checkPredicates();
bool chkNV = checkNewValues();
bool chkR = checkRegisters();
+ bool chkRRO = checkRegistersReadOnly();
bool chkS = checkSolo();
bool chkSh = true;
if (FullCheck)
bool chkSl = true;
if (FullCheck)
chkSl = checkSlots();
- bool chk = chkB && chkP && chkNV && chkR && chkS && chkSh && chkSl;
+ bool chk = chkB && chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl;
return chk;
}
return true;
}
+bool HexagonMCChecker::checkRegistersReadOnly() {
+ for (auto I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
+ MCInst const &Inst = *I.getInst();
+ unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs();
+ for (unsigned j = 0; j < Defs; ++j) {
+ MCOperand const &Operand = Inst.getOperand(j);
+ assert(Operand.isReg() && "Def is not a register");
+ unsigned Register = Operand.getReg();
+ if (ReadOnly.find(Register) != ReadOnly.end()) {
+ reportError(Inst.getLoc(), "Cannot write to read-only register `" +
+ llvm::Twine(RI.getName(Register)) + "'");
+ return false;
+ }
+ }
+ }
+ return true;
+}
+
// Check for legal register uses and definitions.
bool HexagonMCChecker::checkRegisters() {
// Check for proper register definitions.
for (const auto &I : Defs) {
unsigned R = I.first;
- if (ReadOnly.count(R)) {
- // Error out for definitions of read-only registers.
- reportError("cannot write to read-only register `" +
- llvm::Twine(RI.getName(R)) + "'");
- return false;
- }
if (isLoopRegister(R) && Defs.count(R) > 1 &&
(HexagonMCInstrInfo::isInnerLoop(MCB) ||
HexagonMCInstrInfo::isOuterLoop(MCB))) {