net: sparx5: Implement SIOCSHWTSTAMP and SIOCGHWTSTAMP

Implement the ioctl callbacks SIOCSHWTSTAMP and SIOCGHWTSTAMP to allow
to configure the ports to enable/disable timestamping for TX. The RX
timestamping is always enabled. The HW is capable to run both 1-step
timestamping and 2-step timestamping.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
index cf68b3f..8f3c7a9 100644 (file)
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
@@ -84,6 +84,10 @@ enum sparx5_vlan_port_type {
 #define SPARX5_PHC_COUNT               3
 #define SPARX5_PHC_PORT                        0
 
+#define IFH_REW_OP_NOOP                        0x0
+#define IFH_REW_OP_ONE_STEP_PTP                0x3
+#define IFH_REW_OP_TWO_STEP_PTP                0x4
+
 struct sparx5;
 
 struct sparx5_db_hw {
@@ -174,6 +178,8 @@ struct sparx5_port {
        u32 custom_etype;
        bool vlan_aware;
        struct hrtimer inj_timer;
+       /* ptp */
+       u8 ptp_cmd;
 };
 
 enum sparx5_core_clockfreq {
@@ -242,6 +248,7 @@ struct sparx5 {
        bool ptp;
        struct sparx5_phc phc[SPARX5_PHC_COUNT];
        spinlock_t ptp_clock_lock; /* lock for phc */
+       struct mutex ptp_lock; /* lock for ptp interface state */
 };
 
 /* sparx5_switchdev.c */
@@ -314,6 +321,8 @@ void sparx5_unregister_netdevs(struct sparx5 *sparx5);
 /* sparx5_ptp.c */
 int sparx5_ptp_init(struct sparx5 *sparx5);
 void sparx5_ptp_deinit(struct sparx5 *sparx5);
+int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, struct ifreq *ifr);
+int sparx5_ptp_hwtstamp_get(struct sparx5_port *port, struct ifreq *ifr);
 
 /* Clock period in picoseconds */
 static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock)

diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
index 86cae8b..5fd0b2e 100644 (file)
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
@@ -179,6 +179,24 @@ static int sparx5_get_port_parent_id(struct net_device *dev,
        return 0;
 }
 
+static int sparx5_port_ioctl(struct net_device *dev, struct ifreq *ifr,
+                            int cmd)
+{
+       struct sparx5_port *sparx5_port = netdev_priv(dev);
+       struct sparx5 *sparx5 = sparx5_port->sparx5;
+
+       if (!phy_has_hwtstamp(dev->phydev) && sparx5->ptp) {
+               switch (cmd) {
+               case SIOCSHWTSTAMP:
+                       return sparx5_ptp_hwtstamp_set(sparx5_port, ifr);
+               case SIOCGHWTSTAMP:
+                       return sparx5_ptp_hwtstamp_get(sparx5_port, ifr);
+               }
+       }
+
+       return phy_mii_ioctl(dev->phydev, ifr, cmd);
+}
+
 static const struct net_device_ops sparx5_port_netdev_ops = {
        .ndo_open               = sparx5_port_open,
        .ndo_stop               = sparx5_port_stop,
@@ -189,6 +207,7 @@ static const struct net_device_ops sparx5_port_netdev_ops = {
        .ndo_validate_addr      = eth_validate_addr,
        .ndo_get_stats64        = sparx5_get_stats64,
        .ndo_get_port_parent_id = sparx5_get_port_parent_id,
+       .ndo_eth_ioctl          = sparx5_port_ioctl,
 };
 
 bool sparx5_netdevice_check(const struct net_device *dev)

diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c
index 0203d87..0d919e2 100644 (file)
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c
@@ -74,6 +74,79 @@ static u64 sparx5_ptp_get_nominal_value(struct sparx5 *sparx5)
        return res;
 }
 
+int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, struct ifreq *ifr)
+{
+       struct sparx5 *sparx5 = port->sparx5;
+       struct hwtstamp_config cfg;
+       struct sparx5_phc *phc;
+
+       /* For now don't allow to run ptp on ports that are part of a bridge,
+        * because in case of transparent clock the HW will still forward the
+        * frames, so there would be duplicate frames
+        */
+
+       if (test_bit(port->portno, sparx5->bridge_mask))
+               return -EINVAL;
+
+       if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
+               return -EFAULT;
+
+       switch (cfg.tx_type) {
+       case HWTSTAMP_TX_ON:
+               port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
+               break;
+       case HWTSTAMP_TX_ONESTEP_SYNC:
+               port->ptp_cmd = IFH_REW_OP_ONE_STEP_PTP;
+               break;
+       case HWTSTAMP_TX_OFF:
+               port->ptp_cmd = IFH_REW_OP_NOOP;
+               break;
+       default:
+               return -ERANGE;
+       }
+
+       switch (cfg.rx_filter) {
+       case HWTSTAMP_FILTER_NONE:
+               break;
+       case HWTSTAMP_FILTER_ALL:
+       case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
+       case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
+       case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
+       case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
+       case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
+       case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
+       case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
+       case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
+       case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
+       case HWTSTAMP_FILTER_PTP_V2_EVENT:
+       case HWTSTAMP_FILTER_PTP_V2_SYNC:
+       case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
+       case HWTSTAMP_FILTER_NTP_ALL:
+               cfg.rx_filter = HWTSTAMP_FILTER_ALL;
+               break;
+       default:
+               return -ERANGE;
+       }
+
+       /* Commit back the result & save it */
+       mutex_lock(&sparx5->ptp_lock);
+       phc = &sparx5->phc[SPARX5_PHC_PORT];
+       memcpy(&phc->hwtstamp_config, &cfg, sizeof(cfg));
+       mutex_unlock(&sparx5->ptp_lock);
+
+       return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
+}
+
+int sparx5_ptp_hwtstamp_get(struct sparx5_port *port, struct ifreq *ifr)
+{
+       struct sparx5 *sparx5 = port->sparx5;
+       struct sparx5_phc *phc;
+
+       phc = &sparx5->phc[SPARX5_PHC_PORT];
+       return copy_to_user(ifr->ifr_data, &phc->hwtstamp_config,
+                           sizeof(phc->hwtstamp_config)) ? -EFAULT : 0;
+}
+
 static int sparx5_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
 {
        struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info);
@@ -291,6 +364,7 @@ int sparx5_ptp_init(struct sparx5 *sparx5)
        }
 
        spin_lock_init(&sparx5->ptp_clock_lock);
+       mutex_init(&sparx5->ptp_lock);
 
        /* Disable master counters */
        spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0), sparx5, PTP_PTP_DOM_CFG);