* - src1 is the destination register when write commit occurs.
*/
GS_OPCODE_SVB_WRITE,
+
+ /**
+ * Set destination index in the SVB write message payload (M0.5). Used
+ * in gen6 for transform feedback.
+ *
+ * - dst is the header to save the destination indices for SVB WRITE.
+ * - src is the register that holds the destination indices value.
+ */
+ GS_OPCODE_SVB_SET_DST_INDEX,
};
enum brw_derivative_quality {
return "set_primitive_id";
case GS_OPCODE_SVB_WRITE:
return "gs_svb_write";
+ case GS_OPCODE_SVB_SET_DST_INDEX:
+ return "gs_svb_set_dst_index";
default:
/* Yes, this leaks. It's in debug code, it should never occur, and if
unsigned sol_binding; /**< gen6: SOL binding table index */
bool sol_final_write; /**< gen6: send commit message */
+ unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
bool is_send_from_grf();
bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
struct brw_reg dst,
struct brw_reg src0,
struct brw_reg src1);
+ void generate_gs_svb_set_destination_index(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src);
void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
void generate_gs_prepare_channel_masks(struct brw_reg dst);
void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
}
void
+vec4_generator::generate_gs_svb_set_destination_index(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src)
+{
+
+ int vertex = inst->sol_vertex;
+ brw_push_insn_state(p);
+ brw_set_default_access_mode(p, BRW_ALIGN_1);
+ brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+ brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
+ brw_pop_insn_state(p);
+}
+
+void
vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src)
{
brw_push_insn_state(p);
generate_gs_svb_write(inst, dst, src[0], src[1]);
break;
+ case GS_OPCODE_SVB_SET_DST_INDEX:
+ generate_gs_svb_set_destination_index(inst, dst, src[0]);
+ break;
+
case GS_OPCODE_THREAD_END:
generate_gs_thread_end(inst);
break;