drm/i915: Stop getting the fault address from RING_FAULT_REG

This register does not contain it. Instead, we have to look into FAULT_TLB_DATA0 & 1
(where, by the way, we can also get the address space).

v2: Right formatting
v3:
  - Use 12 (as per the register format) instead of PAGE_SIZE (Chris)
  - s/BITS_44_TO_47/HIGHBITS (Chris)
  - Right formatting, this time for real

Fixes: b03ec3d67ab8 ("drm/i915: There is only one fault register from GEN8 onwards")
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1513982329-32191-1-git-send-email-oscar.mateo@intel.com
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f2a0f55..26dee5e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2287,12 +2287,23 @@ static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
        u32 fault = I915_READ(GEN8_RING_FAULT_REG);
 
        if (fault & RING_FAULT_VALID) {
+               u32 fault_data0, fault_data1;
+               u64 fault_addr;
+
+               fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
+               fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
+               fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
+                            ((u64)fault_data0 << 12);
+
                DRM_DEBUG_DRIVER("Unexpected fault\n"
-                                "\tAddr: 0x%08lx\n"
+                                "\tAddr: 0x%08x_%08x\n"
+                                "\tAddress space: %s\n"
                                 "\tEngine ID: %d\n"
                                 "\tSource ID: %d\n"
                                 "\tType: %d\n",
-                                fault & PAGE_MASK,
+                                upper_32_bits(fault_addr),
+                                lower_32_bits(fault_addr),
+                                fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
                                 GEN8_RING_FAULT_ENGINE_ID(fault),
                                 RING_FAULT_SRCID(fault),
                                 RING_FAULT_FAULT_TYPE(fault));

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 505c605..a2108e3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2489,6 +2489,8 @@ enum i915_power_well_id {
 
 #define GEN8_FAULT_TLB_DATA0           _MMIO(0x4b10)
 #define GEN8_FAULT_TLB_DATA1           _MMIO(0x4b14)
+#define   FAULT_VA_HIGH_BITS           (0xf << 0)
+#define   FAULT_GTT_SEL                        (1 << 4)
 
 #define FPGA_DBG               _MMIO(0x42300)
 #define   FPGA_DBG_RM_NOCLAIM  (1<<31)