/* Boards following the design guidelines in the developer's manual,
* with on-chip GPIOs not Lubbock's weird hardware, can have a sane
* VBUS IRQ and omit the methods above. Store the GPIO number
- * here; for GPIO 0, also mask in one of the pxa_gpio_mode() bits.
- * Note that sometimes the signals go through inverters...
+ * here. Note that sometimes the signals go through inverters...
*/
bool gpio_vbus_inverted;
u16 gpio_vbus; /* high == vbus present */
extern struct platform_device pxa27x_device_pwm1;
extern struct platform_device pxa3xx_device_nand;
+extern struct platform_device pxa3xx_device_i2c_power;
void __init pxa_register_device(struct platform_device *dev, void *data);
*/
unsigned int get_clk_frequency_khz(int info)
{
- if (cpu_is_pxa21x() || cpu_is_pxa25x())
+ if (cpu_is_pxa25x())
return pxa25x_get_clk_frequency_khz(info);
else if (cpu_is_pxa27x())
return pxa27x_get_clk_frequency_khz(info);
*/
unsigned int get_memclk_frequency_10khz(void)
{
- if (cpu_is_pxa21x() || cpu_is_pxa25x())
+ if (cpu_is_pxa25x())
return pxa25x_get_memclk_frequency_10khz();
else if (cpu_is_pxa27x())
return pxa27x_get_memclk_frequency_10khz();
#ifndef __ASSEMBLY__
+/*
+ * CPU Stepping CPU_ID JTAG_ID
+ *
+ * PXA210 B0 0x69052922 0x2926C013
+ * PXA210 B1 0x69052923 0x3926C013
+ * PXA210 B2 0x69052924 0x4926C013
+ * PXA210 C0 0x69052D25 0x5926C013
+ *
+ * PXA250 A0 0x69052100 0x09264013
+ * PXA250 A1 0x69052101 0x19264013
+ * PXA250 B0 0x69052902 0x29264013
+ * PXA250 B1 0x69052903 0x39264013
+ * PXA250 B2 0x69052904 0x49264013
+ * PXA250 C0 0x69052D05 0x59264013
+ *
+ * PXA255 A0 0x69052D06 0x69264013
+ *
+ * PXA26x A0 0x69052903 0x39264013
+ * PXA26x B0 0x69052D05 0x59264013
+ *
+ * PXA27x A0 0x69054110 0x09265013
+ * PXA27x A1 0x69054111 0x19265013
+ * PXA27x B0 0x69054112 0x29265013
+ * PXA27x B1 0x69054113 0x39265013
+ * PXA27x C0 0x69054114 0x49265013
+ * PXA27x C5 0x69054117 0x79265013
+ *
+ * PXA30x A0 0x69056880 0x0E648013
+ * PXA30x A1 0x69056881 0x1E648013
+ * PXA31x A0 0x69056890 0x0E649013
+ * PXA31x A1 0x69056891 0x1E649013
+ * PXA31x A2 0x69056892 0x2E649013
+ * PXA32x B1 0x69056825 0x5E642013
+ * PXA32x B2 0x69056826 0x6E642013
+ *
+ * PXA930 B0 0x69056835 0x5E643013
+ * PXA930 B1 0x69056837 0x7E643013
+ * PXA930 B2 0x69056838 0x8E643013
+ */
#ifdef CONFIG_PXA25x
-#define __cpu_is_pxa21x(id) \
+#define __cpu_is_pxa210(id) \
({ \
- unsigned int _id = (id) >> 4 & 0xf3f; \
- _id == 0x212; \
+ unsigned int _id = (id) & 0xf3f0; \
+ _id == 0x2120; \
})
-#define __cpu_is_pxa255(id) \
- ({ \
- unsigned int _id = (id) >> 4 & 0xfff; \
- _id == 0x2d0; \
- })
+#define __cpu_is_pxa250(id) \
+ ({ \
+ unsigned int _id = (id) & 0xf3ff; \
+ _id <= 0x2105; \
+ })
+
+#define __cpu_is_pxa255(id) \
+ ({ \
+ unsigned int _id = (id) & 0xffff; \
+ _id == 0x2d06; \
+ })
#define __cpu_is_pxa25x(id) \
({ \
- unsigned int _id = (id) >> 4 & 0xfff; \
- _id == 0x2d0 || _id == 0x290; \
+ unsigned int _id = (id) & 0xf300; \
+ _id == 0x2100; \
})
#else
-#define __cpu_is_pxa21x(id) (0)
+#define __cpu_is_pxa210(id) (0)
+#define __cpu_is_pxa250(id) (0)
#define __cpu_is_pxa255(id) (0)
#define __cpu_is_pxa25x(id) (0)
#endif
#define __cpu_is_pxa930(id) (0)
#endif
-#define cpu_is_pxa21x() \
+#define cpu_is_pxa210() \
({ \
- __cpu_is_pxa21x(read_cpuid_id()); \
+ __cpu_is_pxa210(read_cpuid_id()); \
+ })
+
+#define cpu_is_pxa250() \
+ ({ \
+ __cpu_is_pxa250(read_cpuid_id()); \
})
#define cpu_is_pxa255() \
__cpu_is_pxa25x(read_cpuid_id()); \
})
+extern int cpu_is_pxa26x(void);
+
#define cpu_is_pxa27x() \
({ \
__cpu_is_pxa27x(read_cpuid_id()); \
unsigned int slave_addr;
struct i2c_slave_client *slave;
unsigned int class;
- int use_pio;
+ unsigned int use_pio :1;
+ unsigned int fast_mode :1;
};
extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
#ifdef CONFIG_PXA27x
-extern void pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info);
+extern void pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info);
+#endif
+
+#ifdef CONFIG_PXA3xx
+extern void pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info);
#endif
#endif
void (*restore)(unsigned long *);
int (*valid)(suspend_state_t state);
void (*enter)(suspend_state_t state);
+ int (*prepare)(void);
+ void (*finish)(void);
};
extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
#define ICR_SADIE (1 << 13) /* slave address detected int enable */
#define ICR_UR (1 << 14) /* unit reset */
+#define ICR_FM (1 << 15) /* fast mode */
#define ISR_RWM (1 << 0) /* read/write mode */
#define ISR_ACKNAK (1 << 1) /* ack/nak status */
#define __ASM_ARCH_SSP_H
#include <linux/list.h>
+#include <linux/io.h>
enum pxa_ssp_type {
SSP_UNDEFINED = 0,
int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
void ssp_exit(struct ssp_dev *dev);
+/**
+ * ssp_write_reg - Write to a SSP register
+ *
+ * @dev: SSP device to access
+ * @reg: Register to write to
+ * @val: Value to be written.
+ */
+static inline void ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
+{
+ __raw_writel(val, dev->mmio_base + reg);
+}
+
+/**
+ * ssp_read_reg - Read from a SSP register
+ *
+ * @dev: SSP device to access
+ * @reg: Register to read from
+ */
+static inline u32 ssp_read_reg(struct ssp_device *dev, u32 reg)
+{
+ return __raw_readl(dev->mmio_base + reg);
+}
+
struct ssp_device *ssp_request(int port, const char *label);
void ssp_free(struct ssp_device *);
#endif /* __ASM_ARCH_SSP_H */
return -EINVAL;
}
+static int pxa_pm_prepare(void)
+{
+ int ret = 0;
+
+ if (pxa_cpu_pm_fns && pxa_cpu_pm_fns->prepare)
+ ret = pxa_cpu_pm_fns->prepare();
+
+ return ret;
+}
+
+static void pxa_pm_finish(void)
+{
+ if (pxa_cpu_pm_fns && pxa_cpu_pm_fns->finish)
+ pxa_cpu_pm_fns->finish();
+}
+
static struct platform_suspend_ops pxa_pm_ops = {
.valid = pxa_pm_valid,
.enter = pxa_pm_enter,
+ .prepare = pxa_pm_prepare,
+ .finish = pxa_pm_finish,
};
static int __init pxa_pm_init(void)
#include "devices.h"
#include "clock.h"
+int cpu_is_pxa26x(void)
+{
+ return cpu_is_pxa250() && ((BOOT_DEF & 0x8) == 0);
+}
+EXPORT_SYMBOL_GPL(cpu_is_pxa26x);
+
/*
* Various clock factors driven by the CCCR register.
*/
static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
{
- /* ensure not to come back here if it wasn't intended */
- PSPR = 0;
-
RESTORE(CKEN);
RESTORE(PSTR);
}
switch (state) {
case PM_SUSPEND_MEM:
- /* set resume return address */
- PSPR = virt_to_phys(pxa_cpu_resume);
pxa25x_cpu_suspend(PWRMODE_SLEEP);
break;
}
}
+static int pxa25x_cpu_pm_prepare(void)
+{
+ /* set resume return address */
+ PSPR = virt_to_phys(pxa_cpu_resume);
+ return 0;
+}
+
+static void pxa25x_cpu_pm_finish(void)
+{
+ /* ensure not to come back here if it wasn't intended */
+ PSPR = 0;
+}
+
static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
.save_count = SLEEP_SAVE_COUNT,
.valid = suspend_valid_only_mem,
.save = pxa25x_cpu_pm_save,
.restore = pxa25x_cpu_pm_restore,
.enter = pxa25x_cpu_pm_enter,
+ .prepare = pxa25x_cpu_pm_prepare,
+ .finish = pxa25x_cpu_pm_finish,
};
static void __init pxa25x_init_pm(void)
{
int i, ret = 0;
- /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
- if (cpu_is_pxa255())
- clks_register(&pxa25x_hwuart_clk, 1);
-
- if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
+ if (cpu_is_pxa25x()) {
reset_status = RCSR;
return ret;
}
- /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
- if (cpu_is_pxa255())
+ /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
+ if (cpu_is_pxa255() || cpu_is_pxa26x()) {
+ clks_register(&pxa25x_hwuart_clk, 1);
ret = platform_device_register(&pxa_device_hwuart);
+ }
return ret;
}
void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
{
- /* ensure not to come back here if it wasn't intended */
- PSPR = 0;
-
RESTORE(MDREFR);
RESTORE(PCFR);
pxa_cpu_standby();
break;
case PM_SUSPEND_MEM:
- /* set resume return address */
- PSPR = virt_to_phys(pxa_cpu_resume);
pxa27x_cpu_suspend(PWRMODE_SLEEP);
break;
}
return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}
+static int pxa27x_cpu_pm_prepare(void)
+{
+ /* set resume return address */
+ PSPR = virt_to_phys(pxa_cpu_resume);
+ return 0;
+}
+
+static void pxa27x_cpu_pm_finish(void)
+{
+ /* ensure not to come back here if it wasn't intended */
+ PSPR = 0;
+}
+
static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
.save_count = SLEEP_SAVE_COUNT,
.save = pxa27x_cpu_pm_save,
.restore = pxa27x_cpu_pm_restore,
.valid = pxa27x_cpu_pm_valid,
.enter = pxa27x_cpu_pm_enter,
+ .prepare = pxa27x_cpu_pm_prepare,
+ .finish = pxa27x_cpu_pm_finish,
};
static void __init pxa27x_init_pm(void)
.num_resources = ARRAY_SIZE(i2c_power_resources),
};
-void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
+void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
local_irq_disable();
PCFR |= PCFR_PI2CEN;
.disable = clk_pout_disable,
};
+static void clk_dummy_enable(struct clk *clk)
+{
+}
+
+static void clk_dummy_disable(struct clk *clk)
+{
+}
+
+static const struct clkops clk_dummy_ops = {
+ .enable = clk_dummy_enable,
+ .disable = clk_dummy_disable,
+};
+
static struct clk pxa3xx_clks[] = {
{
.name = "CLK_POUT",
.delay = 70,
},
+ /* Power I2C clock is always on */
+ {
+ .name = "I2CCLK",
+ .ops = &clk_dummy_ops,
+ .dev = &pxa3xx_device_i2c_power.dev,
+ },
+
PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL),
* device registration specific to PXA3xx.
*/
+static struct resource i2c_power_resources[] = {
+ {
+ .start = 0x40f500c0,
+ .end = 0x40f500d3,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_PWRI2C,
+ .end = IRQ_PWRI2C,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device pxa3xx_device_i2c_power = {
+ .name = "pxa2xx-i2c",
+ .id = 1,
+ .resource = i2c_power_resources,
+ .num_resources = ARRAY_SIZE(i2c_power_resources),
+};
+
+void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
+{
+ pxa3xx_device_i2c_power.dev.platform_data = info;
+}
+
static struct platform_device *devices[] __initdata = {
/* &pxa_device_udc, The UDC driver is PXA25x only */
&pxa_device_ffuart,
&pxa3xx_device_ssp4,
&pxa27x_device_pwm0,
&pxa27x_device_pwm1,
+ &pxa3xx_device_i2c_power,
};
static struct sys_device pxa3xx_sysdev[] = {
OIER = 0;
OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
- if (cpu_is_pxa21x() || cpu_is_pxa25x())
+ if (cpu_is_pxa25x())
clock_tick_rate = 3686400;
else if (machine_is_mainstone())
clock_tick_rate = 3249600;
u32 icrlog[32];
void __iomem *reg_base;
+ unsigned int reg_shift;
unsigned long iobase;
unsigned long iosize;
int irq;
- int use_pio;
+ unsigned int use_pio :1;
+ unsigned int fast_mode :1;
};
-#define _IBMR(i2c) ((i2c)->reg_base + 0)
-#define _IDBR(i2c) ((i2c)->reg_base + 8)
-#define _ICR(i2c) ((i2c)->reg_base + 0x10)
-#define _ISR(i2c) ((i2c)->reg_base + 0x18)
-#define _ISAR(i2c) ((i2c)->reg_base + 0x20)
+#define _IBMR(i2c) ((i2c)->reg_base + (0x0 << (i2c)->reg_shift))
+#define _IDBR(i2c) ((i2c)->reg_base + (0x4 << (i2c)->reg_shift))
+#define _ICR(i2c) ((i2c)->reg_base + (0x8 << (i2c)->reg_shift))
+#define _ISR(i2c) ((i2c)->reg_base + (0xc << (i2c)->reg_shift))
+#define _ISAR(i2c) ((i2c)->reg_base + (0x10 << (i2c)->reg_shift))
/*
* I2C Slave mode address
static void i2c_pxa_abort(struct pxa_i2c *i2c)
{
- unsigned long timeout = jiffies + HZ/4;
+ int i = 250;
if (i2c_pxa_is_slavemode(i2c)) {
dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
return;
}
- while (time_before(jiffies, timeout) && (readl(_IBMR(i2c)) & 0x1) == 0) {
+ while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
unsigned long icr = readl(_ICR(i2c));
icr &= ~ICR_START;
show_state(i2c);
- msleep(1);
+ mdelay(1);
+ i --;
}
writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
writel(i2c->slave_addr, _ISAR(i2c));
/* set control register values */
- writel(I2C_ICR_INIT, _ICR(i2c));
+ writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
#ifdef CONFIG_I2C_PXA_SLAVE
dev_info(&i2c->adap.dev, "Enabling slave mode\n");
struct pxa_i2c *i2c = adap->algo_data;
int ret, i;
- /* If the I2C controller is disabled we need to reset it (probably due
- to a suspend/resume destroying state). We do this here as we can then
- avoid worrying about resuming the controller before its users. */
- if (!(readl(_ICR(i2c)) & ICR_IUE))
- i2c_pxa_reset(i2c);
-
for (i = adap->retries; i >= 0; i--) {
ret = i2c_pxa_do_xfer(i2c, msgs, num);
if (ret != I2C_RETRY)
ret = -EIO;
goto eremap;
}
+ i2c->reg_shift = (cpu_is_pxa3xx() && (dev->id == 1)) ? 0 : 1;
i2c->iobase = res->start;
i2c->iosize = res_len(res);
if (plat) {
i2c->adap.class = plat->class;
i2c->use_pio = plat->use_pio;
+ i2c->fast_mode = plat->fast_mode;
}
if (i2c->use_pio) {
return 0;
}
+#ifdef CONFIG_PM
+static int i2c_pxa_suspend_late(struct platform_device *dev, pm_message_t state)
+{
+ struct pxa_i2c *i2c = platform_get_drvdata(dev);
+ clk_disable(i2c->clk);
+ return 0;
+}
+
+static int i2c_pxa_resume_early(struct platform_device *dev)
+{
+ struct pxa_i2c *i2c = platform_get_drvdata(dev);
+
+ clk_enable(i2c->clk);
+ i2c_pxa_reset(i2c);
+
+ return 0;
+}
+#else
+#define i2c_pxa_suspend_late NULL
+#define i2c_pxa_resume_early NULL
+#endif
+
static struct platform_driver i2c_pxa_driver = {
.probe = i2c_pxa_probe,
.remove = __exit_p(i2c_pxa_remove),
+ .suspend_late = i2c_pxa_suspend_late,
+ .resume_early = i2c_pxa_resume_early,
.driver = {
.name = "pxa2xx-i2c",
.owner = THIS_MODULE,
#define KB_ACTIVATE_DELAY 10
/* Helper functions for reading the keyboard matrix
- * Note: We should really be using pxa_gpio_mode to alter GPDR but it
- * requires a function call per GPIO bit which is excessive
- * when we need to access 12 bits at once multiple times.
+ * Note: We should really be using the generic gpio functions to alter
+ * GPDR but it requires a function call per GPIO bit which is
+ * excessive when we need to access 12 bits at once, multiple times.
* These functions must be called within local_irq_save()/local_irq_restore()
* or similar.
*/
#define KB_ACTIVATE_DELAY 10
/* Helper functions for reading the keyboard matrix
- * Note: We should really be using pxa_gpio_mode to alter GPDR but it
- * requires a function call per GPIO bit which is excessive
- * when we need to access 11 bits at once, multiple times.
+ * Note: We should really be using the generic gpio functions to alter
+ * GPDR but it requires a function call per GPIO bit which is
+ * excessive when we need to access 11 bits at once, multiple times.
* These functions must be called within local_irq_save()/local_irq_restore()
* or similar.
*/
/* Helper functions for reading the keyboard matrix
- * Note: We should really be using pxa_gpio_mode to alter GPDR but it
- * requires a function call per GPIO bit which is excessive
- * when we need to access 12 bits at once, multiple times.
+ * Note: We should really be using the generic gpio functions to alter
+ * GPDR but it requires a function call per GPIO bit which is
+ * excessive when we need to access 12 bits at once, multiple times.
* These functions must be called within local_irq_save()/local_irq_restore()
* or similar.
*/
/*
* Block length register is only 10 bits before PXA27x.
*/
- mmc->max_blk_size = (cpu_is_pxa21x() || cpu_is_pxa25x()) ? 1023 : 2048;
+ mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048;
/*
* Block count register is 16 bits.
MMC_VDD_32_33|MMC_VDD_33_34;
mmc->caps = 0;
host->cmdat = 0;
- if (!cpu_is_pxa21x() && !cpu_is_pxa25x()) {
+ if (!cpu_is_pxa25x()) {
mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
host->cmdat |= CMDAT_SDIO_INT_EN;
if (cpu_is_pxa300() || cpu_is_pxa310())
serial_out(up, UART_IER, up->ier);
+ if (termios->c_cflag & CRTSCTS)
+ up->mcr |= UART_MCR_AFE;
+ else
+ up->mcr &= ~UART_MCR_AFE;
+
serial_out(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
static int pxa2xx_ac97_resume(struct platform_device *pdev,
struct snd_soc_dai *dai)
{
- pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
- pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
- pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
- pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
-#ifdef CONFIG_PXA27x
- /* Use GPIO 113 as AC97 Reset on Bulverde */
- pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
-#endif
clk_enable(ac97_clk);
return 0;
}
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