net: hns3: Add STRP_TAGP field support for hardware revision 0x21

Hardware Revision(0x21) Buffer Descriptor adds a field STRP_TAGP
for vlan stripped processed indication. STRP_TAGP field has 2 bits,
bit 0 is stripped indication of the vlan tag in outer vlan tag
field, bit 1 is stripped indication of the vlan tag in inner vlan
tag field. For each bit, 0 indicates the tag is not stripped and
1 indicates the tag is stripped.

This patch adds STRP_TAGP support for revision(0x21), and does not
change the revision(0x20) action.

Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
index ae8d749..1bcb676 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
@@ -2066,6 +2066,39 @@ static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
        napi_gro_receive(&ring->tqp_vector->napi, skb);
 }
 
+static u16 hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
+                              struct hns3_desc *desc, u32 l234info)
+{
+       struct pci_dev *pdev = ring->tqp->handle->pdev;
+       u16 vlan_tag;
+
+       if (pdev->revision == 0x20) {
+               vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
+               if (!(vlan_tag & VLAN_VID_MASK))
+                       vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
+
+               return vlan_tag;
+       }
+
+#define HNS3_STRP_OUTER_VLAN   0x1
+#define HNS3_STRP_INNER_VLAN   0x2
+
+       switch (hnae_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
+                              HNS3_RXD_STRP_TAGP_S)) {
+       case HNS3_STRP_OUTER_VLAN:
+               vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
+               break;
+       case HNS3_STRP_INNER_VLAN:
+               vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
+               break;
+       default:
+               vlan_tag = 0;
+               break;
+       }
+
+       return vlan_tag;
+}
+
 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
                             struct sk_buff **out_skb, int *out_bnum)
 {
@@ -2155,6 +2188,9 @@ static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
        }
 
        *out_bnum = bnum;
+
+       l234info = le32_to_cpu(desc->rx.l234_info);
+
        /* Based on hw strategy, the tag offloaded will be stored at
         * ot_vlan_tag in two layer tag case, and stored at vlan_tag
         * in one layer tag case.
@@ -2162,17 +2198,13 @@ static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
        if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
                u16 vlan_tag;
 
-               vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
-               if (!(vlan_tag & VLAN_VID_MASK))
-                       vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
+               vlan_tag = hns3_parse_vlan_tag(ring, desc, l234info);
                if (vlan_tag & VLAN_VID_MASK)
                        __vlan_hwaccel_put_tag(skb,
                                               htons(ETH_P_8021Q),
                                               vlan_tag);
        }
 
-       l234info = le32_to_cpu(desc->rx.l234_info);
-
        if (unlikely(!hnae_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
                netdev_err(netdev, "no valid bd,%016llx,%016llx\n",
                           ((u64 *)desc)[0], ((u64 *)desc)[1]);

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
index 5b40f5a..38e91ca 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
@@ -104,6 +104,9 @@ enum hns3_nic_state {
 #define HNS3_RXD_L4ID_S                                8
 #define HNS3_RXD_L4ID_M                                (0xf << HNS3_RXD_L4ID_S)
 #define HNS3_RXD_FRAG_B                                12
+#define HNS3_RXD_STRP_TAGP_S                   13
+#define HNS3_RXD_STRP_TAGP_M                   (0x3 << HNS3_RXD_STRP_TAGP_S)
+
 #define HNS3_RXD_L2E_B                         16
 #define HNS3_RXD_L3E_B                         17
 #define HNS3_RXD_L4E_B                         18