drm/i915/bxt: Add WaSetClckGatingDisableMedia

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 65b5682..495ac17 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6897,6 +6897,7 @@ enum skl_disp_power_wells {
 #define   GEN7_DOP_CLOCK_GATE_ENABLE           (1<<0)
 #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE     (1<<2)
 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE       (1<<4)
+#define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1<<6)
 
 #define GEN8_GARBCNTL                   0xB004
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 64bc77e..920872a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -134,6 +134,12 @@ static void bxt_init_clock_gating(struct drm_device *dev)
                 */
                I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
        }
+
+       /* WaSetClckGatingDisableMedia:bxt */
+       if (INTEL_REVID(dev) == BXT_REVID_A0) {
+               I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
+                                           ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
+       }
 }
 
 static void i915_pineview_get_mem_freq(struct drm_device *dev)