x86/cpu, kvm: Add the Null Selector Clears Base feature

The Null Selector Clears Base feature was being open-coded for KVM.
Add it to its newly added native CPUID leaf 0x80000021 EAX proper.

Also drop the bit description comments now it's more self-describing.

  [ bp: Convert test in check_null_seg_clears_base() too. ]

Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20230124163319.2277355-6-kim.phillips@amd.com

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 901128e..6bed80c 100644 (file)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -430,6 +430,7 @@
 /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
 #define X86_FEATURE_NO_NESTED_DATA_BP  (20*32+ 0) /* "" No Nested Data Breakpoints */
 #define X86_FEATURE_LFENCE_RDTSC       (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */
+#define X86_FEATURE_NULL_SEL_CLR_BASE  (20*32+ 6) /* "" Null Selector Clears Base */
 
 /*
  * BUG word(s)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index e6f3234..e6bf9b1 100644 (file)
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1685,9 +1685,7 @@ void check_null_seg_clears_base(struct cpuinfo_x86 *c)
        if (!IS_ENABLED(CONFIG_X86_64))
                return;
 
-       /* Zen3 CPUs advertise Null Selector Clears Base in CPUID. */
-       if (c->extended_cpuid_level >= 0x80000021 &&
-           cpuid_eax(0x80000021) & BIT(6))
+       if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE))
                return;
 
        /*

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 12455dc..dde8d6b 100644 (file)
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -743,7 +743,7 @@ void kvm_set_cpu_caps(void)
 
        kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
                F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ |
-               BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */
+               F(NULL_SEL_CLR_BASE) | 0 /* PrefetchCtlMsr */
        );
 
        /*
@@ -759,7 +759,7 @@ void kvm_set_cpu_caps(void)
        if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
                kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC);
        if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
-               kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(6) /* NULL_SEL_CLR_BASE */;
+               kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE);
        kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(9) /* NO_SMM_CTL_MSR */;
 
        kvm_cpu_cap_mask(CPUID_C000_0001_EDX,