Ops.push_back(Chain);
// Writes to two registers.
- std::vector<EVT> RetType;
- RetType.push_back(MVT::i32);
- RetType.push_back(MVT::i32);
- RetType.push_back(MVT::Other);
+ const EVT RetType[] = {MVT::i32, MVT::i32, MVT::Other};
ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, RetType, Ops));
return;
ResTys.push_back(MVT::Other);
// Place arguments in the right order.
- SmallVector<SDValue, 7> Ops;
- Ops.push_back(MemAddr);
- Ops.push_back(getAL(CurDAG, dl));
- Ops.push_back(CurDAG->getRegister(0, MVT::i32));
- Ops.push_back(Chain);
+ SDValue Ops[] = {MemAddr, getAL(CurDAG, dl),
+ CurDAG->getRegister(0, MVT::i32), Chain};
SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
// Transfer memoperands.
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
case Intrinsic::arm_neon_vst2: {
static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
ARM::VST2d32, ARM::VST1q64 };
- static uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
- ARM::VST2q32Pseudo };
+ static const uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
+ ARM::VST2q32Pseudo };
SelectVST(N, false, 2, DOpcodes, QOpcodes, nullptr);
return;
}
case ARMISD::VTBL1: {
SDLoc dl(N);
EVT VT = N->getValueType(0);
- SmallVector<SDValue, 6> Ops;
-
- Ops.push_back(N->getOperand(0));
- Ops.push_back(N->getOperand(1));
- Ops.push_back(getAL(CurDAG, dl)); // Predicate
- Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
+ SDValue Ops[] = {N->getOperand(0), N->getOperand(1),
+ getAL(CurDAG, dl), // Predicate
+ CurDAG->getRegister(0, MVT::i32)}; // Predicate Register
ReplaceNode(N, CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops));
return;
}
SDValue V1 = N->getOperand(1);
SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
- SmallVector<SDValue, 6> Ops;
- Ops.push_back(RegSeq);
- Ops.push_back(N->getOperand(2));
- Ops.push_back(getAL(CurDAG, dl)); // Predicate
- Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
+ SDValue Ops[] = {RegSeq, N->getOperand(2), getAL(CurDAG, dl), // Predicate
+ CurDAG->getRegister(0, MVT::i32)}; // Predicate Register
ReplaceNode(N, CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops));
return;
}