OSDN Git Service

drm/amdgpu: add member to store vm fault interrupt masks
authorHuang Rui <ray.huang@amd.com>
Tue, 21 Jul 2020 06:24:43 +0000 (14:24 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 22 Jul 2020 22:42:42 +0000 (18:42 -0400)
This patch adds a member in vmhub structure to store the vm fault interrupt
masks for different version gfxhubs/mmhubs.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

index acdb61c..e11c21a 100644 (file)
@@ -92,6 +92,8 @@ struct amdgpu_vmhub {
        uint32_t        ctx_addr_distance; /* include LO32/HI32 */
        uint32_t        eng_distance;
        uint32_t        eng_addr_distance; /* include LO32/HI32 */
+
+       uint32_t        vm_cntx_cntl_vm_fault;
 };
 
 /*
index 394e6f5..993185f 100644 (file)
@@ -390,4 +390,12 @@ void gfxhub_v2_0_init(struct amdgpu_device *adev)
                mmGCVM_INVALIDATE_ENG0_REQ;
        hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
                mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+
+       hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 }
index fa0bca3..07cae64 100644 (file)
@@ -389,6 +389,14 @@ void gfxhub_v2_1_init(struct amdgpu_device *adev)
                mmGCVM_INVALIDATE_ENG0_REQ;
        hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
                mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+
+       hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 }
 
 int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
index 757fa8e..48134b9 100644 (file)
@@ -381,6 +381,14 @@ void mmhub_v2_0_init(struct amdgpu_device *adev)
                mmMMVM_INVALIDATE_ENG0_REQ;
        hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
                mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+
+       hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+               MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 }
 
 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,