clk: rockchip: add 533.25MHz to rk3399 clock rates table

We need to get the accurate 533.25MHz for the DP display.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 8387c7a..a5a3f41 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -93,6 +93,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
        RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
        RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
        RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
+       RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0),
        RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
        RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
        RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),