[ARM] Add the non-MVE instructions in Arm v8.1-M.

This should have been part of r362953, but I had a finger-trouble
incident and committed the old rather than new version of the patch.
Sorry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362955 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index d8c6d3e..e324dbe 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -5167,8 +5167,7 @@ def t2LE : t2LOL<(outs ), (ins lelabel_u11:$label), "le", "$label"> {
   let Inst{10-1} = label{10-1};
 }
 
-let Uses = [CPSR] in {
-class CS<string iname, list<dag> pattern=[]>
+class CS<string iname, bits<4> opcode, list<dag> pattern=[]>
   : V8_1MI<(outs rGPR:$Rd), (ins GPRwithZR:$Rn, GPRwithZR:$Rm, pred_noal:$fcond),
            AddrModeNone, NoItinerary, iname, "$Rd, $Rn, $Rm, $fcond", "", pattern> {
   bits<4> Rd;
@@ -5178,27 +5177,18 @@ class CS<string iname, list<dag> pattern=[]>
 
   let Inst{31-20} = 0b111010100101;
   let Inst{19-16} = Rn{3-0};
+  let Inst{15-12} = opcode;
   let Inst{11-8} = Rd{3-0};
   let Inst{7-4} = fcond{3-0};
   let Inst{3-0} = Rm{3-0};
-}
-}
 
-def t2CSEL : CS<"csel"> {
-  let Inst{15-12} = 0b1000;
+  let Uses = [CPSR];
 }
 
-def t2CSINC : CS<"csinc"> {
-  let Inst{15-12} = 0b1001;
-}
-
-def t2CSINV : CS<"csinv"> {
-  let Inst{15-12} = 0b1010;
-}
-
-def t2CSNEG : CS<"csneg"> {
-  let Inst{15-12} = 0b1011;
-}
+def t2CSEL  : CS<"csel",  0b1000>;
+def t2CSINC : CS<"csinc", 0b1001>;
+def t2CSINV : CS<"csinv", 0b1010>;
+def t2CSNEG : CS<"csneg", 0b1011>;
 
 
 // CS aliases.

diff --git a/test/MC/ARM/thumbv8.1m.s b/test/MC/ARM/thumbv8.1m.s
index 9f0fcae..9bb89c7 100644 (file)
--- a/test/MC/ARM/thumbv8.1m.s
+++ b/test/MC/ARM/thumbv8.1m.s
@@ -1096,3 +1096,19 @@ csinv   lr, r2, r2, mi
 # CHECK-FP: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
 # CHECK-NOLOB: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
 csel r0, r0, r1, eq
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable
+it eq
+csel r0, r0, r1, eq
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable
+it eq
+csinc r0, r0, r1, ne
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable
+it gt
+csinv r0, r0, r1, ge
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable
+it lt
+csneg r0, r0, r1, gt