Add support for the 'j' immediate constraint. This is conditionalized on

supporting the instruction that the constraint is for 'movw'.

Part of rdar://9119939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 4a78ad4..fb738cd 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -7485,6 +7485,7 @@ ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
     case 'h': return C_RegisterClass;
     case 'x': return C_RegisterClass;
     case 't': return C_RegisterClass;
+    case 'j': return C_Other; // Constant for movw.
     }
   } else if (Constraint.size() == 2) {
     switch (Constraint[0]) {
@@ -7590,6 +7591,7 @@ void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
   char ConstraintLetter = Constraint[0];
   switch (ConstraintLetter) {
   default: break;
+  case 'j':
   case 'I': case 'J': case 'K': case 'L':
   case 'M': case 'N': case 'O':
     ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
@@ -7604,6 +7606,13 @@ void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
       return;
 
     switch (ConstraintLetter) {
+      case 'j':
+       // Constant suitable for movw, must be between 0 and
+       // 65535.
+       if (Subtarget->hasV6T2Ops())
+         if (CVal >= 0 && CVal <= 65535)
+           break;
+       return;
       case 'I':
         if (Subtarget->isThumb1Only()) {
           // This must be a constant between 0 and 255, for ADD

diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll
index 00257e1..853585d 100644 (file)
--- a/test/CodeGen/ARM/inlineasm3.ll
+++ b/test/CodeGen/ARM/inlineasm3.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon,+v6t2 | FileCheck %s
 
 ; Radar 7449043
 %struct.int32x4_t = type { <4 x i32> }
@@ -71,7 +71,7 @@ entry:
 
 ; Radar 9307836 & 9119939
 
-define double @t7(double %y) nounwind ssp {
+define double @t7(double %y) nounwind {
 entry:
 ; CHECK: t7
 ; CHECK: flds s15, d0
@@ -81,10 +81,20 @@ entry:
 
 ; Radar 9307836 & 9119939
 
-define float @t8(float %y) nounwind ssp {
+define float @t8(float %y) nounwind {
 entry:
 ; CHECK: t8
 ; CHECK: flds s15, s0
   %0 = tail call float asm "flds s15, $0", "=t"() nounwind
   ret float %0
 }
+
+; Radar 9307836 & 9119939
+
+define i32 @t9(i32 %r0) nounwind {
+entry:
+; CHECK: t9
+; CHECK: movw r0, #27182
+  %0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind
+  ret i32 %0
+}