radv: compute the GFX9 fence VA at allocation time

Instead of doing every time we emit cache flushes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index a260596..e75080d 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -335,13 +335,14 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
        if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
            cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
                unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
-               unsigned eop_bug_offset;
+               unsigned fence_offset, eop_bug_offset;
                void *fence_ptr;
 
-               radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
-                                            &cmd_buffer->gfx9_fence_offset,
+               radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0, &fence_offset,
                                             &fence_ptr);
-               cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
+               cmd_buffer->gfx9_fence_va =
+                       radv_buffer_get_va(cmd_buffer->upload.upload_bo);
+               cmd_buffer->gfx9_fence_va += fence_offset;
 
                /* Allocate a buffer for the EOP bug on GFX9. */
                radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
@@ -494,8 +495,7 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
                                RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
 
                if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
-                       va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
-                            cmd_buffer->gfx9_fence_offset;
+                       va = cmd_buffer->gfx9_fence_va;
                        ptr = &cmd_buffer->gfx9_fence_idx;
                }
 

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index dbe483d..85c1890 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1116,8 +1116,7 @@ struct radv_cmd_buffer {
 
        VkResult record_result;
 
-       uint32_t gfx9_fence_offset;
-       struct radeon_winsys_bo *gfx9_fence_bo;
+       uint64_t gfx9_fence_va;
        uint32_t gfx9_fence_idx;
        uint64_t gfx9_eop_bug_va;
 

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 2f32c72..f05096f 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -976,7 +976,7 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
        uint32_t *ptr = NULL;
        uint64_t va = 0;
        if (chip_class == GFX9) {
-               va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) + cmd_buffer->gfx9_fence_offset;
+               va = cmd_buffer->gfx9_fence_va;
                ptr = &cmd_buffer->gfx9_fence_idx;
        }
        si_cs_emit_cache_flush(cmd_buffer->cs,