OSDN Git Service

r600g: Added DB_SHADER_CONTROL defines.
authorTilman Sauerbeck <tilman@code-monkey.de>
Fri, 17 Sep 2010 10:05:26 +0000 (12:05 +0200)
committerTilman Sauerbeck <tilman@code-monkey.de>
Fri, 17 Sep 2010 10:06:07 +0000 (12:06 +0200)
Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
src/gallium/drivers/r600/eg_hw_states.c
src/gallium/drivers/r600/evergreend.h
src/gallium/drivers/r600/r600_hw_states.c
src/gallium/drivers/r600/r600d.h

index e4b5b31..d6f417e 100644 (file)
@@ -367,13 +367,16 @@ static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
        }
        radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
 
-       db_shader_control = 0x210;
+       db_shader_control = 0;
+       db_shader_control |= S_02880C_DUAL_EXPORT_ENABLE(1);
+       db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+
        rshader = &rctx->ps_shader->shader;
        if (rshader->uses_kill)
-               db_shader_control |= (1 << 6);
+               db_shader_control |= S_02880C_KILL_ENABLE(1);
        for (i = 0; i < rshader->noutput; i++) {
                if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
-                       db_shader_control |= 1;
+                       db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
        }
        stencil_ref_mask = 0;
        stencil_ref_mask_bf = 0;
index c8e6710..a3ebc0e 100644 (file)
 #define   S_028D10_IGNORE_SC_ZRANGE(x)                 (((x) & 0x1) << 17)
 #define   G_028D10_IGNORE_SC_ZRANGE(x)                 (((x) >> 17) & 0x1)
 #define   C_028D10_IGNORE_SC_ZRANGE                    0xFFFDFFFF
+#define R_02880C_DB_SHADER_CONTROL                    0x02880C
+#define   S_02880C_Z_EXPORT_ENABLE(x)                  (((x) & 0x1) << 0)
+#define   G_02880C_Z_EXPORT_ENABLE(x)                  (((x) >> 0) & 0x1)
+#define   C_02880C_Z_EXPORT_ENABLE                     0xFFFFFFFE
+#define   S_02880C_Z_ORDER(x)                          (((x) & 0x3) << 4)
+#define   G_02880C_Z_ORDER(x)                          (((x) >> 4) & 0x3)
+#define   C_02880C_Z_ORDER                             0xFFFFFCFF
+#define     V_02880C_LATE_Z                            0
+#define     V_02880C_EARLY_Z_THEN_LATE_Z               1
+#define     V_02880C_RE_Z                              2
+#define     V_02880C_EARLY_Z_THEN_RE_Z                 3
+#define   S_02880C_KILL_ENABLE(x)                      (((x) & 0x1) << 5)
+#define   G_02880C_KILL_ENABLE(x)                      (((x) >> 6) & 0x1)
+#define   C_02880C_KILL_ENABLE                         0xFFFFFFBF
+#define   S_02880C_DUAL_EXPORT_ENABLE(x)               (((x) & 0x1) << 9)
+#define   G_02880C_DUAL_EXPORT_ENABLE(x)               (((x) >> 9) & 0x1)
+#define   C_02880C_DUAL_EXPORT_ENABLE                  0xFFFFFDFF
 #define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
 #define   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) & 0xFF) << 0)
 #define   G_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) >> 0) & 0xFF)
index 1974b20..1449469 100644 (file)
@@ -362,13 +362,16 @@ static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
        }
        radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
 
-       db_shader_control = 0x210;
+       db_shader_control = 0;
+       db_shader_control |= S_02880C_DUAL_EXPORT_ENABLE(1);
+       db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+
        rshader = &rctx->ps_shader->shader;
        if (rshader->uses_kill)
-               db_shader_control |= (1 << 6);
+               db_shader_control |= S_02880C_KILL_ENABLE(1);
        for (i = 0; i < rshader->noutput; i++) {
                if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
-                       db_shader_control |= 1;
+                       db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
        }
        stencil_ref_mask = 0;
        stencil_ref_mask_bf = 0;
index 8ef0074..92ed0a7 100644 (file)
 #define   S_028D10_IGNORE_SC_ZRANGE(x)                 (((x) & 0x1) << 17)
 #define   G_028D10_IGNORE_SC_ZRANGE(x)                 (((x) >> 17) & 0x1)
 #define   C_028D10_IGNORE_SC_ZRANGE                    0xFFFDFFFF
+#define R_02880C_DB_SHADER_CONTROL                    0x02880C
+#define   S_02880C_Z_EXPORT_ENABLE(x)                  (((x) & 0x1) << 0)
+#define   G_02880C_Z_EXPORT_ENABLE(x)                  (((x) >> 0) & 0x1)
+#define   C_02880C_Z_EXPORT_ENABLE                     0xFFFFFFFE
+#define   S_02880C_Z_ORDER(x)                          (((x) & 0x3) << 4)
+#define   G_02880C_Z_ORDER(x)                          (((x) >> 4) & 0x3)
+#define   C_02880C_Z_ORDER                             0xFFFFFCFF
+#define     V_02880C_LATE_Z                            0
+#define     V_02880C_EARLY_Z_THEN_LATE_Z               1
+#define     V_02880C_RE_Z                              2
+#define     V_02880C_EARLY_Z_THEN_RE_Z                 3
+#define   S_02880C_KILL_ENABLE(x)                      (((x) & 0x1) << 5)
+#define   G_02880C_KILL_ENABLE(x)                      (((x) >> 6) & 0x1)
+#define   C_02880C_KILL_ENABLE                         0xFFFFFFBF
+#define   S_02880C_DUAL_EXPORT_ENABLE(x)               (((x) & 0x1) << 9)
+#define   G_02880C_DUAL_EXPORT_ENABLE(x)               (((x) >> 9) & 0x1)
+#define   C_02880C_DUAL_EXPORT_ENABLE                  0xFFFFFDFF
 #define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
 #define   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) & 0xFF) << 0)
 #define   G_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) >> 0) & 0xFF)