[
{
- "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
+ "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x38",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in DRAM or MMIO (Non-DRAM).",
+ "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the L2 cache.",
+ "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the last level cache or other core with HITE/F/M.",
+ "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_atom"
},
"EventName": "MEM_BOUND_STALLS.LOAD",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x7",
"Unit": "cpu_atom"
},
"EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_atom"
},
"EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_atom"
},
"EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of load ops retired that hit in DRAM.",
+ "BriefDescription": "Counts the number of load uops retired that hit in DRAM.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of load ops retired that hit in the L2 cache.",
+ "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache.",
+ "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
+ "Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
"PEBS": "1",
"EventName": "MEM_SCHEDULER_BLOCK.ALL",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
+ "Speculative": "1",
"UMask": "0x7",
"Unit": "cpu_atom"
},
"EventName": "MEM_SCHEDULER_BLOCK.LD_BUF",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
"EventName": "MEM_SCHEDULER_BLOCK.RSV",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_atom"
},
"EventName": "MEM_SCHEDULER_BLOCK.ST_BUF",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_atom"
},
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
+ "L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
+ "L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
+ "L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
+ "L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
+ "L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
+ "L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
+ "L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
+ "L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts all the retired split loads.",
+ "BriefDescription": "Counts the number of retired split load uops.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
},
{
"BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.",
- "CollectPEBSRecord": "2",
+ "CollectPEBSRecord": "3",
"Counter": "0,1,2,3,4,5",
+ "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
- "PEBS": "1",
+ "L1_Hit_Indication": "1",
+ "PEBS": "2",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
"UMask": "0x6",
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
+ "Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"EventName": "TOPDOWN_FE_BOUND.ICACHE",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_atom"
},
{
+ "BriefDescription": "L1D.HWPF_MISS",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x51",
+ "EventName": "L1D.HWPF_MISS",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "Speculative": "1",
+ "UMask": "0x20",
+ "Unit": "cpu_core"
+ },
+ {
"BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventName": "L1D.REPLACEMENT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "L1D_PEND_MISS.FB_FULL",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "L1D_PEND_MISS.L2_STALL",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "L1D_PEND_MISS.L2_STALLS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "L1D_PEND_MISS.PENDING",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "L2_LINES_IN.ALL",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x1f",
"Unit": "cpu_core"
},
{
- "BriefDescription": "All L2 requests.[This event is alias to L2_RQSTS.REFERENCES]",
+ "BriefDescription": "All accesses to L2 cache[This event is alias to L2_RQSTS.REFERENCES]",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.ALL",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0xff",
"Unit": "cpu_core"
},
"EventName": "L2_REQUEST.MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x3f",
"Unit": "cpu_core"
},
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0xe4",
"Unit": "cpu_core"
},
{
- "BriefDescription": "Demand Data Read requests",
+ "BriefDescription": "Demand Data Read access L2 cache",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0xe1",
"Unit": "cpu_core"
},
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x27",
"Unit": "cpu_core"
},
{
+ "BriefDescription": "L2_RQSTS.ALL_HWPF",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x24",
+ "EventName": "L2_RQSTS.ALL_HWPF",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "200003",
+ "Speculative": "1",
+ "UMask": "0xf0",
+ "Unit": "cpu_core"
+ },
+ {
"BriefDescription": "RFO requests to L2 cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_RFO",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0xe2",
"Unit": "cpu_core"
},
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0xc4",
"Unit": "cpu_core"
},
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x24",
"Unit": "cpu_core"
},
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0xc1",
"Unit": "cpu_core"
},
{
- "BriefDescription": "Demand Data Read miss L2, no rejects",
+ "BriefDescription": "Demand Data Read miss L2 cache",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x21",
"Unit": "cpu_core"
},
{
+ "BriefDescription": "L2_RQSTS.HWPF_MISS",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x24",
+ "EventName": "L2_RQSTS.HWPF_MISS",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "200003",
+ "Speculative": "1",
+ "UMask": "0x30",
+ "Unit": "cpu_core"
+ },
+ {
"BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x3f",
"Unit": "cpu_core"
},
{
- "BriefDescription": "All L2 requests.[This event is alias to L2_REQUEST.ALL]",
+ "BriefDescription": "All accesses to L2 cache[This event is alias to L2_REQUEST.ALL]",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0xff",
"Unit": "cpu_core"
},
"EventName": "L2_RQSTS.RFO_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0xc2",
"Unit": "cpu_core"
},
"EventName": "L2_RQSTS.RFO_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x22",
"Unit": "cpu_core"
},
"EventName": "L2_RQSTS.SWPF_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0xc8",
"Unit": "cpu_core"
},
"EventName": "L2_RQSTS.SWPF_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x28",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "LONGEST_LAT_CACHE.MISS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x41",
"Unit": "cpu_core"
},
"EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0xfd",
"Unit": "cpu_core"
},
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "MEM_STORE_RETIRED.L2_HIT",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x44",
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "Counter": "0,1,2,3",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"Unit": "cpu_core"
},
{
- "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
},
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "Counter": "0,1,2,3",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x80",
"Unit": "cpu_core"
},
"EventName": "OFFCORE_REQUESTS.DATA_RD",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
"EventName": "SW_PREFETCH_ACCESS.NTA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
"EventName": "SW_PREFETCH_ACCESS.T0",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "SW_PREFETCH_ACCESS.T1_T2",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
}
-]
\ No newline at end of file
+]
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_atom"
},
"Unit": "cpu_atom"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "ARITH.FPDIV_ACTIVE",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventName": "ARITH.FPDIV_ACTIVE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "ASSISTS.FP",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "ASSISTS.SSE_AVX_MIX",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.SSE_AVX_MIX",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_0",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_5",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"UMask": "0x2",
"Unit": "cpu_core"
}
-]
\ No newline at end of file
+]
"EventName": "BACLEARS.ANY",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_atom"
},
"EventName": "ICACHE.ACCESSES",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x3",
"Unit": "cpu_atom"
},
"EventName": "ICACHE.MISSES",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
"EventName": "DECODE.LCP",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "500009",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"Unit": "cpu_core"
},
{
+ "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc6",
+ "EventName": "FRONTEND_RETIRED.MS_FLOWS",
+ "MSRIndex": "0x3F7",
+ "MSRValue": "0x8",
+ "PEBS": "1",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "SampleAfterValue": "100007",
+ "TakenAlone": "1",
+ "UMask": "0x1",
+ "Unit": "cpu_core"
+ },
+ {
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "ICACHE_DATA.STALLS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "500009",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "ICACHE_TAG.STALLS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "IDQ.DSB_CYCLES_ANY",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
"EventName": "IDQ.DSB_CYCLES_OK",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
"EventName": "IDQ.DSB_UOPS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
"EventName": "IDQ.MITE_CYCLES_ANY",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "IDQ.MITE_CYCLES_OK",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "IDQ.MITE_UOPS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "IDQ.MS_CYCLES_ANY",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
"EventName": "IDQ.MS_SWITCHES",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
"EventName": "IDQ.MS_UOPS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"Invert": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
}
-]
\ No newline at end of file
+]
[
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
+ "CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.ANY_AT_RET",
+ "PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0xff",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
- "Counter": "0,1,2,3",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.L1_BOUND_AT_RET",
+ "PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0xf4",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases when load subsequently retires when load subsequently retires.",
+ "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.OTHER_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0xc0",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a pagewalk when load subsequently retires.",
+ "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.PGWALK_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0xa0",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a store address match when load subsequently retires.",
+ "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.ST_ADDR_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x84",
"Unit": "cpu_atom"
},
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
+ "Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
+ "Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x6",
"Unit": "cpu_core"
},
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x3",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "MEMORY_ACTIVITY.STALLS_L2_MISS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "5",
"EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x5",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "MEMORY_ACTIVITY.STALLS_L3_MISS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "9",
"EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x9",
"Unit": "cpu_core"
},
"Unit": "cpu_core"
},
{
- "BriefDescription": "Retired instructions with at least 1 store uop. This PEBS event is the trigger for stores sampled by the PEBS Store Facility.",
+ "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
"CollectPEBSRecord": "2",
"Data_LA": "1",
"EventCode": "0xcd",
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
},
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"UMask": "0x1",
"Unit": "cpu_core"
}
-]
\ No newline at end of file
+]
[
{
"BriefDescription": "Counts demand data reads that have any type of response.",
- "Counter": "0,1,2,3",
+ "Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
- "Counter": "0,1,2,3",
+ "Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
- "Counter": "0,1,2,3",
+ "Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xc1",
- "EventName": "ASSISTS.ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "SampleAfterValue": "100003",
- "UMask": "0x1f",
- "Unit": "cpu_core"
- },
- {
- "BriefDescription": "Count all other microcode assist beyond FP, AVX_TILE_MIX and A/D assists (counted by their own sub-events). This includes assists at uop writeback like AVX* load/store (non-FP) assists, Null Assist in SNC (due to lack of FP precision format convert with FMA3x3 uarch) or assists generated by ROB (like assists to due to Missprediction for FSW register - fixed in SNC)",
+ "BriefDescription": "ASSISTS.HARDWARE",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.HARDWARE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "ASSISTS.PAGE_FAULT",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.PAGE_FAULT",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "CORE_POWER.LICENSE_1",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LICENSE_1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "CORE_POWER.LICENSE_2",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LICENSE_2",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "CORE_POWER.LICENSE_3",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LICENSE_3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
- "Counter": "0,1,2,3",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
},
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
- "Counter": "0,1,2,3",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
- "Counter": "0,1,2,3",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "XQ.FULL_CYCLES",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventName": "XQ.FULL_CYCLES",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
}
-]
\ No newline at end of file
+]
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and Interrupt call and return.",
+ "BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "CPU_CLK_UNHALTED.CORE",
"PEBScounters": "33",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
"EventName": "CPU_CLK_UNHALTED.CORE_P",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"Unit": "cpu_atom"
},
{
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PEBScounters": "34",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x3",
"Unit": "cpu_atom"
},
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PEBScounters": "33",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of instructions retired. (Fixed event)",
+ "BriefDescription": "Counts the total number of instructions retired. (Fixed event)",
"CollectPEBSRecord": "2",
"Counter": "32",
"EventName": "INST_RETIRED.ANY",
"EventName": "MACHINE_CLEARS.DISAMBIGUATION",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_atom"
},
"EventName": "MACHINE_CLEARS.MRN_NUKE",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x80",
"Unit": "cpu_atom"
},
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.PAGE_FAULT",
- "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_atom"
},
"EventName": "MACHINE_CLEARS.SLOW",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
+ "Speculative": "1",
"UMask": "0x6f",
"Unit": "cpu_atom"
},
"EventName": "MACHINE_CLEARS.SMC",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of issue slots not consumed due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing uops from the UROM until a specified older uop retires.",
+ "BriefDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x75",
"EventName": "SERIALIZATION.NON_C01_MS_SCB",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_BAD_SPECULATION.ALL",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"Unit": "cpu_atom"
},
{
"EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x3",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_BAD_SPECULATION.NUKE",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_BE_BOUND.ALL",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"Unit": "cpu_atom"
},
{
"EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_BE_BOUND.REGISTER",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x40",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_FE_BOUND.ALL",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"Unit": "cpu_atom"
},
{
"EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x40",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_FE_BOUND.CISC",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_FE_BOUND.DECODE",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x8d",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.",
+ "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x72",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_FE_BOUND.ITLB",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_FE_BOUND.OTHER",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x80",
"Unit": "cpu_atom"
},
"EventName": "TOPDOWN_FE_BOUND.PREDECODE",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_atom"
},
"EventName": "ARITH.DIVIDER_ACTIVE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x9",
"Unit": "cpu_core"
},
"EventName": "ARITH.DIV_ACTIVE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x9",
"Unit": "cpu_core"
},
"EventName": "ARITH.FP_DIVIDER_ACTIVE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "This event counts the cycles the integer divider is busy.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb0",
+ "EventName": "ARITH.IDIV_ACTIVE",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "SampleAfterValue": "1000003",
+ "Speculative": "1",
+ "UMask": "0x8",
+ "Unit": "cpu_core"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventName": "ARITH.INT_DIVIDER_ACTIVE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
{
+ "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc1",
+ "EventName": "ASSISTS.ANY",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1f",
+ "Unit": "cpu_core"
+ },
+ {
"BriefDescription": "All branch instructions retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"Unit": "cpu_core"
},
{
+ "BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xec",
+ "EventName": "CPU_CLK_UNHALTED.C01",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "SampleAfterValue": "2000003",
+ "Speculative": "1",
+ "UMask": "0x10",
+ "Unit": "cpu_core"
+ },
+ {
+ "BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xec",
+ "EventName": "CPU_CLK_UNHALTED.C02",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "SampleAfterValue": "2000003",
+ "Speculative": "1",
+ "UMask": "0x20",
+ "Unit": "cpu_core"
+ },
+ {
+ "BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xec",
+ "EventName": "CPU_CLK_UNHALTED.C0_WAIT",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "SampleAfterValue": "2000003",
+ "Speculative": "1",
+ "UMask": "0x70",
+ "Unit": "cpu_core"
+ },
+ {
"BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "25003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "CPU_CLK_UNHALTED.PAUSE",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.PAUSE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x40",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventName": "CPU_CLK_UNHALTED.PAUSE_INST",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x40",
"Unit": "cpu_core"
},
"EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PEBScounters": "34",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x3",
"Unit": "cpu_core"
},
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PEBScounters": "33",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"Unit": "cpu_core"
},
{
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0xc",
"Unit": "cpu_core"
},
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x5",
"Unit": "cpu_core"
},
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
"EventName": "EXE_ACTIVITY.BOUND_ON_LOADS",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x21",
"Unit": "cpu_core"
},
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x40",
"Unit": "cpu_core"
},
{
+ "BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xa6",
+ "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "SampleAfterValue": "1000003",
+ "Speculative": "1",
+ "UMask": "0x80",
+ "Unit": "cpu_core"
+ },
+ {
"BriefDescription": "Instruction decoders utilized in a cycle",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventName": "INST_DECODED.DECODERS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "INST_RETIRED.MACRO_FUSED",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "INST_RETIRED.REP_ITERATION",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "500009",
+ "Speculative": "1",
"UMask": "0x80",
"Unit": "cpu_core"
},
"EventName": "INT_MISC.RECOVERY_CYCLES",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "500009",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xad",
"MSRValue": "0x7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"TakenAlone": "1",
"UMask": "0x40",
"Unit": "cpu_core"
"EventName": "INT_MISC.UOP_DROPPING",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "INT_VEC_RETIRED.128BIT",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "INT_VEC_RETIRED.256BIT",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "INT_VEC_RETIRED.MUL_256",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "INT_VEC_RETIRED.SHUFFLES",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "INT_VEC_RETIRED.VNNI_128",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "INT_VEC_RETIRED.VNNI_256",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "LD_BLOCKS.ADDRESS_ALIAS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "LD_BLOCKS.NO_SR",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x88",
"Unit": "cpu_core"
},
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x82",
"Unit": "cpu_core"
},
"EventName": "LOAD_HIT_PREFETCH.SWPF",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"CounterMask": "1",
"EventCode": "0xa8",
"EventName": "LSD.CYCLES_ACTIVE",
- "PEBScounters": "0,1,2,3",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"CounterMask": "6",
"EventCode": "0xa8",
"EventName": "LSD.CYCLES_OK",
- "PEBScounters": "0,1,2,3",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "LSD.UOPS",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "MACHINE_CLEARS.COUNT",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "MACHINE_CLEARS.SMC",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "MISC2_RETIRED.LFENCE",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe0",
"EventName": "MISC2_RETIRED.LFENCE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "400009",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
"EventName": "RESOURCE_STALLS.SB",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
"EventName": "RESOURCE_STALLS.SCOREBOARD",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "10000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventCode": "0xa4",
"EventName": "TOPDOWN.BAD_SPEC_SLOTS",
"SampleAfterValue": "10000003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventCode": "0xa4",
"EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
"SampleAfterValue": "10000003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.MEMORY_BOUND_SLOTS",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "10000003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
"EventName": "TOPDOWN.SLOTS",
"PEBScounters": "35",
"SampleAfterValue": "10000003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "TOPDOWN.SLOTS_P",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "10000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "UOPS_DECODED.DEC0_UOPS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UOPS_DECODED.DEC0_UOPS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "UOPS_DISPATCHED.PORT_0",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "UOPS_DISPATCHED.PORT_1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "UOPS_DISPATCHED.PORT_2_3_10",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "UOPS_DISPATCHED.PORT_4_9",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
"EventName": "UOPS_DISPATCHED.PORT_5_11",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
"EventName": "UOPS_DISPATCHED.PORT_6",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x40",
"Unit": "cpu_core"
},
"EventName": "UOPS_DISPATCHED.PORT_7_8",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x80",
"Unit": "cpu_core"
},
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "UOPS_EXECUTED.CYCLES_GE_1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "UOPS_EXECUTED.CYCLES_GE_2",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "UOPS_EXECUTED.CYCLES_GE_3",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "UOPS_EXECUTED.CYCLES_GE_4",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"Invert": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"Invert": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "UOPS_EXECUTED.THREAD",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"EventName": "UOPS_EXECUTED.X87",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
"EventName": "UOPS_ISSUED.ANY",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "Retired uops except the last uop of each instruction.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"Unit": "cpu_core"
},
{
- "BriefDescription": "TBD",
+ "BriefDescription": "UOPS_RETIRED.MS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"UMask": "0x2",
"Unit": "cpu_core"
}
-]
\ No newline at end of file
+]
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_atom"
},
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DTLB miss when load subsequently retires.",
+ "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.DTLB_MISS_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x90",
"Unit": "cpu_atom"
},
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_core"
},
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_core"
},
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
"EventName": "ITLB_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
"EventName": "ITLB_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_core"
},
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
"EventName": "ITLB_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
}
-]
\ No newline at end of file
+]
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