but a4 instruction degraded...
);
end component;
-
--------- signals for address calucuration ----------
signal al_buf_we_n : std_logic;
signal ah_buf_we_n : std_logic;
signal addr_c_in : std_logic;
signal addr_c : std_logic;
+signal addr_c_reg : std_logic;
signal pcl_carry_reg_in : std_logic;
signal d_oe_n : std_logic;
begin
-
----------------------------------------
-- address calucurator instances ----
----------------------------------------
addr_calc_inst : address_calculator generic map (dsize)
port map (a_sel, addr1, addr2, addr_out, addr_c_in, addr_c);
+ ea_carry_dff_bit : d_flip_flop_bit
+ port map(clk, '1', '1',
+ '0', addr_c, addr_c_reg);
----------------------------------------
-- arithmatic operation instances ----
---rel val is on the d_bus.
addr2 <= int_d_bus;
addr_back <= addr_out;
- ea_carry <= addr_c;
+ addr_c_in <= '0';
+ ea_carry <= addr_c_reg;
--keep the value in the cycle
al_buf_we_n <= '0';
al_reg_in <= addr_out;
- if (clk = '0') then
- abl <= addr_out;
- else
- abl <= al_reg;
- end if;
abh <= bah;
+ abl <= addr_out;
end if;
elsif (indir_n = '0') then
abh <= bah;
generic (dsize : integer := 8);
port (
-- signal dbg_ea_carry : out std_logic;
- signal dbg_wait_a58_branch_next : out std_logic;
set_clk : in std_logic;
signal nmi_handled_n : std_logic;
-- page boundary handling
-signal wait_a58_branch_next : std_logic;
-
signal wk_next_cycle : std_logic_vector (5 downto 0);
signal wk_acc_cmd : std_logic_vector(3 downto 0);
signal wk_x_cmd : std_logic_vector(3 downto 0);
signal wk_stat_alu_we_n : std_logic;
begin
- dbg_wait_a58_branch_next <= wait_a58_branch_next;
---pc page next is connected to top bit of exec_cycle
pch_inc_input <= not exec_cycle(5);
port map(set_clk, '1', '1', '0', pch_inc_input, pch_inc_n);
--acc,x,y next cycle is changed when it goes page across.
- next_cycle <= T3 when ea_carry = '1' and wait_a58_branch_next = '1' else
- wk_next_cycle;
+ --The conditional branch instructions all have the form xxy10000
+ next_cycle <= wk_next_cycle;
acc_cmd <= wk_acc_cmd(3) & '1' & wk_acc_cmd(1) & '1'
- when ea_carry = '1' and wait_a58_branch_next = '1' else
+ when ea_carry = '1' and
+ wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
wk_acc_cmd;
x_cmd <= wk_x_cmd(3) & '1' & wk_x_cmd(1 downto 0)
- when ea_carry = '1' and wait_a58_branch_next = '1' else
+ when ea_carry = '1' and
+ wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
wk_x_cmd;
y_cmd <= wk_y_cmd(3) & '1' & wk_y_cmd(1 downto 0)
- when ea_carry = '1' and wait_a58_branch_next = '1' else
+ when ea_carry = '1' and
+ wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
wk_y_cmd;
- stat_alu_we_n <= '1' when ea_carry = '1' and wait_a58_branch_next = '1' else
+ stat_alu_we_n <= '1' when ea_carry = '1' and
+ wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
wk_stat_alu_we_n;
main_p : process (set_clk, res_n, nmi_n)
- --a58_branch_wk_next_cycle)
-------------------------------------------------------------
-------------------------------------------------------------
n_vec_oe_n <= '1';
i_vec_oe_n <= '1';
- wait_a58_branch_next <= '0';
end procedure;
procedure fetch_inst (inc_pcl : in std_logic) is
back_oe(pch_cmd, '0');
back_we(pcl_cmd, '0');
- wait_a58_branch_next <= '1';
wk_next_cycle <= T0;
- elsif exec_cycle = T3 then
+ elsif (exec_cycle = T0 and ea_carry = '1') then
d_print("page crossed.");
--page crossed. adh calc.
back_we(pcl_cmd, '1');
stat_bus_all_n <= '1';
stat_bus_nz_n <= '1';
wk_stat_alu_we_n <= '1';
- wait_a58_branch_next <= '0';
--pc l/h is reset vector.
pcl_cmd <= "1110";
signal dbg_int_d_bus : out std_logic_vector(7 downto 0);\r
signal dbg_exec_cycle : out std_logic_vector (5 downto 0);\r
signal dbg_ea_carry : out std_logic;\r
- signal dbg_wait_a58_branch_next : out std_logic;\r
\r
-- signal dbg_index_bus : out std_logic_vector(7 downto 0);\r
-- signal dbg_acc_bus : out std_logic_vector(7 downto 0);\r
generic (dsize : integer := 8);
port ( \r
--signal dbg_ea_carry : out std_logic;\r
- signal dbg_wait_a58_branch_next : out std_logic;\r
\r
set_clk : in std_logic;
trig_clk : in std_logic;
dec_inst : decoder generic map (dsize)
port map(\r
--dbg_ea_carry ,\r
- dbg_wait_a58_branch_next ,\r
\r
set_clk,
trigger_clk,
signal dbg_int_d_bus : out std_logic_vector(7 downto 0);
signal dbg_exec_cycle : out std_logic_vector (5 downto 0);
signal dbg_ea_carry : out std_logic;
- signal dbg_wait_a58_branch_next : out std_logic;
-- signal dbg_index_bus : out std_logic_vector(7 downto 0);
-- signal dbg_acc_bus : out std_logic_vector(7 downto 0);
signal dbg_status : out std_logic_vector(7 downto 0);
signal dbg_int_d_bus : out std_logic_vector(7 downto 0);
signal dbg_exec_cycle : out std_logic_vector (5 downto 0);
signal dbg_ea_carry : out std_logic;
- signal dbg_wait_a58_branch_next : out std_logic;
-- signal dbg_index_bus : out std_logic_vector(7 downto 0);
-- signal dbg_acc_bus : out std_logic_vector(7 downto 0);
signal dbg_status : out std_logic_vector(7 downto 0);
dbg_int_d_bus,
dbg_exec_cycle,
dbg_ea_carry,
- dbg_wait_a58_branch_next,
-- dbg_index_bus,
-- dbg_acc_bus,
dbg_status,
signal dbg_int_d_bus : out std_logic_vector(7 downto 0);
signal dbg_exec_cycle : out std_logic_vector (5 downto 0);
signal dbg_ea_carry : out std_logic;
- signal dbg_wait_a58_branch_next : out std_logic;
-- signal dbg_index_bus : out std_logic_vector(7 downto 0);
-- signal dbg_acc_bus : out std_logic_vector(7 downto 0);
signal dbg_status : out std_logic_vector(7 downto 0);
signal dbg_int_d_bus : std_logic_vector(7 downto 0);
signal dbg_exec_cycle : std_logic_vector (5 downto 0);
signal dbg_ea_carry : std_logic;
- signal dbg_wait_a58_branch_next : std_logic;
-- signal dbg_index_bus : std_logic_vector(7 downto 0);
-- signal dbg_acc_bus : std_logic_vector(7 downto 0);
signal dbg_status : std_logic_vector(7 downto 0);
dbg_int_d_bus,
dbg_exec_cycle ,
dbg_ea_carry ,
-dbg_wait_a58_branch_next ,
--dbg_index_bus ,
--dbg_acc_bus ,
dbg_status ,
; single_inst_test\r
; a2_inst_test\r
; a3_inst_test\r
-; a4_inst_test\r
+; a5_inst_test\r
\r
;;test start...\r
jsr single_inst_test\r
jsr a2_inst_test\r
jsr a3_inst_test\r
- jsr a4_inst_test\r
+; jsr a4_inst_test\r
jsr a5_inst_test\r
jsr ppu_test\r
\r
\r
lda #$00\r
ldx #00\r
- beq @fwd\r
+ beq @fwd ;;<<<ok!!!!\r
;;forward page crossing branch\r
@bwd:\r
jmp @fwd\r
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