drm/i915/pmu: Add RC6 residency metrics

For clients like intel-gpu-overlay it is easier to read the
counters via the perf API than having to parse sysfs.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-9-tvrtko.ursulin@linux.intel.com

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index fef389e..1071935 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -361,6 +361,15 @@ static int i915_pmu_event_init(struct perf_event *event)
                        break;
                case I915_PMU_INTERRUPTS:
                        break;
+               case I915_PMU_RC6_RESIDENCY:
+                       if (!HAS_RC6(i915))
+                               ret = -ENODEV;
+                       break;
+               case I915_PMU_RC6p_RESIDENCY:
+               case I915_PMU_RC6pp_RESIDENCY:
+                       if (!HAS_RC6p(i915))
+                               ret = -ENODEV;
+                       break;
                default:
                        ret = -ENOENT;
                        break;
@@ -413,6 +422,24 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
                case I915_PMU_INTERRUPTS:
                        val = count_interrupts(i915);
                        break;
+               case I915_PMU_RC6_RESIDENCY:
+                       intel_runtime_pm_get(i915);
+                       val = intel_rc6_residency_ns(i915,
+                                                    IS_VALLEYVIEW(i915) ?
+                                                    VLV_GT_RENDER_RC6 :
+                                                    GEN6_GT_GFX_RC6);
+                       intel_runtime_pm_put(i915);
+                       break;
+               case I915_PMU_RC6p_RESIDENCY:
+                       intel_runtime_pm_get(i915);
+                       val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
+                       intel_runtime_pm_put(i915);
+                       break;
+               case I915_PMU_RC6pp_RESIDENCY:
+                       intel_runtime_pm_get(i915);
+                       val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
+                       intel_runtime_pm_put(i915);
+                       break;
                }
        }
 
@@ -677,6 +704,10 @@ static struct attribute *i915_pmu_events_attrs[] = {
 
        I915_EVENT_ATTR(interrupts, I915_PMU_INTERRUPTS),
 
+       I915_EVENT(rc6-residency,   I915_PMU_RC6_RESIDENCY,   "ns"),
+       I915_EVENT(rc6p-residency,  I915_PMU_RC6p_RESIDENCY,  "ns"),
+       I915_EVENT(rc6pp-residency, I915_PMU_RC6pp_RESIDENCY, "ns"),
+
        NULL,
 };
 

diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index d840ff0..915a6e8 100644 (file)
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -141,7 +141,11 @@ enum drm_i915_pmu_engine_sample {
 
 #define I915_PMU_INTERRUPTS            __I915_PMU_OTHER(2)
 
-#define I915_PMU_LAST I915_PMU_INTERRUPTS
+#define I915_PMU_RC6_RESIDENCY         __I915_PMU_OTHER(3)
+#define I915_PMU_RC6p_RESIDENCY                __I915_PMU_OTHER(4)
+#define I915_PMU_RC6pp_RESIDENCY       __I915_PMU_OTHER(5)
+
+#define I915_PMU_LAST I915_PMU_RC6pp_RESIDENCY
 
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */