[X86] Flag SLM scheduler model as complete

We just have to locally tag COPY as WriteMove

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320303 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ScheduleSLM.td b/lib/Target/X86/X86ScheduleSLM.td
index 6a2a998..fb0999b 100644 (file)
--- a/lib/Target/X86/X86ScheduleSLM.td
+++ b/lib/Target/X86/X86ScheduleSLM.td
@@ -23,16 +23,11 @@ def SLMModel : SchedMachineModel {
 
   // For small loops, expand by a small factor to hide the backedge cost.
   let LoopMicroOpBufferSize = 10;
-
-  // FIXME: SSE4 is unimplemented. This flag is set to allow
-  // the scheduler to assign a default model to unrecognized opcodes.
-  let CompleteModel = 0;
 }
 
 let SchedModel = SLMModel in {
 
 // Silvermont has 5 reservation stations for micro-ops
-
 def IEC_RSV0 : ProcResource<1>;
 def IEC_RSV1 : ProcResource<1>;
 def FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
@@ -78,6 +73,9 @@ def : WriteRes<WriteLoad,  [MEC_RSV]> { let Latency = 3; }
 def : WriteRes<WriteMove,  [IEC_RSV01]>;
 def : WriteRes<WriteZero,  []>;
 
+// Treat misc copies as a move.
+def : InstRW<[WriteMove], (instrs COPY)>;
+
 defm : SMWriteResPair<WriteALU,   IEC_RSV01, 1>;
 defm : SMWriteResPair<WriteIMul,  IEC_RSV1,  3>;
 defm : SMWriteResPair<WriteShift, IEC_RSV0,  1>;