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Fix a bug that prevented this pattern from matching
author
Chris Lattner
<sabre@nondot.org>
Thu, 3 Nov 2005 05:45:34 +0000
(
05:45
+0000)
committer
Chris Lattner
<sabre@nondot.org>
Thu, 3 Nov 2005 05:45:34 +0000
(
05:45
+0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24161
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/IA64/IA64InstrInfo.td
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diff --git
a/lib/Target/IA64/IA64InstrInfo.td
b/lib/Target/IA64/IA64InstrInfo.td
index
9bd8678
..
7620f4a
100644
(file)
--- a/
lib/Target/IA64/IA64InstrInfo.td
+++ b/
lib/Target/IA64/IA64InstrInfo.td
@@
-360,7
+360,7
@@
def SELECTINT : Pat<(select PR:$which, GR:$src1, GR:$src2),
// load constants of various sizes // FIXME: prettyprint -ve constants
def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>;
def : Pat<(i64 imm64:$imm), (MOVL imm64:$imm)>;
-def : Pat<(i1 1), (CMPEQ r0, r0)>; // TODO: this should just be a ref to p0
+def : Pat<(i1
-
1), (CMPEQ r0, r0)>; // TODO: this should just be a ref to p0
// TODO: support postincrement (reg, imm9) loads+stores - this needs more
// tablegen support