drm/amd/pp: Fix sysfs pp_dpm_pcie bug on CI/VI

when echo "01">pp_dpm_pcie
the pcie dpm will fix in highest link speed.
But user should expect auto speed between
level 0 and level1

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 5f61e70..f82f40f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6642,6 +6642,9 @@ static int ci_dpm_force_clock_level(void *handle,
        if (adev->pm.dpm.forced_level != AMD_DPM_FORCED_LEVEL_MANUAL)
                return -EINVAL;
 
+       if (mask == 0)
+               return -EINVAL;
+
        switch (type) {
        case PP_SCLK:
                if (!pi->sclk_dpm_key_disabled)
@@ -6660,15 +6663,15 @@ static int ci_dpm_force_clock_level(void *handle,
        case PP_PCIE:
        {
                uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
-               uint32_t level = 0;
 
-               while (tmp >>= 1)
-                       level++;
-
-               if (!pi->pcie_dpm_key_disabled)
-                       amdgpu_ci_send_msg_to_smc_with_parameter(adev,
+               if (!pi->pcie_dpm_key_disabled) {
+                       if (fls(tmp) != ffs(tmp))
+                               amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_UnForceLevel);
+                       else
+                               amdgpu_ci_send_msg_to_smc_with_parameter(adev,
                                        PPSMC_MSG_PCIeDPM_ForceLevel,
-                                       level);
+                                       fls(tmp) - 1);
+               }
                break;
        }
        default:

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 0c2e025..c59cb94 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4296,6 +4296,9 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
 {
        struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 
+       if (mask == 0)
+               return -EINVAL;
+
        switch (type) {
        case PP_SCLK:
                if (!data->sclk_dpm_key_disabled)
@@ -4312,15 +4315,15 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
        case PP_PCIE:
        {
                uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
-               uint32_t level = 0;
 
-               while (tmp >>= 1)
-                       level++;
-
-               if (!data->pcie_dpm_key_disabled)
-                       smum_send_msg_to_smc_with_parameter(hwmgr,
+               if (!data->pcie_dpm_key_disabled) {
+                       if (fls(tmp) != ffs(tmp))
+                               smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel);
+                       else
+                               smum_send_msg_to_smc_with_parameter(hwmgr,
                                        PPSMC_MSG_PCIeDPM_ForceLevel,
-                                       level);
+                                       fls(tmp) - 1);
+               }
                break;
        }
        default: