/// getRARegister - This method should return the register where the return
/// address can be found.
virtual unsigned getRARegister() const = 0;
-
+
+ /// getEHExceptionRegister - This method should return the register containing
+ /// the address of the exception info on entry to a landing pad.
+ virtual unsigned getEHExceptionRegister() const = 0;
+
+ /// getEHHandlerRegister - This method should return the register containing
+ /// the switch table selection on entry to an landing pad.
+ virtual unsigned getEHHandlerRegister() const = 0;
+
/// getLocation - This method should return the actual location of a frame
/// variable given the frame index. The location is returned in ML.
/// Subclasses should override this method for special handling of frame
return LowerFORMAL_ARGUMENTS(Op, DAG);
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
+ // Exception address and exception selector. Currently unimplemented.
+ case ISD::EXCEPTIONADDR: break;
+ case ISD::EHSELECTION: break;
}
return SDOperand();
}
return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11;
}
+unsigned ARMRegisterInfo::getEHExceptionRegister() const {
+ assert(0 && "What is the exception register");
+ return 0;
+}
+
+unsigned ARMRegisterInfo::getEHHandlerRegister() const {
+ assert(0 && "What is the exception handler register");
+ return 0;
+}
+
#include "ARMGenRegisterInfo.inc"
// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(MachineFunction &MF) const;
+
+ // Exception handling queries.
+ unsigned getEHExceptionRegister() const;
+ unsigned getEHHandlerRegister() const;
};
} // end namespace llvm
return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64);
//FIXME: implement
case ISD::FRAMEADDR: break;
+ // Exception address and exception selector. Currently unimplemented.
+ case ISD::EXCEPTIONADDR: break;
+ case ISD::EHSELECTION: break;
}
-
+
return SDOperand();
}
return hasFP(MF) ? Alpha::R15 : Alpha::R30;
}
+unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
+ assert(0 && "What is the exception register");
+ return 0;
+}
+
+unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
+ assert(0 && "What is the exception handler register");
+ return 0;
+}
+
#include "AlphaGenRegisterInfo.inc"
std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
unsigned getRARegister() const;
unsigned getFrameRegister(MachineFunction &MF) const;
+ // Exception handling queries.
+ unsigned getEHExceptionRegister() const;
+ unsigned getEHHandlerRegister() const;
+
static std::string getPrettyName(unsigned reg);
};
// Frame & Return address. Currently unimplemented
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
+ // Exception address and exception selector. Currently unimplemented.
+ case ISD::EXCEPTIONADDR: break;
+ case ISD::EHSELECTION: break;
}
return SDOperand();
}
return hasFP(MF) ? IA64::r5 : IA64::r12;
}
+unsigned IA64RegisterInfo::getEHExceptionRegister() const {
+ assert(0 && "What is the exception register");
+ return 0;
+}
+
+unsigned IA64RegisterInfo::getEHHandlerRegister() const {
+ assert(0 && "What is the exception handler register");
+ return 0;
+}
+
#include "IA64GenRegisterInfo.inc"
// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(MachineFunction &MF) const;
+
+ // Exception handling queries.
+ unsigned getEHExceptionRegister() const;
+ unsigned getEHHandlerRegister() const;
};
} // End llvm namespace
}
}
+/// LowerEXCEPTIONADDR - Replace EXCEPTIONADDR with a copy from the exception
+/// register. The register was made live in the ISel.
+static SDOperand LowerEXCEPTIONADDR(SDOperand Op, SelectionDAG &DAG) {
+ const MRegisterInfo *MRI = DAG.getTargetLoweringInfo().
+ getTargetMachine().
+ getRegisterInfo();
+ MVT::ValueType VT = Op.Val->getValueType(0);
+ unsigned Reg = MRI->getEHExceptionRegister();
+ SDOperand Result = DAG.getCopyFromReg(Op.getOperand(0), Reg, VT);
+ return Result.getValue(Op.ResNo);
+}
+
+/// LowerEXCEPTIONADDR - Replace EHSELECTION with a copy from the exception
+/// selection register. The register was made live in the ISel.
+static SDOperand LowerEHSELECTION(SDOperand Op, SelectionDAG &DAG) {
+ const MRegisterInfo *MRI = DAG.getTargetLoweringInfo().
+ getTargetMachine().
+ getRegisterInfo();
+ MVT::ValueType VT = Op.Val->getValueType(0);
+ unsigned Reg = MRI->getEHHandlerRegister();
+ SDOperand Result = DAG.getCopyFromReg(Op.getOperand(1), Reg, VT);
+ return Result.getValue(Op.ResNo);
+}
+
/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
// Frame & Return address. Currently unimplemented
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
+
+ // Exception address and exception selector.
+ case ISD::EXCEPTIONADDR: return LowerEXCEPTIONADDR(Op, DAG);
+ case ISD::EHSELECTION: return LowerEHSELECTION(Op, DAG);
}
return SDOperand();
}
unsigned PPCRegisterInfo::getRARegister() const {
return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
-
}
unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
Moves.push_back(MachineMove(0, Dst, Src));
}
+unsigned PPCRegisterInfo::getEHExceptionRegister() const {
+ return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
+}
+
+unsigned PPCRegisterInfo::getEHHandlerRegister() const {
+ return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
+}
+
#include "PPCGenRegisterInfo.inc"
unsigned getRARegister() const;
unsigned getFrameRegister(MachineFunction &MF) const;
void getInitialFrameState(std::vector<MachineMove> &Moves) const;
+
+ // Exception handling queries.
+ unsigned getEHExceptionRegister() const;
+ unsigned getEHHandlerRegister() const;
};
} // end namespace llvm
// Frame & Return address. Currently unimplemented
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
+ // Exception address and exception selector. Currently unimplemented.
+ case ISD::EXCEPTIONADDR: break;
+ case ISD::EHSELECTION: break;
}
return SDOperand();
}
return SP::G1;
}
+unsigned SparcRegisterInfo::getEHExceptionRegister() const {
+ assert(0 && "What is the exception register");
+ return 0;
+}
+
+unsigned SparcRegisterInfo::getEHHandlerRegister() const {
+ assert(0 && "What is the exception handler register");
+ return 0;
+}
+
#include "SparcGenRegisterInfo.inc"
// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(MachineFunction &MF) const;
+
+ // Exception handling queries.
+ unsigned getEHExceptionRegister() const;
+ unsigned getEHHandlerRegister() const;
};
} // end namespace llvm
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
+ // Exception address and exception selector. Currently unimplemented.
+ case ISD::EXCEPTIONADDR: break;
+ case ISD::EHSELECTION: break;
}
+ return SDOperand();
}
const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
Moves.push_back(MachineMove(0, Dst, Src));
}
+unsigned X86RegisterInfo::getEHExceptionRegister() const {
+ assert(0 && "What is the exception register");
+ return 0;
+}
+
+unsigned X86RegisterInfo::getEHHandlerRegister() const {
+ assert(0 && "What is the exception handler register");
+ return 0;
+}
+
namespace llvm {
unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
switch (VT) {
unsigned getRARegister() const;
unsigned getFrameRegister(MachineFunction &MF) const;
void getInitialFrameState(std::vector<MachineMove> &Moves) const;
+
+ // Exception handling queries.
+ unsigned getEHExceptionRegister() const;
+ unsigned getEHHandlerRegister() const;
};
// getX86SubSuperRegister - X86 utility function. It returns the sub or super