drm/i915: Fold i9xx_set_pll_dividers() into i9xx_enable_pll()

Can't think of a good reason why we'd need to program the FP
dividers so early. Let's just do it when programming the rest
of the DPLL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-12-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2d137cf..9babdf1 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3598,17 +3598,6 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
        intel_encoders_enable(state, crtc);
 }
 
-static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
-{
-       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
-       intel_de_write(dev_priv, FP0(crtc->pipe),
-                      crtc_state->dpll_hw_state.fp0);
-       intel_de_write(dev_priv, FP1(crtc->pipe),
-                      crtc_state->dpll_hw_state.fp1);
-}
-
 static void i9xx_crtc_enable(struct intel_atomic_state *state,
                             struct intel_crtc *crtc)
 {
@@ -3620,8 +3609,6 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
        if (drm_WARN_ON(&dev_priv->drm, crtc->active))
                return;
 
-       i9xx_set_pll_dividers(new_crtc_state);
-
        if (intel_crtc_has_dp_encoder(new_crtc_state))
                intel_dp_set_m_n(new_crtc_state, M1_N1);
 

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 381f6ea..210f91f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1406,6 +1406,9 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
        if (i9xx_has_pps(dev_priv))
                assert_panel_unlocked(dev_priv, pipe);
 
+       intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0);
+       intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1);
+
        /*
         * Apparently we need to have VGA mode enabled prior to changing
         * the P1/P2 dividers. Otherwise the DPLL will keep using the old