* Enable clocks while 7412 reset is asserted, delay
* De-assert 7412 reset
*/
- rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_DECODER_CTRL);
+ rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp,
+ MISC_PERST_DECODER_CTRL);
rst_deco_cntrl.stop_bcm_7412_clk = 0;
rst_deco_cntrl.bcm7412_rst = 1;
- crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg);
+ crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL,
+ rst_deco_cntrl.whole_reg);
msleep_interruptible(10);
- rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_DECODER_CTRL);
+ rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp,
+ MISC_PERST_DECODER_CTRL);
rst_deco_cntrl.bcm7412_rst = 0;
- crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg);
+ crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL,
+ rst_deco_cntrl.whole_reg);
msleep_interruptible(50);
/* Disable OTP_CONTENT_MISC to 0 to disable all secure modes */
* Assert 7412 reset, delay
* Assert 7412 stop clock
*/
- rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_DECODER_CTRL);
+ rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp,
+ MISC_PERST_DECODER_CTRL);
rst_deco_cntrl.stop_bcm_7412_clk = 1;
- crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg);
+ crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL,
+ rst_deco_cntrl.whole_reg);
msleep_interruptible(50);
/* Bus Arbiter Timeout: GISB_ARBITER_TIMER
{
uint32_t reg;
- /* FIXME: jarod: wouldn't we want to write a 0 to the reg? Or does the write clear the bits specified? */
+ /* FIXME: jarod: wouldn't we want to write a 0 to the reg?
+ Or does the write clear the bits specified? */
reg = crystalhd_reg_rd(adp, MISC1_Y_RX_ERROR_STATUS);
if (reg)
crystalhd_reg_wr(adp, MISC1_Y_RX_ERROR_STATUS, reg);
crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (BC_DRAM_FW_CFG_ADDR >> 19));
crystalhd_reg_wr(adp, AES_CMD, 0);
- crystalhd_reg_wr(adp, AES_CONFIG_INFO, (BC_DRAM_FW_CFG_ADDR & 0x7FFFF));
+ crystalhd_reg_wr(adp, AES_CONFIG_INFO,
+ (BC_DRAM_FW_CFG_ADDR & 0x7FFFF));
crystalhd_reg_wr(adp, AES_CMD, 0x1);
- /* FIXME: jarod: I've seen this fail, and introducing extra delays helps... */
+ /* FIXME: jarod: I've seen this fail,
+ and introducing extra delays helps... */
for (i = 0; i < 100; ++i) {
reg = crystalhd_reg_rd(adp, AES_STATUS);
if (reg & 0x1)
return true;
}
-static struct crystalhd_rx_dma_pkt *crystalhd_hw_alloc_rx_pkt(struct crystalhd_hw *hw)
+static struct crystalhd_rx_dma_pkt *crystalhd_hw_alloc_rx_pkt(
+ struct crystalhd_hw *hw)
{
unsigned long flags = 0;
struct crystalhd_rx_dma_pkt *temp = NULL;
}
-static bool crystalhd_code_in_full(struct crystalhd_adp *adp, uint32_t needed_sz,
- bool b_188_byte_pkts, uint8_t flags)
+static bool crystalhd_code_in_full(struct crystalhd_adp *adp,
+ uint32_t needed_sz, bool b_188_byte_pkts, uint8_t flags)
{
uint32_t base, end, writep, readp;
uint32_t cpbSize, cpbFullness, fifoSize;
}
static enum BC_STATUS crystalhd_hw_tx_req_complete(struct crystalhd_hw *hw,
- uint32_t list_id, enum BC_STATUS cs)
+ uint32_t list_id, enum BC_STATUS cs)
{
struct tx_dma_pkt *tx_req;
hw->pwr_lock--;
- tx_req = (struct tx_dma_pkt *)crystalhd_dioq_find_and_fetch(hw->tx_actq, list_id);
+ tx_req = (struct tx_dma_pkt *)crystalhd_dioq_find_and_fetch(
+ hw->tx_actq, list_id);
if (!tx_req) {
if (cs != BC_STS_IO_USER_ABORT)
BCMLOG_ERR("Find and Fetch Did not find req\n");
return crystalhd_dioq_add(hw->tx_freeq, tx_req, false, 0);
}
-static bool crystalhd_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts)
+static bool crystalhd_tx_list0_handler(struct crystalhd_hw *hw,
+ uint32_t err_sts)
{
uint32_t err_mask, tmp;
unsigned long flags = 0;
return true;
}
-static bool crystalhd_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts)
+static bool crystalhd_tx_list1_handler(struct crystalhd_hw *hw,
+ uint32_t err_sts)
{
uint32_t err_mask, tmp;
unsigned long flags = 0;
if (!p_dma_desc || !cnt)
return;
- /* FIXME: jarod: perhaps a modparam desc_debug to enable this, rather than
- * setting ll (log level, I presume) to non-zero? */
+ /* FIXME: jarod: perhaps a modparam desc_debug to enable this,
+ rather than setting ll (log level, I presume) to non-zero? */
if (!ll)
return;
for (ix = ul_desc_index; ix < (ul_desc_index + cnt); ix++) {
- BCMLOG(ll, "%s[%d] Buff[%x:%x] Next:[%x:%x] XferSz:%x Intr:%x,Last:%x\n",
- ((p_dma_desc[ul_desc_index].dma_dir) ? "TDesc" : "RDesc"),
+ BCMLOG(ll,
+ "%s[%d] Buff[%x:%x] Next:[%x:%x] XferSz:%x Intr:%x,Last:%x\n",
+ ((p_dma_desc[ul_desc_index].dma_dir) ? "TDesc" : "RDesc"),
ul_desc_index,
p_dma_desc[ul_desc_index].buff_addr_high,
p_dma_desc[ul_desc_index].buff_addr_low,
/* Get SGLE length */
len = crystalhd_get_sgle_len(ioreq, sg_ix);
if (len % 4) {
- BCMLOG_ERR(" len in sg %d %d %d\n", len, sg_ix, sg_cnt);
+ BCMLOG_ERR(" len in sg %d %d %d\n", len, sg_ix,
+ sg_cnt);
return BC_STS_NOT_IMPL;
}
/* Setup DMA desc with Phy addr & Length at current index. */
desc[ix].dma_dir = ioreq->uinfo.dir_tx;
/* Chain DMA descriptor. */
- addr_temp.full_addr = desc_phy_addr + sizeof(struct dma_descriptor);
+ addr_temp.full_addr = desc_phy_addr +
+ sizeof(struct dma_descriptor);
desc[ix].next_desc_addr_low = addr_temp.low_part;
desc[ix].next_desc_addr_high = addr_temp.high_part;
/* Debug.. */
if ((!len) || (len > crystalhd_get_sgle_len(ioreq, sg_ix))) {
- BCMLOG_ERR("inv-len(%x) Ix(%d) count:%x xfr_sz:%x sg_cnt:%d\n",
- len, ix, count, xfr_sz, sg_cnt);
+ BCMLOG_ERR(
+ "inv-len(%x) Ix(%d) count:%x xfr_sz:%x sg_cnt:%d\n",
+ len, ix, count, xfr_sz, sg_cnt);
return BC_STS_ERROR;
}
/* Length expects Multiple of 4 */
return BC_STS_SUCCESS;
}
-static enum BC_STATUS crystalhd_xlat_sgl_to_dma_desc(struct crystalhd_dio_req *ioreq,
+static enum BC_STATUS crystalhd_xlat_sgl_to_dma_desc(
+ struct crystalhd_dio_req *ioreq,
struct dma_desc_mem *pdesc_mem,
uint32_t *uv_desc_index)
{
while ((l1 || l2) && cnt) {
if (l1) {
- l1 = crystalhd_reg_rd(hw->adp, MISC1_TX_FIRST_DESC_L_ADDR_LIST0);
+ l1 = crystalhd_reg_rd(hw->adp,
+ MISC1_TX_FIRST_DESC_L_ADDR_LIST0);
l1 &= DMA_START_BIT;
}
if (l2) {
- l2 = crystalhd_reg_rd(hw->adp, MISC1_TX_FIRST_DESC_L_ADDR_LIST1);
+ l2 = crystalhd_reg_rd(hw->adp,
+ MISC1_TX_FIRST_DESC_L_ADDR_LIST1);
l2 &= DMA_START_BIT;
}
return addr_entry;
}
-static bool crystalhd_rel_addr_to_pib_Q(struct crystalhd_hw *hw, uint32_t addr_to_rel)
+static bool crystalhd_rel_addr_to_pib_Q(struct crystalhd_hw *hw,
+ uint32_t addr_to_rel)
{
uint32_t Q_addr;
uint32_t r_offset, w_offset, n_offset;
return true;
}
-static void cpy_pib_to_app(struct c011_pib *src_pib, struct BC_PIC_INFO_BLOCK *dst_pib)
+static void cpy_pib_to_app(struct c011_pib *src_pib,
+ struct BC_PIC_INFO_BLOCK *dst_pib)
{
if (!src_pib || !dst_pib) {
BCMLOG_ERR("Invalid Arguments\n");
(uint32_t *)&src_pib);
if (src_pib.bFormatChange) {
- rx_pkt = (struct crystalhd_rx_dma_pkt *)crystalhd_dioq_fetch(hw->rx_freeq);
+ rx_pkt = (struct crystalhd_rx_dma_pkt *)
+ crystalhd_dioq_fetch(hw->rx_freeq);
if (!rx_pkt)
return;
rx_pkt->flags = 0;
- rx_pkt->flags |= COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE;
+ rx_pkt->flags |= COMP_FLAG_PIB_VALID |
+ COMP_FLAG_FMT_CHANGE;
AppPib = &rx_pkt->pib;
cpy_pib_to_app(&src_pib, AppPib);
rx_pkt->pib.pulldown,
rx_pkt->pib.ycom);
- crystalhd_dioq_add(hw->rx_rdyq, (void *)rx_pkt, true, rx_pkt->pkt_tag);
+ crystalhd_dioq_add(hw->rx_rdyq, (void *)rx_pkt, true,
+ rx_pkt->pkt_tag);
}
{
uint32_t dma_cntrl;
- dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
+ dma_cntrl = crystalhd_reg_rd(hw->adp,
+ MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
if (!(dma_cntrl & DMA_START_BIT)) {
dma_cntrl |= DMA_START_BIT;
- crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
+ crystalhd_reg_wr(hw->adp,
+ MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
}
- dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
+ dma_cntrl = crystalhd_reg_rd(hw->adp,
+ MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
if (!(dma_cntrl & DMA_START_BIT)) {
dma_cntrl |= DMA_START_BIT;
- crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
+ crystalhd_reg_wr(hw->adp,
+ MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
}
return;
uint32_t dma_cntrl = 0, count = 30;
uint32_t l0y = 1, l0uv = 1, l1y = 1, l1uv = 1;
- dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
+ dma_cntrl = crystalhd_reg_rd(hw->adp,
+ MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
if ((dma_cntrl & DMA_START_BIT)) {
dma_cntrl &= ~DMA_START_BIT;
- crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
+ crystalhd_reg_wr(hw->adp,
+ MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
}
- dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
+ dma_cntrl = crystalhd_reg_rd(hw->adp,
+ MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
if ((dma_cntrl & DMA_START_BIT)) {
dma_cntrl &= ~DMA_START_BIT;
- crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
+ crystalhd_reg_wr(hw->adp,
+ MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
}
/* Poll for 3seconds (30 * 100ms) on both the lists..*/
while ((l0y || l0uv || l1y || l1uv) && count) {
if (l0y) {
- l0y = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0);
+ l0y = crystalhd_reg_rd(hw->adp,
+ MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0);
l0y &= DMA_START_BIT;
if (!l0y)
hw->rx_list_sts[0] &= ~rx_waiting_y_intr;
}
if (l1y) {
- l1y = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1);
+ l1y = crystalhd_reg_rd(hw->adp,
+ MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1);
l1y &= DMA_START_BIT;
if (!l1y)
hw->rx_list_sts[1] &= ~rx_waiting_y_intr;
}
if (l0uv) {
- l0uv = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0);
+ l0uv = crystalhd_reg_rd(hw->adp,
+ MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0);
l0uv &= DMA_START_BIT;
if (!l0uv)
hw->rx_list_sts[0] &= ~rx_waiting_uv_intr;
}
if (l1uv) {
- l1uv = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1);
+ l1uv = crystalhd_reg_rd(hw->adp,
+ MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1);
l1uv &= DMA_START_BIT;
if (!l1uv)
hw->rx_list_sts[1] &= ~rx_waiting_uv_intr;
count, hw->rx_list_sts[0], hw->rx_list_sts[1]);
}
-static enum BC_STATUS crystalhd_hw_prog_rxdma(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *rx_pkt)
+static enum BC_STATUS crystalhd_hw_prog_rxdma(struct crystalhd_hw *hw,
+ struct crystalhd_rx_dma_pkt *rx_pkt)
{
uint32_t y_low_addr_reg, y_high_addr_reg;
uint32_t uv_low_addr_reg, uv_high_addr_reg;
}
spin_lock_irqsave(&hw->rx_lock, flags);
- /* FIXME: jarod: sts_free is an enum for 0, in crystalhd_hw.h... yuk... */
+ /* FIXME: jarod: sts_free is an enum for 0,
+ in crystalhd_hw.h... yuk... */
if (sts_free != hw->rx_list_sts[hw->rx_list_post_index]) {
spin_unlock_irqrestore(&hw->rx_lock, flags);
return BC_STS_BUSY;
hw->rx_list_post_index = (hw->rx_list_post_index + 1) % DMA_ENGINE_CNT;
spin_unlock_irqrestore(&hw->rx_lock, flags);
- crystalhd_dioq_add(hw->rx_actq, (void *)rx_pkt, false, rx_pkt->pkt_tag);
+ crystalhd_dioq_add(hw->rx_actq, (void *)rx_pkt, false,
+ rx_pkt->pkt_tag);
crystalhd_start_rx_dma_engine(hw);
/* Program the Y descriptor */
if (rx_pkt->uv_phy_addr) {
/* Program the UV descriptor */
desc_addr.full_addr = rx_pkt->uv_phy_addr;
- crystalhd_reg_wr(hw->adp, uv_high_addr_reg, desc_addr.high_part);
- crystalhd_reg_wr(hw->adp, uv_low_addr_reg, desc_addr.low_part | 0x01);
+ crystalhd_reg_wr(hw->adp, uv_high_addr_reg,
+ desc_addr.high_part);
+ crystalhd_reg_wr(hw->adp, uv_low_addr_reg,
+ desc_addr.low_part | 0x01);
}
return BC_STS_SUCCESS;
hw->stop_pending = 0;
- dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
+ dma_cntrl = crystalhd_reg_rd(hw->adp,
+ MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
if (dma_cntrl & DMA_START_BIT) {
dma_cntrl &= ~DMA_START_BIT;
- crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
+ crystalhd_reg_wr(hw->adp,
+ MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
}
- dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
+ dma_cntrl = crystalhd_reg_rd(hw->adp,
+ MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
if (dma_cntrl & DMA_START_BIT) {
dma_cntrl &= ~DMA_START_BIT;
- crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
+ crystalhd_reg_wr(hw->adp,
+ MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
}
hw->rx_list_post_index = 0;
crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm);
}
-static enum BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw, uint32_t list_index,
- enum BC_STATUS comp_sts)
+static enum BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw,
+ uint32_t list_index, enum BC_STATUS comp_sts)
{
struct crystalhd_rx_dma_pkt *rx_pkt = NULL;
uint32_t y_dw_dnsz, uv_dw_dnsz;
rx_pkt = crystalhd_dioq_find_and_fetch(hw->rx_actq,
hw->rx_pkt_tag_seed + list_index);
if (!rx_pkt) {
- BCMLOG_ERR("Act-Q:PostIx:%x L0Sts:%x L1Sts:%x current L:%x tag:%x comp:%x\n",
+ BCMLOG_ERR(
+ "Act-Q:PostIx:%x L0Sts:%x L1Sts:%x current L:%x tag:%x comp:%x\n",
hw->rx_list_post_index, hw->rx_list_sts[0],
hw->rx_list_sts[1], list_index,
hw->rx_pkt_tag_seed + list_index, comp_sts);
return crystalhd_hw_post_cap_buff(hw, rx_pkt);
}
-static bool crystalhd_rx_list0_handler(struct crystalhd_hw *hw, uint32_t int_sts,
- uint32_t y_err_sts, uint32_t uv_err_sts)
+static bool crystalhd_rx_list0_handler(struct crystalhd_hw *hw,
+ uint32_t int_sts, uint32_t y_err_sts, uint32_t uv_err_sts)
{
uint32_t tmp;
enum list_sts tmp_lsts;
tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK;
}
- if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) {
+ if (uv_err_sts &
+ MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) {
hw->rx_list_sts[0] &= ~rx_uv_mask;
hw->rx_list_sts[0] |= rx_uv_error;
tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK;
return (tmp_lsts != hw->rx_list_sts[0]);
}
-static bool crystalhd_rx_list1_handler(struct crystalhd_hw *hw, uint32_t int_sts,
- uint32_t y_err_sts, uint32_t uv_err_sts)
+static bool crystalhd_rx_list1_handler(struct crystalhd_hw *hw,
+ uint32_t int_sts, uint32_t y_err_sts, uint32_t uv_err_sts)
{
uint32_t tmp;
enum list_sts tmp_lsts;
/* Update States..*/
spin_lock_irqsave(&hw->rx_lock, flags);
if (i == 0)
- ret = crystalhd_rx_list0_handler(hw, intr_sts, y_err_sts, uv_err_sts);
+ ret = crystalhd_rx_list0_handler(hw, intr_sts,
+ y_err_sts, uv_err_sts);
else
- ret = crystalhd_rx_list1_handler(hw, intr_sts, y_err_sts, uv_err_sts);
+ ret = crystalhd_rx_list1_handler(hw, intr_sts,
+ y_err_sts, uv_err_sts);
if (ret) {
switch (hw->rx_list_sts[i]) {
case sts_free:
/* We got error on both or Y or uv. */
hw->stats.rx_errors++;
crystalhd_get_dnsz(hw, i, &y_dn_sz, &uv_dn_sz);
- /* FIXME: jarod: this is where my mini pci-e card is tripping up */
+ /* FIXME: jarod: this is where
+ my mini pci-e card is tripping up */
BCMLOG(BCMLOG_DBG, "list_index:%x rx[%d] Y:%x "
"UV:%x Int:%x YDnSz:%x UVDnSz:%x\n",
i, hw->stats.rx_errors, y_err_sts,
- uv_err_sts, intr_sts, y_dn_sz, uv_dn_sz);
+ uv_err_sts, intr_sts, y_dn_sz,
+ uv_dn_sz);
hw->rx_list_sts[i] = sts_free;
comp_sts = BC_STS_ERROR;
break;
union link_misc_perst_decoder_ctrl rst_cntrl_reg;
/* Pulse reset pin of 7412 (MISC_PERST_DECODER_CTRL) */
- rst_cntrl_reg.whole_reg = crystalhd_reg_rd(hw->adp, MISC_PERST_DECODER_CTRL);
+ rst_cntrl_reg.whole_reg = crystalhd_reg_rd(hw->adp,
+ MISC_PERST_DECODER_CTRL);
rst_cntrl_reg.bcm_7412_rst = 1;
- crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg);
+ crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL,
+ rst_cntrl_reg.whole_reg);
msleep_interruptible(50);
rst_cntrl_reg.bcm_7412_rst = 0;
- crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg);
+ crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL,
+ rst_cntrl_reg.whole_reg);
/* Close all banks, put DDR in idle */
bc_dec_reg_wr(hw->adp, SDRAM_PRECHARGE, 0);
**
*************************************************/
-enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp, void *buffer, uint32_t sz)
+enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp, void *buffer,
+ uint32_t sz)
{
uint32_t reg_data, cnt, *temp_buff;
uint32_t fw_sig_len = 36;
crystalhd_hw_proc_pib(hw);
bc_dec_reg_wr(adp, Stream2Host_Intr_Sts, deco_intr);
- /* FIXME: jarod: No udelay? might this be the real reason mini pci-e cards were stalling out? */
+ /* FIXME: jarod: No udelay? might this be
+ the real reason mini pci-e cards were stalling out? */
bc_dec_reg_wr(adp, Stream2Host_Intr_Sts, 0);
rc = 1;
}
return rc;
}
-enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *hw, struct crystalhd_adp *adp)
+enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *hw,
+ struct crystalhd_adp *adp)
{
if (!hw || !adp) {
BCMLOG_ERR("Invalid Arguments\n");
}
rpkt->desc_mem.pdma_desc_start = mem;
rpkt->desc_mem.phy_addr = phy_addr;
- rpkt->desc_mem.sz = BC_LINK_MAX_SGLS * sizeof(struct dma_descriptor);
+ rpkt->desc_mem.sz = BC_LINK_MAX_SGLS *
+ sizeof(struct dma_descriptor);
rpkt->pkt_tag = hw->rx_pkt_tag_seed + i;
crystalhd_hw_free_rx_pkt(hw, rpkt);
}
return BC_STS_SUCCESS;
}
-enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq,
+enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw,
+ struct crystalhd_dio_req *ioreq,
hw_comp_callback call_back,
wait_queue_head_t *cb_event, uint32_t *list_id,
uint8_t data_flags)
}
/* Get a list from TxFreeQ */
- tx_dma_packet = (struct tx_dma_pkt *)crystalhd_dioq_fetch(hw->tx_freeq);
+ tx_dma_packet = (struct tx_dma_pkt *)crystalhd_dioq_fetch(
+ hw->tx_freeq);
if (!tx_dma_packet) {
BCMLOG_ERR("No empty elements..\n");
return BC_STS_ERR_USAGE;
crystalhd_start_tx_dma_engine(hw);
crystalhd_reg_wr(hw->adp, first_desc_u_addr, desc_addr.high_part);
- crystalhd_reg_wr(hw->adp, first_desc_l_addr, desc_addr.low_part | 0x01);
+ crystalhd_reg_wr(hw->adp, first_desc_l_addr, desc_addr.low_part |
+ 0x01);
/* Be sure we set the valid bit ^^^^ */
return BC_STS_SUCCESS;
*
* FIX_ME: Not Tested the actual condition..
*/
-enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id)
+enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw,
+ uint32_t list_id)
{
if (!hw || !list_id) {
BCMLOG_ERR("Invalid Arguments\n");
}
enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw,
- struct crystalhd_dio_req *ioreq, bool en_post)
+ struct crystalhd_dio_req *ioreq, bool en_post)
{
struct crystalhd_rx_dma_pkt *rpkt;
uint32_t tag, uv_desc_ix = 0;
rpkt->dio_req = ioreq;
tag = rpkt->pkt_tag;
- sts = crystalhd_xlat_sgl_to_dma_desc(ioreq, &rpkt->desc_mem, &uv_desc_ix);
+ sts = crystalhd_xlat_sgl_to_dma_desc(ioreq, &rpkt->desc_mem,
+ &uv_desc_ix);
if (sts != BC_STS_SUCCESS)
return sts;
/* Store the address of UV in the rx packet for post*/
if (uv_desc_ix)
rpkt->uv_phy_addr = rpkt->desc_mem.phy_addr +
- (sizeof(struct dma_descriptor) * (uv_desc_ix + 1));
+ (sizeof(struct dma_descriptor) * (uv_desc_ix + 1));
if (en_post)
sts = crystalhd_hw_post_cap_buff(hw, rpkt);
rpkt = crystalhd_dioq_fetch_wait(hw->rx_rdyq, timeout, &sig_pending);
if (!rpkt) {
if (sig_pending) {
- BCMLOG(BCMLOG_INFO, "wait on frame time out %d\n", sig_pending);
+ BCMLOG(BCMLOG_INFO, "wait on frame time out %d\n",
+ sig_pending);
return BC_STS_IO_USER_ABORT;
} else {
return BC_STS_TIMEOUT;
return BC_STS_SUCCESS;
}
-void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats)
+void crystalhd_hw_stats(struct crystalhd_hw *hw,
+ struct crystalhd_hw_stats *stats)
{
if (!hw) {
BCMLOG_ERR("Invalid Arguments\n");
if (reg & 0x00020000) {
hw->prev_n = n;
- /* FIXME: jarod: outputting a random "C" is... confusing... */
+ /* FIXME: jarod: outputting
+ a random "C" is... confusing... */
BCMLOG(BCMLOG_INFO, "C");
return BC_STS_SUCCESS;
} else {
#define Cpu2HstMbx1 0x00100F04
#define MbxStat1 0x00100F08
#define Stream2Host_Intr_Sts 0x00100F24
-#define C011_RET_SUCCESS 0x0 /* Reutrn status of firmware command. */
+#define C011_RET_SUCCESS 0x0 /* Reutrn status of firmware command. */
/* TS input status register */
#define TS_StreamAFIFOStatus 0x0010044C
#define BC_FWIMG_ST_ADDR 0x00000000
/* FIXME: jarod: there's a kernel function that'll do this for us... */
#define rotr32_1(x, n) (((x) >> n) | ((x) << (32 - n)))
-#define bswap_32_1(x) ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00))
+#define bswap_32_1(x) ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00))
#define DecHt_HostSwReset 0x340000
#define BC_DRAM_FW_CFG_ADDR 0x001c2000
union link_misc_perst_deco_ctrl {
struct {
- uint32_t bcm7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/
+ uint32_t bcm7412_rst:1; /* 1 -> BCM7412 is held
+ in reset. Reset value 1.*/
uint32_t reserved0:3; /* Reserved.No Effect*/
- uint32_t stop_bcm_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/
+ uint32_t stop_bcm_7412_clk:1; /* 1 ->Stops branch of
+ 27MHz clk used to clk BCM7412*/
uint32_t reserved1:27; /* Reseved. No Effect*/
};
union link_misc_perst_clk_ctrl {
struct {
- uint32_t sel_alt_clk:1; /* When set, selects a 6.75MHz clock as the source of core_clk */
- uint32_t stop_core_clk:1; /* When set, stops the branch of core_clk that is not needed for low power operation */
- uint32_t pll_pwr_dn:1; /* When set, powers down the main PLL. The alternate clock bit should be set
- to select an alternate clock before setting this bit.*/
+ uint32_t sel_alt_clk:1; /* When set, selects a
+ 6.75MHz clock as the source of core_clk */
+ uint32_t stop_core_clk:1; /* When set, stops the branch
+ of core_clk that is not needed for low power operation */
+ uint32_t pll_pwr_dn:1; /* When set, powers down the
+ main PLL. The alternate clock bit should be set to
+ select an alternate clock before setting this bit.*/
uint32_t reserved0:5; /* Reserved */
- uint32_t pll_mult:8; /* This setting controls the multiplier for the PLL. */
- uint32_t pll_div:4; /* This setting controls the divider for the PLL. */
+ uint32_t pll_mult:8; /* This setting controls
+ the multiplier for the PLL. */
+ uint32_t pll_div:4; /* This setting controls
+ the divider for the PLL. */
uint32_t reserved1:12; /* Reserved */
};
union link_misc_perst_decoder_ctrl {
struct {
- uint32_t bcm_7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/
+ uint32_t bcm_7412_rst:1; /* 1 -> BCM7412 is held
+ in reset. Reset value 1.*/
uint32_t res0:3; /* Reserved.No Effect*/
- uint32_t stop_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/
+ uint32_t stop_7412_clk:1; /* 1 ->Stops branch of 27MHz
+ clk used to clk BCM7412*/
uint32_t res1:27; /* Reseved. No Effect */
};
* The virtual address will determine what should be freed.
*/
struct dma_desc_mem {
- struct dma_descriptor *pdma_desc_start; /* 32-bytes for dma descriptor. should be first element */
- dma_addr_t phy_addr; /* physical address of each DMA desc */
+ struct dma_descriptor *pdma_desc_start; /* 32-bytes for dma
+ descriptor. should be first element */
+ dma_addr_t phy_addr; /* physical address
+ of each DMA desc */
uint32_t sz;
- struct _dma_desc_mem_ *Next; /* points to Next Descriptor in chain */
+ struct _dma_desc_mem_ *Next; /* points to Next Descriptor in chain */
};
#define CLOCK_PRESET 175
/* DMA engine register BIT mask wrappers.. */
-#define DMA_START_BIT MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK
-
-#define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \
- INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \
- INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \
- INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \
- INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \
- INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \
- INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \
- INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK)
-
-#define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \
- MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \
- MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \
- MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK)
-
-#define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \
- MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \
- MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \
- MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK)
-
-#define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \
- MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \
- MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \
- MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK)
-
-#define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \
- MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \
- MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \
- MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK)
+#define DMA_START_BIT MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK
+
+#define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \
+ INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \
+ INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \
+ INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \
+ INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \
+ INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \
+ INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \
+ INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK)
+
+#define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \
+ MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \
+ MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \
+ MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK)
+
+#define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \
+ MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \
+ MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \
+ MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK)
+
+#define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \
+ MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \
+ MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \
+ MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK)
+
+#define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \
+ MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \
+ MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \
+ MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK)
/**** API Exposed to the other layers ****/
enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp,
void *buffer, uint32_t sz);
-enum BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw, struct BC_FW_CMD *fw_cmd);
-bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, struct crystalhd_hw *hw);
-enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *, struct crystalhd_adp *);
+enum BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw,
+ struct BC_FW_CMD *fw_cmd);
+bool crystalhd_hw_interrupt(struct crystalhd_adp *adp,
+ struct crystalhd_hw *hw);
+enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *,
+ struct crystalhd_adp *);
enum BC_STATUS crystalhd_hw_close(struct crystalhd_hw *);
enum BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *);
enum BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *);
-enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq,
+enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw,
+ struct crystalhd_dio_req *ioreq,
hw_comp_callback call_back,
wait_queue_head_t *cb_event,
uint32_t *list_id, uint8_t data_flags);
enum BC_STATUS crystalhd_hw_pause(struct crystalhd_hw *hw);
enum BC_STATUS crystalhd_hw_unpause(struct crystalhd_hw *hw);
enum BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw);
-enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id);
+enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw,
+ uint32_t list_id);
enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw,
- struct crystalhd_dio_req *ioreq, bool en_post);
+ struct crystalhd_dio_req *ioreq, bool en_post);
enum BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw,
struct BC_PIC_INFO_BLOCK *pib,
struct crystalhd_dio_req **ioreq);
enum BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw);
enum BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw);
-void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats);
+void crystalhd_hw_stats(struct crystalhd_hw *hw,
+ struct crystalhd_hw_stats *stats);
/* API to program the core clock on the decoder */
enum BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *);
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