* SuperHCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
- * @name: The name.
* @pvr: Processor Version Register
* @prr: Processor Revision Register
* @cvr: Cache Version Register
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
- const char *name;
uint32_t pvr;
uint32_t prr;
uint32_t cvr;
static void superh_cpu_list_entry(gpointer data, gpointer user_data)
{
- ObjectClass *oc = data;
- SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
SuperHCPUListState *s = user_data;
+ const char *typename = object_class_get_name(OBJECT_CLASS(data));
+ int len = strlen(typename) - strlen(SUPERH_CPU_TYPE_SUFFIX);
- (*s->cpu_fprintf)(s->file, "%s\n",
- scc->name);
+ (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename);
}
void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
- scc->name = "SH7750R";
scc->pvr = 0x00050000;
scc->prr = 0x00000100;
scc->cvr = 0x00110000;
{
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
- scc->name = "SH7751R";
scc->pvr = 0x04050005;
scc->prr = 0x00000113;
scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
{
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
- scc->name = "SH7785";
scc->pvr = 0x10300700;
scc->prr = 0x00000200;
scc->cvr = 0x71440211;