PR 10924

        * arm-dis.c (print_insn_arm): Mark insns that use the PC in
        post-indexed addressing as unpredictable.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7ecb512..9e2dfbd 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2009-12-09  Nick Clifton  <nickc@redhat.com>
+
+       PR 10924
+       * arm-dis.c (print_insn_arm): Mark insns that use the PC in
+       post-indexed addressing as unpredictable.
+
 2009-12-03  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-dis.c (FXSAVE_Fixup): New.

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index a871d23..3bfad52 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2931,11 +2931,17 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
                                      NEGATIVE_BIT_SET ? "-" : "",
                                      arm_regnames[given & 0xf]);
 
-                             /* Writeback is automatically implied by post- addressing.
-                                Setting the W bit is unnecessary and ARM specify it as
-                                being unpredictable.  */
-                             if (WRITEBACK_BIT_SET && ! allow_unpredictable)
-                               func (stream, UNPREDICTABLE_INSTRUCTION);
+                             if (! allow_unpredictable)
+                               {
+                                 /* Writeback is automatically implied by post- addressing.
+                                    Setting the W bit is unnecessary and ARM specify it as
+                                    being unpredictable.  */
+                                 if (WRITEBACK_BIT_SET
+                                     /* Specifying the PC register as the post-indexed
+                                        registers is also unpredictable.  */
+                                     || ((given & 0xf) == 0xf))
+                                   func (stream, UNPREDICTABLE_INSTRUCTION);
+                               }
                            }
                        }
                      break;