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ASoC: SOF: rename cores_mask to host_managed_cores_mask
authorRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Thu, 10 Sep 2020 16:41:22 +0000 (19:41 +0300)
committerMark Brown <broonie@kernel.org>
Fri, 11 Sep 2020 14:29:29 +0000 (15:29 +0100)
Rename the cores_mask in struct sof_intel_dsp_desc to
host_managed_cores_mask to be more indicative of the fact that
only these cores can be powered up/down by the host.

Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@linux.intel.com>
Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Reviewed-by: Keyon Jie <yang.jie@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Link: https://lore.kernel.org/r/20200910164125.2033062-2-kai.vehmanen@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sof/intel/apl.c
sound/soc/sof/intel/bdw.c
sound/soc/sof/intel/byt.c
sound/soc/sof/intel/cnl.c
sound/soc/sof/intel/hda-dsp.c
sound/soc/sof/intel/hda-loader.c
sound/soc/sof/intel/hda.c
sound/soc/sof/intel/shim.h
sound/soc/sof/intel/tgl.c

index 9e29d4f..25d3f57 100644 (file)
@@ -129,7 +129,7 @@ const struct sof_intel_dsp_desc apl_chip_info = {
        /* Apollolake */
        .cores_num = 2,
        .init_core_mask = 1,
-       .cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
+       .host_managed_cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
        .ipc_req = HDA_DSP_REG_HIPCI,
        .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
        .ipc_ack = HDA_DSP_REG_HIPCIE,
index 99fd0bd..50a4a73 100644 (file)
@@ -655,7 +655,7 @@ EXPORT_SYMBOL_NS(sof_bdw_ops, SND_SOC_SOF_BROADWELL);
 
 const struct sof_intel_dsp_desc bdw_chip_info = {
        .cores_num = 1,
-       .cores_mask = 1,
+       .host_managed_cores_mask = 1,
 };
 EXPORT_SYMBOL_NS(bdw_chip_info, SND_SOC_SOF_BROADWELL);
 
index 49f67f1..186736e 100644 (file)
@@ -651,7 +651,7 @@ EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD);
 
 const struct sof_intel_dsp_desc tng_chip_info = {
        .cores_num = 1,
-       .cores_mask = 1,
+       .host_managed_cores_mask = 1,
 };
 EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD);
 
@@ -896,7 +896,7 @@ EXPORT_SYMBOL_NS(sof_byt_ops, SND_SOC_SOF_BAYTRAIL);
 
 const struct sof_intel_dsp_desc byt_chip_info = {
        .cores_num = 1,
-       .cores_mask = 1,
+       .host_managed_cores_mask = 1,
 };
 EXPORT_SYMBOL_NS(byt_chip_info, SND_SOC_SOF_BAYTRAIL);
 
@@ -976,7 +976,7 @@ EXPORT_SYMBOL_NS(sof_cht_ops, SND_SOC_SOF_BAYTRAIL);
 
 const struct sof_intel_dsp_desc cht_chip_info = {
        .cores_num = 1,
-       .cores_mask = 1,
+       .host_managed_cores_mask = 1,
 };
 EXPORT_SYMBOL_NS(cht_chip_info, SND_SOC_SOF_BAYTRAIL);
 
index 70f14b2..51e336d 100644 (file)
@@ -334,7 +334,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
        /* Cannonlake */
        .cores_num = 4,
        .init_core_mask = 1,
-       .cores_mask = HDA_DSP_CORE_MASK(0) |
+       .host_managed_cores_mask = HDA_DSP_CORE_MASK(0) |
                                HDA_DSP_CORE_MASK(1) |
                                HDA_DSP_CORE_MASK(2) |
                                HDA_DSP_CORE_MASK(3),
@@ -353,7 +353,7 @@ const struct sof_intel_dsp_desc icl_chip_info = {
        /* Icelake */
        .cores_num = 4,
        .init_core_mask = 1,
-       .cores_mask = HDA_DSP_CORE_MASK(0) |
+       .host_managed_cores_mask = HDA_DSP_CORE_MASK(0) |
                                HDA_DSP_CORE_MASK(1) |
                                HDA_DSP_CORE_MASK(2) |
                                HDA_DSP_CORE_MASK(3),
@@ -372,7 +372,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
        /* Elkhartlake */
        .cores_num = 4,
        .init_core_mask = 1,
-       .cores_mask = HDA_DSP_CORE_MASK(0),
+       .host_managed_cores_mask = HDA_DSP_CORE_MASK(0),
        .ipc_req = CNL_DSP_REG_HIPCIDR,
        .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
        .ipc_ack = CNL_DSP_REG_HIPCIDA,
@@ -388,7 +388,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
        /* Jasperlake */
        .cores_num = 2,
        .init_core_mask = 1,
-       .cores_mask = HDA_DSP_CORE_MASK(0) |
+       .host_managed_cores_mask = HDA_DSP_CORE_MASK(0) |
                                HDA_DSP_CORE_MASK(1),
        .ipc_req = CNL_DSP_REG_HIPCIDR,
        .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
index ed4d65a..18d7266 100644 (file)
@@ -610,7 +610,7 @@ static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
 #endif
 
        /* power down DSP */
-       ret = hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
+       ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
        if (ret < 0) {
                dev_err(sdev->dev,
                        "error: failed to power down core during suspend\n");
index 7072749..713ebe8 100644 (file)
@@ -91,7 +91,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
        int i;
 
        /* step 1: power up corex */
-       ret = hda_dsp_core_power_up(sdev, chip->cores_mask);
+       ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
        if (ret < 0) {
                if (iteration == HDA_FW_BOOT_ATTEMPTS)
                        dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
@@ -147,7 +147,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
 
        /* step 5: power down corex */
        ret = hda_dsp_core_power_down(sdev,
-                                 chip->cores_mask & ~(HDA_DSP_CORE_MASK(0)));
+                                 chip->host_managed_cores_mask & ~(HDA_DSP_CORE_MASK(0)));
        if (ret < 0) {
                if (iteration == HDA_FW_BOOT_ATTEMPTS)
                        dev_err(sdev->dev,
@@ -176,7 +176,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
 
 err:
        hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
-       hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
+       hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
 
        return ret;
 }
index de8e859..8825271 100644 (file)
@@ -928,7 +928,7 @@ int hda_dsp_remove(struct snd_sof_dev *sdev)
 
        /* disable cores */
        if (chip)
-               hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
+               hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
 
        /* disable DSP */
        snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
index 6fe8b00..1e0afb5 100644 (file)
 /* DSP hardware descriptor */
 struct sof_intel_dsp_desc {
        int cores_num;
-       int cores_mask;
+       int host_managed_cores_mask;
        int init_core_mask; /* cores available after fw boot */
        int ipc_req;
        int ipc_req_mask;
index d0e84b7..8f3fe82 100644 (file)
@@ -124,7 +124,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
        /* Tigerlake */
        .cores_num = 4,
        .init_core_mask = 1,
-       .cores_mask = HDA_DSP_CORE_MASK(0),
+       .host_managed_cores_mask = HDA_DSP_CORE_MASK(0),
        .ipc_req = CNL_DSP_REG_HIPCIDR,
        .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
        .ipc_ack = CNL_DSP_REG_HIPCIDA,