sdram fifo ready

diff --git a/tools/qt_proj_test5/qt_proj_test5.vhd b/tools/qt_proj_test5/qt_proj_test5.vhd
index 730b9a7..6bcd4e7 100644 (file)
--- a/tools/qt_proj_test5/qt_proj_test5.vhd
+++ b/tools/qt_proj_test5/qt_proj_test5.vhd
@@ -52,6 +52,7 @@ entity qt_proj_test5 is
         signal dbg_f_cnt            : out std_logic_vector(7 downto 0);\r
         signal dbg_f_rd, dbg_f_wr, dbg_f_emp, dbg_f_ful \r
                                     : out std_logic;\r
+        signal dbg_bst_cnt          : out std_logic_vector(7 downto 0);\r
         \r
         base_clk       : in std_logic;\r
         base_clk_27mhz         : in std_logic;\r
@@ -130,6 +131,7 @@ component vga_ctl
         signal dbg_f_cnt            : out std_logic_vector(7 downto 0);\r
         signal dbg_f_rd, dbg_f_wr, dbg_f_emp, dbg_f_ful \r
                                     : out std_logic;\r
+        signal dbg_bst_cnt          : out std_logic_vector(7 downto 0);\r
 \r
             ppu_clk     : in std_logic;\r
             sdram_clk   : in std_logic;\r
@@ -299,6 +301,7 @@ begin
         dbg_f_out            ,\r
         dbg_f_cnt            ,\r
         dbg_f_rd, dbg_f_wr, dbg_f_emp, dbg_f_ful ,\r
+        dbg_bst_cnt          ,\r
 \r
             ppu_clk     ,\r
             sdram_clk,\r

diff --git a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
index c57475d..57c8798 100644 (file)
--- a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
+++ b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
@@ -41,14 +41,14 @@ sim:/testbench_qt_proj_test5/sim_board/dbg_vga_y
 #sim:/testbench_qt_proj_test5/sim_board/dbg_nes_x_old        \\r
 \r
 add wave -divider fifo\r
+add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_f_wr\r
 add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_f_in             \r
+add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_f_rd\r
 add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_f_out            \r
 add wave -radix decimal -unsigned sim:/testbench_qt_proj_test5/sim_board/dbg_f_cnt           \r
-add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_f_rd\r
-add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_f_wr\r
+add wave -radix decimal -unsigned sim:/testbench_qt_proj_test5/sim_board/dbg_bst_cnt          \r
 add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_f_emp\r
 add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_f_ful \r
-\r
 add wave -radix decimal -unsigned sim:/testbench_qt_proj_test5/sim_board/dbg_sw_state     \r
 \r
 add wave -divider sdram_ctl\r

diff --git a/tools/qt_proj_test5/testbench_qt_proj_test5.vhd b/tools/qt_proj_test5/testbench_qt_proj_test5.vhd
index 0ca5efb..1450bc9 100644 (file)
--- a/tools/qt_proj_test5/testbench_qt_proj_test5.vhd
+++ b/tools/qt_proj_test5/testbench_qt_proj_test5.vhd
@@ -51,6 +51,7 @@ architecture stimulus of testbench_qt_proj_test5 is
         signal dbg_f_cnt            : out std_logic_vector(7 downto 0);
         signal dbg_f_rd, dbg_f_wr, dbg_f_emp, dbg_f_ful 
                                     : out std_logic;
+        signal dbg_bst_cnt          : out std_logic_vector(7 downto 0);
 
         base_clk       : in std_logic;
         base_clk_27mhz         : in std_logic;
@@ -157,6 +158,7 @@ architecture stimulus of testbench_qt_proj_test5 is
     signal dbg_f_cnt            : std_logic_vector(7 downto 0);
     signal dbg_f_rd, dbg_f_wr, dbg_f_emp, dbg_f_ful 
                                     : std_logic;
+    signal dbg_bst_cnt          : std_logic_vector(7 downto 0);
 
 begin
 
@@ -202,6 +204,7 @@ begin
     dbg_f_out            ,
     dbg_f_cnt            ,
     dbg_f_rd, dbg_f_wr, dbg_f_emp, dbg_f_ful ,
+       dbg_bst_cnt          ,
     
     base_clk, base_clk_27mhz, reset_input, 
         h_sync_n    ,

diff --git a/tools/qt_proj_test5/vga.vhd b/tools/qt_proj_test5/vga.vhd
index 1bdbb58..50f5b63 100644 (file)
--- a/tools/qt_proj_test5/vga.vhd
+++ b/tools/qt_proj_test5/vga.vhd
@@ -24,6 +24,7 @@ entity vga_ctl is
             signal dbg_f_cnt            : out std_logic_vector(7 downto 0);\r
             signal dbg_f_rd, dbg_f_wr, dbg_f_emp, dbg_f_ful \r
                                         : out std_logic;\r
+            signal dbg_bst_cnt          : out std_logic_vector(7 downto 0);\r
     \r
             ppu_clk     : in std_logic;
             sdram_clk   : in std_logic;\r
@@ -153,6 +154,8 @@ signal f_cnt            : std_logic_vector(7 downto 0);
 signal sdram_write_addr         :   std_logic_vector (21 downto 0);\r
 signal sdram_addr_inc_n         :   std_logic;\r
 signal sdram_addr_res_n         :   std_logic;\r
+signal bst_wr_cnt               :   std_logic_vector (7 downto 0);\r
+signal bst_wr_cnt_we_n          :   std_logic;\r
 \r
 signal f_rd, f_wr, f_emp, f_ful \r
                         : std_logic;\r
@@ -161,7 +164,8 @@ constant sw_idle        : std_logic_vector(2 downto 0) := "000";
 constant sw_pop_fifo    : std_logic_vector(2 downto 0) := "001";\r
 constant sw_write       : std_logic_vector(2 downto 0) := "010";\r
 constant sw_write_ack   : std_logic_vector(2 downto 0) := "011";\r
-constant sw_write_burst : std_logic_vector(2 downto 0) := "100";\r
+constant sw_write_burst1 : std_logic_vector(2 downto 0) := "100";\r
+constant sw_write_burst2 : std_logic_vector(2 downto 0) := "101";\r
 \r
 signal sw_state         : std_logic_vector(2 downto 0);\r
 \r
@@ -184,9 +188,9 @@ begin
     dbg_sw_state     <= sw_state     ;\r
 \r
     dbg_f_in             <= f_in             ;\r
-    --dbg_f_out            <= f_val            ;\r
     dbg_f_out            <= f_out            ;\r
     dbg_f_cnt            <= f_cnt            ;\r
+    dbg_bst_cnt          <= bst_wr_cnt            ;\r
     dbg_f_rd             <= f_rd             ;\r
     dbg_f_wr             <= f_wr             ;\r
     dbg_f_emp            <= f_emp            ;\r
@@ -216,21 +220,18 @@ begin
     pos_x_old_inst: d_flip_flop generic map (9)\r
         port map (sdram_clk_n, rst_n, '1', pos_x_we_n, pos_x, pos_x_old);\r
 \r
---    mem_cnt_inst : counter_register generic map (5, 1)\r
---            port map (sdram_clk , x_res_n, '0', '1', (others => '0'), mem_cnt);\r
-\r
     dram_rd_inst : d_flip_flop generic map (16)\r
         port map (sdram_clk, rst_n, '1', dram_col_we_n, wbs_dat_o, dram_col);\r
 \r
     fifo_inst : sdram_write_fifo port map\r
         (rst, sdram_clk_n, f_in, f_rd, f_wr, f_emp, f_ful, f_out, f_cnt);\r
         \r
---    fifo_data_inst: d_flip_flop generic map (12)\r
---        port map (sdram_clk, rst_n, '1', f_val_we_n, f_out, f_val);\r
-        \r
     sdram_wr_addr_inst : counter_register generic map (22, 1)\r
             port map (sdram_clk, sdram_addr_res_n, sdram_addr_inc_n, '1', (others => '0'), sdram_write_addr);\r
 \r
+    fifo_bst_wr_cnt : counter_register generic map (8, 255)\r
+            port map (sdram_clk, sdram_addr_res_n, sdram_addr_inc_n, bst_wr_cnt_we_n, f_cnt, bst_wr_cnt);\r
+\r
     pos_x_p : process (rst_n, sdram_clk)\r
     begin\r
         if (rst_n = '0') then\r
@@ -287,24 +288,35 @@ begin
                 or vga_y >= conv_std_logic_vector(VGA_H, 10)) then\r
                 --write to sdram status\r
                 case sw_state is\r
-                when sw_idle =>\r
-                    if (f_cnt = "00000000") then\r
+                when sw_idle =>         --0: idle...\r
+                    if (f_emp = '1') then\r
                         sw_state <= sw_idle;\r
                     else\r
                         sw_state <= sw_pop_fifo;\r
                     end if;\r
                 \r
-                when sw_pop_fifo =>\r
+                when sw_pop_fifo =>     --1: initialize writing...\r
                     sw_state <= sw_write;\r
 \r
-                when sw_write =>\r
+                when sw_write =>        --2: start writing\r
                     sw_state <= sw_write_ack;\r
                     \r
-                when sw_write_ack =>\r
-                    sw_state <= sw_write_burst;\r
+                when sw_write_ack =>    --3: push first data\r
+                    sw_state <= sw_write_burst1;\r
 \r
-                when sw_write_burst =>\r
-                    sw_state <= sw_idle;\r
+                when sw_write_burst1 =>  --4-1: repeat...\r
+                    if (bst_wr_cnt(7 downto 1) = "0000000") then -- case 0 or 1\r
+                        sw_state <= sw_idle;\r
+                    else\r
+                        sw_state <= sw_write_burst2;\r
+                    end if;\r
+\r
+                when sw_write_burst2 =>  --4-2: repeat...\r
+                    if (bst_wr_cnt(7 downto 1) = "0000000") then -- case 0 or 1\r
+                        sw_state <= sw_idle;\r
+                    else\r
+                        sw_state <= sw_write_burst2;\r
+                    end if;\r
                 \r
                 when others =>\r
                     sw_state <= sw_idle;\r
@@ -316,24 +328,20 @@ begin
         end if;\r
     end process;\r
 \r
-    fifo_r_p : process (sw_state)\r
-    begin\r
-        case sw_state is\r
-        when sw_pop_fifo =>\r
-            f_rd <= '1';\r
-        when others =>\r
-            f_rd <= '0';\r
-        end case;\r
-    end process;\r
+    f_rd <= '0' when rst_n = '0' else\r
+            '1' when (sw_state = sw_pop_fifo or sw_state = sw_write_burst2) else\r
+            '0';\r
 \r
     sdram_addr_res_n <= rst_n;\r
     sdram_addr_inc_n <= '1' when rst_n = '0' else\r
-                        '0' when sw_state = sw_write_burst else\r
+                        '0' when (sw_state(2) = '1') else --case sw_write_burst1 or sw_write_burst2\r
                         '1';\r
+    bst_wr_cnt_we_n <= '1' when rst_n = '0' else\r
+                       '0' when sw_state = sw_pop_fifo else\r
+                       '1';\r
     wbs_adr_i <= sdram_write_addr;\r
     wbs_dat_i <= "0000" & f_out;\r
-\r
-    wbs_tga_i <= "11111111";\r
+    wbs_tga_i <= bst_wr_cnt;\r
     wbs_cyc_i <= '0' when rst_n = '0' else\r
                  '1' when sw_state >= sw_write else\r
                  '0';\r
@@ -341,7 +349,7 @@ begin
                  '1' when sw_state >= sw_write else\r
                  '0';\r
     wbs_we_i  <= '0' when rst_n = '0' else\r
-                 '1' when sw_state = sw_write else\r
+                 '1' when sw_state >= sw_write else\r
                  '0';\r
 \r
     ----------- vga position conversion 640 to 256\r

diff --git a/tools/qt_proj_test5/vga_clk_gen.vhd b/tools/qt_proj_test5/vga_clk_gen.vhd
index 3da7384..40a173d 100644 (file)
--- a/tools/qt_proj_test5/vga_clk_gen.vhd
+++ b/tools/qt_proj_test5/vga_clk_gen.vhd
@@ -148,9 +148,9 @@ BEGIN
                clk0_duty_cycle => 50,\r
                clk0_multiply_by => 1,\r
                clk0_phase_shift => "0",\r
-               clk1_divide_by => 1,\r
+               clk1_divide_by => 2,\r
                clk1_duty_cycle => 50,\r
-               clk1_multiply_by => 2,\r
+               clk1_multiply_by => 3,\r
                clk1_phase_shift => "0",\r
                compensate_clock => "CLK0",\r
                gate_lock_signal => "NO",\r
@@ -238,7 +238,7 @@ END SYN;
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"\r
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"\r
 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"\r
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"\r
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "75.000000"\r
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"\r
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"\r
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"\r
@@ -267,7 +267,7 @@ END SYN;
 -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"\r
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"\r
 -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"\r
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"\r
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "75.00000000"\r
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"\r
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"\r
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"\r
@@ -317,9 +317,9 @@ END SYN;
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"\r
 -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"\r
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"\r
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"\r
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"\r
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"\r
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"\r
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "3"\r
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"\r
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"\r
 -- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"\r