vram_p : process (cpu_clk, rst_n)\r
use ieee.std_logic_arith.conv_std_logic_vector;\r
variable init_step_cnt, plt_step_cnt, \r
- nt_step_cnt, enable_ppu_step_cnt : integer;\r
+ nt_step_cnt, spr_step_cnt, enable_ppu_step_cnt : integer;\r
variable init_done : std_logic;\r
variable global_step_cnt : integer;\r
\r
init_step_cnt := 0;\r
plt_step_cnt := 0;\r
nt_step_cnt := 0;\r
+ spr_step_cnt := 0;\r
enable_ppu_step_cnt := 0;\r
\r
elsif (rising_edge(cpu_clk)) then\r
\r
elsif (plt_step_cnt = 4) then\r
--set palette data\r
- ppu_set(16#2007#, 16#0f#);\r
+ ppu_set(16#2007#, 16#11#);\r
elsif (plt_step_cnt = 6) then\r
- ppu_set(16#2007#, 16#00#);\r
+ ppu_set(16#2007#, 16#01#);\r
elsif (plt_step_cnt = 8) then\r
- ppu_set(16#2007#, 16#10#);\r
+ ppu_set(16#2007#, 16#03#);\r
elsif (plt_step_cnt = 10) then\r
- ppu_set(16#2007#, 16#20#);\r
+ ppu_set(16#2007#, 16#13#);\r
\r
elsif (plt_step_cnt = 12) then\r
ppu_set(16#2007#, 16#0f#);\r
ppu_set(16#2007#, 16#28#);\r
\r
elsif (plt_step_cnt = 28) then\r
- ppu_set(16#2007#, 16#0f#);\r
+ ppu_set(16#2007#, 16#05#);\r
elsif (plt_step_cnt = 30) then\r
ppu_set(16#2007#, 16#0c#);\r
elsif (plt_step_cnt = 32) then\r
elsif (global_step_cnt = 2) then\r
--step1 = name table set.\r
if (nt_step_cnt = 0) then\r
- --set vram addr 2004 (first row, 4th col)\r
+ --set vram addr 2006 (first row, 6th col)\r
ppu_set(16#2006#, 16#20#);\r
elsif (nt_step_cnt = 2) then\r
- ppu_set(16#2006#, 16#04#);\r
+ ppu_set(16#2006#, 16#06#);\r
elsif (nt_step_cnt = 4) then\r
--set name tbl data\r
--0x44, 45, 45 = DEE\r
elsif (nt_step_cnt = 30) then\r
ppu_set(16#2007#, 16#21#);\r
\r
+ elsif (nt_step_cnt = 32) then\r
+ --set vram addr 23c1\r
+ ppu_set(16#2006#, 16#23#);\r
+ elsif (nt_step_cnt = 34) then\r
+ ppu_set(16#2006#, 16#c1#);\r
+ elsif (nt_step_cnt = 36) then\r
+ --attr=11011000\r
+ ppu_set(16#2007#, 16#d8#);\r
+\r
else\r
ppu_clr;\r
- if (nt_step_cnt > 30) then\r
+ if (nt_step_cnt > 36) then\r
global_step_cnt := global_step_cnt + 1;\r
end if;\r
end if;\r
nt_step_cnt := nt_step_cnt + 1;\r
\r
+ elsif (global_step_cnt = 2) then\r
+ --step2 = sprite set.\r
+ if (spr_step_cnt = 0) then\r
+ --set sprite addr=00\r
+ ppu_set(16#2003#, 16#00#);\r
+ elsif (spr_step_cnt = 2) then\r
+ --set sprite data: y=01\r
+ ppu_set(16#2004#, 16#01#);\r
+ elsif (spr_step_cnt = 4) then\r
+ --tile=0x4d (ascii 'M')\r
+ ppu_set(16#2004#, 16#4d#);\r
+ elsif (spr_step_cnt = 6) then\r
+ --set sprite attr=00\r
+ ppu_set(16#2004#, 16#00#);\r
+ elsif (spr_step_cnt = 8) then\r
+ --set sprite data: x=39\r
+ ppu_set(16#2004#, 16#27#);\r
+ else\r
+ ppu_clr;\r
+ if (spr_step_cnt > 8) then\r
+ global_step_cnt := global_step_cnt + 1;\r
+ end if;\r
+ end if;\r
+ spr_step_cnt := spr_step_cnt + 1;\r
+\r
elsif (global_step_cnt = 3) then\r
--final step = enable ppu.\r
if (enable_ppu_step_cnt = 0) then\r
--show bg\r
--PPUMASK=1e (show bg and sprite)\r
--PPUMASK=0e (show bg only)\r
- ppu_set(16#2001#, 16#0e#);\r
+ ppu_set(16#2001#, 16#1e#);\r
elsif (enable_ppu_step_cnt = 2) then\r
--show enable nmi\r
--PPUCTRL=80\r
& prf_x(dsize - 1 downto 3);\r
vram_addr(asize - 1 downto 10) <= "10" & ppu_ctrl(PPUBNA downto 0) \r
+ ("000" & prf_x(dsize));\r
- end if;\r
- if (prf_x (2 downto 0) = "010") then\r
- nt_we_n <= '0';\r
- else\r
- nt_we_n <= '1';\r
- end if;\r
-\r
- --TODO must load 8 cycle each for the first two tiles!!!\r
----fetch attr table byte.\r
- if (prf_x (4 downto 0) = "00011") then\r
+ elsif (prf_x (4 downto 0) = "00011") then\r
--attribute table is loaded every 32 cycle.\r
--attr table at 0x23c0\r
vram_addr(dsize - 1 downto 0) <= "11000000" +\r
vram_addr(asize - 1 downto dsize) <= "10" &\r
ppu_ctrl(PPUBNA downto 0) & "11"\r
+ ("000" & prf_x(dsize) & "00");\r
+ ----fetch pattern table low byte.\r
+ elsif (prf_x (2 downto 0) = "101") then\r
+ --vram addr is incremented every 8 cycle.\r
+ vram_addr <= "0" & ppu_ctrl(PPUBPA) & \r
+ disp_nt(dsize - 1 downto 0) \r
+ & "0" & prf_y(2 downto 0);\r
+ ----fetch pattern table high byte.\r
+ elsif (prf_x (2 downto 0) = "111") then\r
+ --vram addr is incremented every 8 cycle.\r
+ vram_addr <= "0" & ppu_ctrl(PPUBPA) & \r
+ disp_nt(dsize - 1 downto 0) \r
+ & "0" & prf_y(2 downto 0) + "00000000001000";\r
+ end if;\r
+\r
+\r
+\r
+ ----fetch next tile byte.\r
+ if (prf_x (2 downto 0) = "010") then\r
+ nt_we_n <= '0';\r
+ else\r
+ nt_we_n <= '1';\r
end if;\r
+\r
+ ----fetch attr table byte.\r
if (prf_x (4 downto 0) = "00100") then\r
attr_we_n <= '0';\r
else\r
else\r
attr_ce_n <= '1';\r
end if;\r
- \r
- ----fetch pattern table low byte.\r
- if (prf_x (2 downto 0) = "101") then\r
- --vram addr is incremented every 8 cycle.\r
- vram_addr <= "0" & ppu_ctrl(PPUBPA) & \r
- disp_nt(dsize - 1 downto 0) \r
- & "0" & prf_y(2 downto 0);\r
- end if;\r
- if (prf_x (2 downto 0) = "110") then\r
- ptn_l_we_n <= '0';\r
- else\r
- ptn_l_we_n <= '1';\r
- end if;\r
\r
- ----fetch pattern table high byte.\r
- if (prf_x (2 downto 0) = "111") then\r
- --vram addr is incremented every 8 cycle.\r
- vram_addr <= "0" & ppu_ctrl(PPUBPA) & \r
- disp_nt(dsize - 1 downto 0) \r
- & "0" & prf_y(2 downto 0) + "00000000001000";\r
- end if;\r
- if (prf_x (2 downto 0) = "000") then\r
- ptn_h_we_n <= '0';\r
- else\r
- ptn_h_we_n <= '1';\r
- end if;\r
+ ----fetch pattern table low byte.\r
+ if (prf_x (2 downto 0) = "110") then\r
+ ptn_l_we_n <= '0';\r
+ else\r
+ ptn_l_we_n <= '1';\r
+ end if;\r
+\r
+ ----fetch pattern table high byte.\r
+ if (prf_x (2 downto 0) = "000") then\r
+ ptn_h_we_n <= '0';\r
+ else\r
+ ptn_h_we_n <= '1';\r
+ end if;\r
\r
end if;--if (ppu_mask(PPUSBG) = '1') and\r
\r