val |= vsync ? STAT_VSYNC : 0;
//val |= (cmd_fifo->empty()) ? STAT_EMPTY : 0;
val |= STAT_EMPTY;
+ //val |= ((cmd_ready) ? STAT_EMPTY : 0);
val |= (cmd_fifo->full()) ? STAT_FULL : 0;
val |= (!(fo->empty())) ? STAT_DRDY : 0;
// clear busy stat
{
if(!first_load) {
write_vram(before_addr, cache_val);
- wrote_bytes++;
+ //wrote_bytes++;
}
first_load = true;
before_addr = 0xffffffff;
if((first_load) || (addr != before_addr)) {
if(!(first_load)) {
write_vram(before_addr, cache_val);
- wrote_bytes++;
+ //wrote_bytes++;
}
cache_val = read_vram(addr);
} else if((x < 0) || (y < 0) || (x >= (width << 3)) || (y >= height)) {
bit = 1 << (x & 7);
}
uint8_t cur = cache_val;
+ wrote_bytes++; // OK?
switch(mod) {
case 0: // replace