drm/msm/dp: DisplayPort PHY compliance tests fixup

Bandwidth code was being used as test link rate. Fix this by converting
bandwidth code to test link rate

Do not reset voltage and pre-emphasis level during IRQ HPD attention
interrupt. Also fix pre-emphasis parsing during test link status process

Signed-off-by: Tanmay Shah <tanmay@codeaurora.org>
Fixes: 8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets")
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 2e3e191..872b126 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -1643,9 +1643,6 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
        if (rc)
                return rc;
 
-       ctrl->link->phy_params.p_level = 0;
-       ctrl->link->phy_params.v_level = 0;
-
        while (--link_train_max_retries &&
                !atomic_read(&ctrl->dp_ctrl.aborted)) {
                rc = dp_ctrl_reinitialize_mainlink(ctrl);

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index e175aa3..ae9989e 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -335,6 +335,7 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp)
        dp->dp_display.max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ;
        dp->dp_display.max_dp_lanes = dp->parser->max_dp_lanes;
 
+       dp_link_reset_phy_params_vx_px(dp->link);
        rc = dp_ctrl_on_link(dp->ctrl);
        if (rc) {
                DRM_ERROR("failed to complete DP link training\n");

diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c
index c811da5..49d7fad 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_link.c
+++ b/drivers/gpu/drm/msm/dp/dp_link.c
@@ -869,6 +869,9 @@ static int dp_link_parse_vx_px(struct dp_link_private *link)
                drm_dp_get_adjust_request_voltage(link->link_status, 0);
        link->dp_link.phy_params.p_level =
                drm_dp_get_adjust_request_pre_emphasis(link->link_status, 0);
+
+       link->dp_link.phy_params.p_level >>= DP_TRAIN_PRE_EMPHASIS_SHIFT;
+
        DRM_DEBUG_DP("Requested: v_level = 0x%x, p_level = 0x%x\n",
                        link->dp_link.phy_params.v_level,
                        link->dp_link.phy_params.p_level);
@@ -911,7 +914,8 @@ static int dp_link_process_phy_test_pattern_request(
                        link->request.test_lane_count);
 
        link->dp_link.link_params.num_lanes = link->request.test_lane_count;
-       link->dp_link.link_params.rate = link->request.test_link_rate;
+       link->dp_link.link_params.rate =
+               drm_dp_bw_code_to_link_rate(link->request.test_link_rate);
 
        ret = dp_link_parse_vx_px(link);
 
@@ -1156,6 +1160,12 @@ int dp_link_adjust_levels(struct dp_link *dp_link, u8 *link_status)
        return 0;
 }
 
+void dp_link_reset_phy_params_vx_px(struct dp_link *dp_link)
+{
+       dp_link->phy_params.v_level = 0;
+       dp_link->phy_params.p_level = 0;
+}
+
 u32 dp_link_get_test_bits_depth(struct dp_link *dp_link, u32 bpp)
 {
        u32 tbd;

diff --git a/drivers/gpu/drm/msm/dp/dp_link.h b/drivers/gpu/drm/msm/dp/dp_link.h
index 49811b6..9dd4dd9 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_link.h
+++ b/drivers/gpu/drm/msm/dp/dp_link.h
@@ -135,6 +135,7 @@ static inline u32 dp_link_bit_depth_to_bpc(u32 tbd)
        }
 }
 
+void dp_link_reset_phy_params_vx_px(struct dp_link *dp_link);
 u32 dp_link_get_test_bits_depth(struct dp_link *dp_link, u32 bpp);
 int dp_link_process_request(struct dp_link *dp_link);
 int dp_link_get_colorimetry_config(struct dp_link *dp_link);