// Remove the load, if the destination register of the loads is the same
// register for stored value.
if (StRt == LdRt && LoadSize == 8) {
- StoreI->clearRegisterKills(StRt, TRI);
+ for (MachineInstr &MI : make_range(StoreI->getIterator(),
+ LoadI->getIterator())) {
+ if (MI.killsRegister(StRt, TRI)) {
+ MI.clearRegisterKills(StRt, TRI);
+ break;
+ }
+ }
DEBUG(dbgs() << "Remove load instruction:\n ");
DEBUG(LoadI->print(dbgs()));
DEBUG(dbgs() << "\n");
# CHECK: UBFMWri undef %w1
# CHECK: STRHHui undef %w3
# CHECK: ANDWri undef %w3
+---
+name: promote-load-from-store-trivial-kills
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: %x0, %lr
+
+ STRXui %x0, %sp, 0 :: (store 8)
+ STRXui killed %x0, %sp, 2 :: (store 8)
+ %x0 = LDRXui %sp, 0 :: (load 8)
+ BL $bar, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit-def %sp
+ RET %lr
+...
+# CHECK-LABEL: name: promote-load-from-store-trivial-kills
+# CHECK: STRXui %x0, %sp, 0
+# CHECK: STRXui %x0, %sp, 2
+# CHECK-NOT: LDRXui
+# CHECK-NOT: ORR
+# CHECK: BL $bar, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit-def %sp