struct mdss_pll_resources *rsc;
struct dsi_pll_config pll_configuration;
struct dsi_pll_regs reg_setup;
- int bitclk_src_div;
};
static struct mdss_pll_resources *pll_rsc_db[DSI_PLL_MAX];
u32 frac;
u64 multiplier;
- target_freq = rsc->vco_current_rate / pll->bitclk_src_div;
+ target_freq = rsc->vco_current_rate;
pr_debug("target_freq = %llu\n", target_freq);
if (config->div_override) {
wmb();
}
-static int vco_cobalt_set_rate_sub(struct mdss_pll_resources *rsc)
+static int vco_cobalt_set_rate(struct clk *c, unsigned long rate)
{
int rc;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *rsc = vco->priv;
struct dsi_pll_cobalt *pll;
if (!rsc) {
return -EINVAL;
}
- if (!rsc->vco_current_rate) {
- pr_debug("vco rate not configured yet\n");
- return 0;
- }
-
if (rsc->pll_on)
return 0;
return -EINVAL;
}
+ pr_debug("ndx=%d, rate=%lu\n", rsc->index, rate);
+
+ rsc->vco_current_rate = rate;
+ rsc->vco_ref_clk_rate = vco->ref_clk_rate;
+
rc = mdss_pll_resource_enable(rsc, true);
if (rc) {
pr_err("failed to enable mdss dsi pll(%d), rc=%d\n",
mdss_pll_resource_enable(rsc, false);
- return rc;
-}
-
-static int vco_cobalt_set_rate(struct clk *c, unsigned long rate)
-{
- struct dsi_pll_vco_clk *vco = to_vco_clk(c);
- struct mdss_pll_resources *rsc = vco->priv;
-
- if (!rsc) {
- pr_err("pll resource not found\n");
- return -EINVAL;
- }
-
- pr_debug("ndx=%d, rate=%lu\n", rsc->index, rate);
-
- rsc->vco_current_rate = rate;
- rsc->vco_ref_clk_rate = vco->ref_clk_rate;
-
- return vco_cobalt_set_rate_sub(rsc);
+ return 0;
}
static int dsi_pll_cobalt_lock_status(struct mdss_pll_resources *pll)
reg_val = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG0);
reg_val &= ~0x0F;
- reg_val |= (div - 1);
+ reg_val |= div;
MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG0, reg_val);
}
return rc;
}
- /*
- * Once the bit clock source divider is setup, we may need to
- * re-configure the rest of the VCO registers if this divider value
- * has changed.
- */
- if (pll->bitclk_src_div != div) {
- pll->bitclk_src_div = div;
- rc = vco_cobalt_set_rate_sub(rsc);
- if (rc)
- goto error;
- }
-
bit_clk_set_div_sub(rsc, div);
+ /* For slave PLL, this divider always should be set to 1 */
if (rsc->slave)
- bit_clk_set_div_sub(rsc->slave, div);
+ bit_clk_set_div_sub(rsc->slave, 1);
(void)mdss_pll_resource_enable(rsc, false);
-error:
return rc;
}