after fixing the i386 case

Change-Id: If6fe0b6ec01f111115fb734fe31c0e152dbc165f

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315311 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 0f6a27e..d35c188 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -8028,8 +8028,8 @@ static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
   // output register, mark it as legal and catch the pattern in instruction
   // selection to avoid emitting extra insturctions (for zeroing upper bits).
   if (SDValue Promoted = isTypePromotionOfi1ZeroUpBits(Op)) {
-    SDValue ZeroC = DAG.getConstant(0, dl, MVT::i64);
-    SDValue AllZeros = DAG.getSplatBuildVector(ResVT, dl, ZeroC);
+    SDValue ZeroC = DAG.getIntPtrConstant(0, dl);
+    SDValue AllZeros = getZeroVector(ResVT, Subtarget, DAG, dl);
     return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, AllZeros, Promoted,
                        ZeroC);
   }