ARM: dts: sun8i: r40: add node for CAN controller

Allwinner R40 (also known as A40i, T3, V40) has a CAN controller. The
controller is the same as in earlier A10 and A20 SoCs, but needs reset
line to be deasserted before use.

This patch adds a CAN node and the corresponding pinctrl descriptions.

Link: https://lore.kernel.org/all/20211122104616.537156-4-boger@wirenboard.com
Signed-off-by: Evgeny Boger <boger@wirenboard.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 1d87fc0..c99c92f 100644 (file)
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -511,6 +511,16 @@
                        #interrupt-cells = <3>;
                        #gpio-cells = <3>;
 
+                       can_ph_pins: can-ph-pins {
+                               pins = "PH20", "PH21";
+                               function = "can";
+                       };
+
+                       can_pa_pins: can-pa-pins {
+                               pins = "PA16", "PA17";
+                               function = "can";
+                       };
+
                        clk_out_a_pin: clk-out-a-pin {
                                pins = "PI12";
                                function = "clk_out_a";
@@ -926,6 +936,15 @@
                        #size-cells = <0>;
                };
 
+               can0: can@1c2bc00 {
+                       compatible = "allwinner,sun8i-r40-can";
+                       reg = <0x01c2bc00 0x400>;
+                       interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_CAN>;
+                       resets = <&ccu RST_BUS_CAN>;
+                       status = "disabled";
+               };
+
                i2c4: i2c@1c2c000 {
                        compatible = "allwinner,sun6i-a31-i2c";
                        reg = <0x01c2c000 0x400>;