static const XtensaConfig dc232b = {
.name = "dc232b",
- .options = XTENSA_OPTIONS,
.gdb_regmap = {
.num_regs = 120,
.num_core_regs = 52,
#include "core-dc232b/gdb-config.c"
}
},
- .nareg = XCHAL_NUM_AREGS,
- .ndepc = 1,
- EXCEPTIONS_SECTION,
- INTERRUPTS_SECTION,
- TLB_SECTION,
- DEBUG_SECTION,
.clock_freq_khz = 10000,
+ DEFAULT_SECTIONS
};
REGISTER_CORE(dc232b)
static const XtensaConfig dc233c = {
.name = "dc233c",
- .options = XTENSA_OPTIONS,
.gdb_regmap = {
.num_regs = 121,
.num_core_regs = 52,
#include "core-dc233c/gdb-config.c"
}
},
- .nareg = XCHAL_NUM_AREGS,
- .ndepc = 1,
- EXCEPTIONS_SECTION,
- INTERRUPTS_SECTION,
- TLB_SECTION,
- DEBUG_SECTION,
.clock_freq_khz = 10000,
+ DEFAULT_SECTIONS
};
REGISTER_CORE(dc233c)
static const XtensaConfig fsf = {
.name = "fsf",
- .options = XTENSA_OPTIONS,
/* GDB for this core is not supported currently */
- .nareg = XCHAL_NUM_AREGS,
- .ndepc = 1,
- EXCEPTIONS_SECTION,
- INTERRUPTS_SECTION,
- TLB_SECTION,
- DEBUG_SECTION,
.clock_freq_khz = 10000,
+ DEFAULT_SECTIONS
};
REGISTER_CORE(fsf)
.nibreak = XCHAL_NUM_IBREAK, \
.ndbreak = XCHAL_NUM_DBREAK
+#define DEFAULT_SECTIONS \
+ .options = XTENSA_OPTIONS, \
+ .nareg = XCHAL_NUM_AREGS, \
+ .ndepc = (XCHAL_XEA_VERSION >= 2), \
+ EXCEPTIONS_SECTION, \
+ INTERRUPTS_SECTION, \
+ TLB_SECTION, \
+ DEBUG_SECTION
+
+
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0
#endif