Rename register classes to be upper case to make it obvious that they are X86

specific in the tree patterns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7578 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 354bf42..add8e45 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -254,14 +254,14 @@ X86RegisterInfo::getRegClassForType(const Type* Ty) const {
   default:              assert(0 && "Invalid type to getClass!");
   case Type::BoolTyID:
   case Type::SByteTyID:
-  case Type::UByteTyID:   return &r8Instance;
+  case Type::UByteTyID:   return &R8Instance;
   case Type::ShortTyID:
-  case Type::UShortTyID:  return &r16Instance;
+  case Type::UShortTyID:  return &R16Instance;
   case Type::IntTyID:
   case Type::UIntTyID:
-  case Type::PointerTyID: return &r32Instance;
+  case Type::PointerTyID: return &R32Instance;
     
   case Type::FloatTyID:
-  case Type::DoubleTyID: return &rFPInstance;
+  case Type::DoubleTyID: return &RFPInstance;
   }
 }

diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 5428686..e08b089 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -69,8 +69,8 @@ def : RegisterAliases<SP, [ESP]>;     def : RegisterAliases<BP, [EBP]>;
 // top-level register classes.  The order specified in the register list is
 // implicitly defined to be the register allocation order.
 //
-def r8  : RegisterClass<i8,  1, [AL, CL, DL, BL, AH, CH, DH, BH]>;
-def r16 : RegisterClass<i16, 2, [AX, CX, DX, BX, SI, DI, BP, SP]> {
+def R8  : RegisterClass<i8,  1, [AL, CL, DL, BL, AH, CH, DH, BH]>;
+def R16 : RegisterClass<i16, 2, [AX, CX, DX, BX, SI, DI, BP, SP]> {
   let Methods = [{
     iterator allocation_order_end(MachineFunction &MF) const {
       if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
@@ -81,7 +81,7 @@ def r16 : RegisterClass<i16, 2, [AX, CX, DX, BX, SI, DI, BP, SP]> {
   }];
 }
 
-def r32 : RegisterClass<i32, 4, [EAX, ECX, EDX, EBX, ESI, EDI, EBP, ESP]> {
+def R32 : RegisterClass<i32, 4, [EAX, ECX, EDX, EBX, ESI, EDI, EBP, ESP]> {
   let Methods = [{
     iterator allocation_order_end(MachineFunction &MF) const {
       if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
@@ -92,7 +92,7 @@ def r32 : RegisterClass<i32, 4, [EAX, ECX, EDX, EBX, ESI, EDI, EBP, ESP]> {
   }];
 }
 
-def rFP : RegisterClass<f80, 4, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
+def RFP : RegisterClass<f80, 4, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
 
 // Registers which cannot be allocated... and are thus left unnamed.
 def : RegisterClass<f80, 4, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]>;