drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw xlut_set()

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c
index 412270e..d497bd0 100644 (file)
--- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c
@@ -114,7 +114,8 @@ base507c_xlut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
        if ((ret = PUSH_WAIT(push, 2)))
                return ret;
 
-       PUSH_NVSQ(push, NV507C, 0x00e0, 0x40000000);
+       PUSH_MTHD(push, NV507C, SET_BASE_LUT_LO,
+                 NVDEF(NV507C, SET_BASE_LUT_LO, ENABLE, USE_CORE_LUT));
        return 0;
 }
 

diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c
index e962234..2fb033c 100644 (file)
--- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c
@@ -72,11 +72,16 @@ base907c_xlut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
        if ((ret = PUSH_WAIT(push, 6)))
                return ret;
 
-       PUSH_NVSQ(push, NV907C, 0x00e0, asyw->xlut.i.enable << 30 |
-                                       asyw->xlut.i.mode << 24,
-                               0x00e4, asyw->xlut.i.offset >> 8,
-                               0x00e8, 0x40000000);
-       PUSH_NVSQ(push, NV907C, 0x00fc, asyw->xlut.handle);
+       PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO,
+                 NVVAL(NV907C, SET_BASE_LUT_LO, ENABLE, asyw->xlut.i.enable) |
+                 NVVAL(NV907C, SET_BASE_LUT_LO, MODE, asyw->xlut.i.mode),
+
+                               SET_BASE_LUT_HI, asyw->xlut.i.offset >> 8,
+
+                               SET_OUTPUT_LUT_LO,
+                 NVDEF(NV907C, SET_OUTPUT_LUT_LO, ENABLE, USE_CORE_LUT));
+
+       PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, asyw->xlut.handle);
        return 0;
 }
 
@@ -86,8 +91,12 @@ base907c_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, int size)
        if (size != 256 && size != 1024)
                return false;
 
-       asyw->xlut.i.mode = size == 1024 ? 4 : 7;
-       asyw->xlut.i.enable = 2;
+       if (size == 1024)
+               asyw->xlut.i.mode = NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE;
+       else
+               asyw->xlut.i.mode = NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE;
+
+       asyw->xlut.i.enable = NV907C_SET_BASE_LUT_LO_ENABLE_ENABLE;
        asyw->xlut.i.load = head907d_olut_load;
        return true;
 }

diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
index b72170d..942b68e 100644 (file)
--- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
@@ -72,11 +72,13 @@ wndwc37e_ilut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
        if ((ret = PUSH_WAIT(push, 4)))
                return ret;
 
-       PUSH_NVSQ(push, NVC37E, 0x02b0, asyw->xlut.i.output_mode << 8 |
-                                       asyw->xlut.i.range << 4 |
-                                       asyw->xlut.i.size,
-                               0x02b4, asyw->xlut.i.offset >> 8,
-                               0x02b8, asyw->xlut.handle);
+       PUSH_MTHD(push, NVC37E, SET_CONTROL_INPUT_LUT,
+                 NVVAL(NVC37E, SET_CONTROL_INPUT_LUT, OUTPUT_MODE, asyw->xlut.i.output_mode) |
+                 NVVAL(NVC37E, SET_CONTROL_INPUT_LUT, RANGE, asyw->xlut.i.range) |
+                 NVVAL(NVC37E, SET_CONTROL_INPUT_LUT, SIZE, asyw->xlut.i.size),
+
+                               SET_OFFSET_INPUT_LUT, asyw->xlut.i.offset >> 8,
+                               SET_CONTEXT_DMA_INPUT_LUT, asyw->xlut.handle);
        return 0;
 }
 
@@ -86,10 +88,10 @@ wndwc37e_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, int size)
        if (size != 256 && size != 1024)
                return false;
 
-       asyw->xlut.i.mode = 2;
-       asyw->xlut.i.size = size == 1024 ? 2 : 0;
-       asyw->xlut.i.range = 0;
-       asyw->xlut.i.output_mode = 1;
+       asyw->xlut.i.size = size == 1024 ? NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_1025 :
+                                          NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_257;
+       asyw->xlut.i.range = NVC37E_SET_CONTROL_INPUT_LUT_RANGE_UNITY;
+       asyw->xlut.i.output_mode = NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INTERPOLATE;
        asyw->xlut.i.load = head907d_olut_load;
        return true;
 }

diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
index 1da5ffb..86c50ed 100644 (file)
--- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
@@ -113,11 +113,13 @@ wndwc57e_ilut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
        if ((ret = PUSH_WAIT(push, 4)))
                return ret;
 
-       PUSH_NVSQ(push, NVC57E, 0x0440, asyw->xlut.i.size << 8 |
-                                       asyw->xlut.i.mode << 2 |
-                                       asyw->xlut.i.output_mode,
-                               0x0444, asyw->xlut.handle,
-                               0x0448, asyw->xlut.i.offset >> 8);
+       PUSH_MTHD(push, NVC57E, SET_ILUT_CONTROL,
+                 NVVAL(NVC57E, SET_ILUT_CONTROL, SIZE, asyw->xlut.i.size) |
+                 NVVAL(NVC57E, SET_ILUT_CONTROL, MODE, asyw->xlut.i.mode) |
+                 NVVAL(NVC57E, SET_ILUT_CONTROL, INTERPOLATE, asyw->xlut.i.output_mode),
+
+                               SET_CONTEXT_DMA_ILUT, asyw->xlut.handle,
+                               SET_OFFSET_ILUT, asyw->xlut.i.offset >> 8);
        return 0;
 }
 
@@ -163,13 +165,13 @@ wndwc57e_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, int size)
        if (size = size ? size : 1024, size != 256 && size != 1024)
                return false;
 
-       if (size == 256) {
-               asyw->xlut.i.mode = 1; /* DIRECT8. */
-       } else {
-               asyw->xlut.i.mode = 2; /* DIRECT10. */
-       }
+       if (size == 256)
+               asyw->xlut.i.mode = NVC57E_SET_ILUT_CONTROL_MODE_DIRECT8;
+       else
+               asyw->xlut.i.mode = NVC57E_SET_ILUT_CONTROL_MODE_DIRECT10;
+
        asyw->xlut.i.size = 4 /* VSS header. */ + size + 1 /* Entries. */;
-       asyw->xlut.i.output_mode = 0; /* INTERPOLATE_DISABLE. */
+       asyw->xlut.i.output_mode = NVC57E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE;
        asyw->xlut.i.load = wndwc57e_ilut_load;
        return true;
 }